Merge branch '4.3-fixes' into mips-for-linux-next
authorRalf Baechle <ralf@linux-mips.org>
Thu, 12 Nov 2015 10:36:03 +0000 (11:36 +0100)
committerRalf Baechle <ralf@linux-mips.org>
Thu, 12 Nov 2015 10:36:03 +0000 (11:36 +0100)
1  2 
arch/mips/kernel/idle.c
arch/mips/kernel/traps.c
arch/mips/kernel/vmlinux.lds.S

diff --combined arch/mips/kernel/idle.c
index 35af61530de1b4e9b5525606006b3d88575383aa,d636c70fef19932ce557d32c5aa7b274026928ae..46794d64c0bfe3f9779cc43714cc7c3fbb6a10bc
@@@ -134,16 -134,6 +134,16 @@@ void __init check_wait(void
                return;
        }
  
 +      /*
 +       * MIPSr6 specifies that masked interrupts should unblock an executing
 +       * wait instruction, and thus that it is safe for us to use
 +       * r4k_wait_irqoff. Yippee!
 +       */
 +      if (cpu_has_mips_r6) {
 +              cpu_wait = r4k_wait_irqoff;
 +              return;
 +      }
 +
        switch (current_cpu_type()) {
        case CPU_R3081:
        case CPU_R3081E:
        case CPU_4KEC:
        case CPU_4KSC:
        case CPU_5KC:
 +      case CPU_5KE:
        case CPU_25KF:
        case CPU_PR4450:
        case CPU_BMIPS3300:
        case CPU_BMIPS4350:
        case CPU_BMIPS4380:
-       case CPU_BMIPS5000:
        case CPU_CAVIUM_OCTEON:
        case CPU_CAVIUM_OCTEON_PLUS:
        case CPU_CAVIUM_OCTEON2:
        case CPU_XLP:
                cpu_wait = r4k_wait;
                break;
+       case CPU_BMIPS5000:
+               cpu_wait = r4k_wait_irqoff;
+               break;
        case CPU_RM7000:
                cpu_wait = rm7k_wait_irqoff;
                break;
        case CPU_INTERAPTIV:
        case CPU_M5150:
        case CPU_QEMU_GENERIC:
 -      case CPU_I6400:
                cpu_wait = r4k_wait;
                if (read_c0_config7() & MIPS_CONF7_WII)
                        cpu_wait = r4k_wait_irqoff;
diff --combined arch/mips/kernel/traps.c
index 4e106d52f30410c0abc24eba7ff866d62af13a16,efcedd43780fbf4a34c71bb215a4932145d2cfc4..886cb1976e90f682dafac7a958043d68bc4b6473
@@@ -37,7 -37,6 +37,7 @@@
  #include <linux/irq.h>
  #include <linux/perf_event.h>
  
 +#include <asm/addrspace.h>
  #include <asm/bootinfo.h>
  #include <asm/branch.h>
  #include <asm/break.h>
@@@ -1857,12 -1856,14 +1857,14 @@@ void __noreturn nmi_exception_handler(s
  {
        char str[100];
  
+       nmi_enter();
        raw_notifier_call_chain(&nmi_chain, 0, regs);
        bust_spinlocks(1);
        snprintf(str, 100, "CPU%d NMI taken, CP0_EPC=%lx\n",
                 smp_processor_id(), regs->cp0_epc);
        regs->cp0_epc = read_c0_errorepc();
        die(str, regs);
+       nmi_exit();
  }
  
  #define VECTORSPACING 0x100   /* for EI/VI mode */
@@@ -2205,8 -2206,12 +2207,8 @@@ void __init trap_init(void
                ebase = (unsigned long)
                        __alloc_bootmem(size, 1 << fls(size), 0);
        } else {
 -#ifdef CONFIG_KVM_GUEST
 -#define KVM_GUEST_KSEG0     0x40000000
 -        ebase = KVM_GUEST_KSEG0;
 -#else
 -        ebase = CKSEG0;
 -#endif
 +              ebase = CAC_BASE;
 +
                if (cpu_has_mips_r2_r6)
                        ebase += (read_c0_ebase() & 0x3ffff000);
        }
index f4c23d9023be1f7acfadbba66bf9b05a079a60b8,cce2fcb58881f48cc071230698c4da85a8350360..0a93e83cd01479a4abc952e2e41a853dbf4159b9
@@@ -17,7 -17,9 +17,9 @@@ OUTPUT_ARCH(mips
  ENTRY(kernel_entry)
  PHDRS {
        text PT_LOAD FLAGS(7);  /* RWX */
+ #ifndef CONFIG_CAVIUM_OCTEON_SOC
        note PT_NOTE FLAGS(4);  /* R__ */
+ #endif /* CAVIUM_OCTEON_SOC */
  }
  
  #ifdef CONFIG_32BIT
@@@ -71,7 -73,12 +73,12 @@@ SECTION
                __stop___dbe_table = .;
        }
  
-       NOTES :text :note
+ #ifdef CONFIG_CAVIUM_OCTEON_SOC
+ #define NOTES_HEADER
+ #else /* CONFIG_CAVIUM_OCTEON_SOC */
+ #define NOTES_HEADER :note
+ #endif /* CONFIG_CAVIUM_OCTEON_SOC */
+       NOTES :text NOTES_HEADER
        .dummy : { *(.dummy) } :text
  
        _sdata = .;                     /* Start of data section */
        __appended_dtb = .;
        /* leave space for appended DTB */
        . += 0x100000;
 +#elif defined(CONFIG_MIPS_ELF_APPENDED_DTB)
 +      .appended_dtb : AT(ADDR(.appended_dtb) - LOAD_OFFSET) {
 +              *(.appended_dtb)
 +              KEEP(*(.appended_dtb))
 +      }
  #endif
        /*
         * Align to 64K in attempt to eliminate holes before the
        DISCARDS
        /DISCARD/ : {
                /* ABI crap starts here */
+               *(.MIPS.abiflags)
                *(.MIPS.options)
                *(.options)
                *(.pdr)