arch/mips/kernel/idle.c

   1 /*
   2  * MIPS idle loop and WAIT instruction support.
   3  *
   4  * Copyright (C) xxxx  the Anonymous
   5  * Copyright (C) 1994 - 2006 Ralf Baechle
   6  * Copyright (C) 2003, 2004  Maciej W. Rozycki
   7  * Copyright (C) 2001, 2004, 2011, 2012  MIPS Technologies, Inc.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or (at your option) any later version.
  13  */
  14 #include <linux/export.h>
  15 #include <linux/init.h>
  16 #include <linux/irqflags.h>
  17 #include <linux/printk.h>
  18 #include <linux/sched.h>
  19 #include <asm/cpu.h>
  20 #include <asm/cpu-info.h>
  21 #include <asm/cpu-type.h>
  22 #include <asm/idle.h>
  23 #include <asm/mipsregs.h>
  24
  25 /*
  26  * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
  27  * the implementation of the "wait" feature differs between CPU families. This
  28  * points to the function that implements CPU specific wait.
  29  * The wait instruction stops the pipeline and reduces the power consumption of
  30  * the CPU very much.
  31  */
  32 void (*cpu_wait)(void);
  33 EXPORT_SYMBOL(cpu_wait);
  34
  35 static void r3081_wait(void)
  36 {
  37         unsigned long cfg = read_c0_conf();
  38         write_c0_conf(cfg | R30XX_CONF_HALT);
  39         local_irq_enable();
  40 }
  41
  42 static void r39xx_wait(void)
  43 {
  44         if (!need_resched())
  45                 write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
  46         local_irq_enable();
  47 }
  48
  49 void r4k_wait(void)
  50 {
  51         local_irq_enable();
  52         __r4k_wait();
  53 }
  54
  55 /*
  56  * This variant is preferable as it allows testing need_resched and going to
  57  * sleep depending on the outcome atomically.  Unfortunately the "It is
  58  * implementation-dependent whether the pipeline restarts when a non-enabled
  59  * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
  60  * using this version a gamble.
  61  */
  62 void r4k_wait_irqoff(void)
  63 {
  64         if (!need_resched())
  65                 __asm__(
  66                 "       .set    push            \n"
  67                 "       .set    arch=r4000      \n"
  68                 "       wait                    \n"
  69                 "       .set    pop             \n");
  70         local_irq_enable();
  71 }
  72
  73 /*
  74  * The RM7000 variant has to handle erratum 38.  The workaround is to not
  75  * have any pending stores when the WAIT instruction is executed.
  76  */
  77 static void rm7k_wait_irqoff(void)
  78 {
  79         if (!need_resched())
  80                 __asm__(
  81                 "       .set    push                                    \n"
  82                 "       .set    arch=r4000                              \n"
  83                 "       .set    noat                                    \n"
  84                 "       mfc0    $1, $12                                 \n"
  85                 "       sync                                            \n"
  86                 "       mtc0    $1, $12         # stalls until W stage  \n"
  87                 "       wait                                            \n"
  88                 "       mtc0    $1, $12         # stalls until W stage  \n"
  89                 "       .set    pop                                     \n");
  90         local_irq_enable();
  91 }
  92
  93 /*
  94  * Au1 'wait' is only useful when the 32kHz counter is used as timer,
  95  * since coreclock (and the cp0 counter) stops upon executing it. Only an
  96  * interrupt can wake it, so they must be enabled before entering idle modes.
  97  */
  98 static void au1k_wait(void)
  99 {
 100         unsigned long c0status = read_c0_status() | 1;  /* irqs on */
 101
 102         __asm__(
 103         "       .set    arch=r4000                      \n"
 104         "       cache   0x14, 0(%0)             \n"
 105         "       cache   0x14, 32(%0)            \n"
 106         "       sync                            \n"
 107         "       mtc0    %1, $12                 \n" /* wr c0status */
 108         "       wait                            \n"
 109         "       nop                             \n"
 110         "       nop                             \n"
 111         "       nop                             \n"
 112         "       nop                             \n"
 113         "       .set    mips0                   \n"
 114         : : "r" (au1k_wait), "r" (c0status));
 115 }
 116
 117 static int __initdata nowait;
 118
 119 static int __init wait_disable(char *s)
 120 {
 121         nowait = 1;
 122
 123         return 1;
 124 }
 125
 126 __setup("nowait", wait_disable);
 127
 128 void __init check_wait(void)
 129 {
 130         struct cpuinfo_mips *c = &current_cpu_data;
 131
 132         if (nowait) {
 133                 printk("Wait instruction disabled.\n");
 134                 return;
 135         }
 136
 137         /*
 138          * MIPSr6 specifies that masked interrupts should unblock an executing
 139          * wait instruction, and thus that it is safe for us to use
 140          * r4k_wait_irqoff. Yippee!
 141          */
 142         if (cpu_has_mips_r6) {
 143                 cpu_wait = r4k_wait_irqoff;
 144                 return;
 145         }
 146
 147         switch (current_cpu_type()) {
 148         case CPU_R3081:
 149         case CPU_R3081E:
 150                 cpu_wait = r3081_wait;
 151                 break;
 152         case CPU_TX3927:
 153                 cpu_wait = r39xx_wait;
 154                 break;
 155         case CPU_R4200:
 156 /*      case CPU_R4300: */
 157         case CPU_R4600:
 158         case CPU_R4640:
 159         case CPU_R4650:
 160         case CPU_R4700:
 161         case CPU_R5000:
 162         case CPU_R5500:
 163         case CPU_NEVADA:
 164         case CPU_4KC:
 165         case CPU_4KEC:
 166         case CPU_4KSC:
 167         case CPU_5KC:
 168         case CPU_5KE:
 169         case CPU_25KF:
 170         case CPU_PR4450:
 171         case CPU_BMIPS3300:
 172         case CPU_BMIPS4350:
 173         case CPU_BMIPS4380:
 174         case CPU_CAVIUM_OCTEON:
 175         case CPU_CAVIUM_OCTEON_PLUS:
 176         case CPU_CAVIUM_OCTEON2:
 177         case CPU_CAVIUM_OCTEON3:
 178         case CPU_JZRISC:
 179         case CPU_LOONGSON1:
 180         case CPU_XLR:
 181         case CPU_XLP:
 182                 cpu_wait = r4k_wait;
 183                 break;
 184         case CPU_BMIPS5000:
 185                 cpu_wait = r4k_wait_irqoff;
 186                 break;
 187         case CPU_RM7000:
 188                 cpu_wait = rm7k_wait_irqoff;
 189                 break;
 190
 191         case CPU_PROAPTIV:
 192         case CPU_P5600:
 193                 /*
 194                  * Incoming Fast Debug Channel (FDC) data during a wait
 195                  * instruction causes the wait never to resume, even if an
 196                  * interrupt is received. Avoid using wait at all if FDC data is
 197                  * likely to be received.
 198                  */
 199                 if (IS_ENABLED(CONFIG_MIPS_EJTAG_FDC_TTY))
 200                         break;
 201                 /* fall through */
 202         case CPU_M14KC:
 203         case CPU_M14KEC:
 204         case CPU_24K:
 205         case CPU_34K:
 206         case CPU_1004K:
 207         case CPU_1074K:
 208         case CPU_INTERAPTIV:
 209         case CPU_M5150:
 210         case CPU_QEMU_GENERIC:
 211                 cpu_wait = r4k_wait;
 212                 if (read_c0_config7() & MIPS_CONF7_WII)
 213                         cpu_wait = r4k_wait_irqoff;
 214                 break;
 215
 216         case CPU_74K:
 217                 cpu_wait = r4k_wait;
 218                 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
 219                         cpu_wait = r4k_wait_irqoff;
 220                 break;
 221
 222         case CPU_TX49XX:
 223                 cpu_wait = r4k_wait_irqoff;
 224                 break;
 225         case CPU_ALCHEMY:
 226                 cpu_wait = au1k_wait;
 227                 break;
 228         case CPU_20KC:
 229                 /*
 230                  * WAIT on Rev1.0 has E1, E2, E3 and E16.
 231                  * WAIT on Rev2.0 and Rev3.0 has E16.
 232                  * Rev3.1 WAIT is nop, why bother
 233                  */
 234                 if ((c->processor_id & 0xff) <= 0x64)
 235                         break;
 236
 237                 /*
 238                  * Another rev is incremeting c0_count at a reduced clock
 239                  * rate while in WAIT mode.  So we basically have the choice
 240                  * between using the cp0 timer as clocksource or avoiding
 241                  * the WAIT instruction.  Until more details are known,
 242                  * disable the use of WAIT for 20Kc entirely.
 243                    cpu_wait = r4k_wait;
 244                  */
 245                 break;
 246         default:
 247                 break;
 248         }
 249 }
 250
 251 void arch_cpu_idle(void)
 252 {
 253         if (cpu_wait)
 254                 cpu_wait();
 255         else
 256                 local_irq_enable();
 257 }
 258
 259 #ifdef CONFIG_CPU_IDLE
 260
 261 int mips_cpuidle_wait_enter(struct cpuidle_device *dev,
 262                             struct cpuidle_driver *drv, int index)
 263 {
 264         arch_cpu_idle();
 265         return index;
 266 }
 267
 268 #endif