irqchip/gic: Kconfig the number of instances

There is currently a hack in the GIC driver making it possible
to pass the number of GIC instances from the platform-specific
include files and thus override the variable MAX_GIC_NR.

With multiplatform deployments, this will not work as we need
to get rid of the platform-specific include files.

It turns out that this feature is only used by the RealView
platform which has a cascaded GIC. So move the configuration
to Kconfig and bump to 2 instances if we're building for the
RealView. The include file hacks can then be removed.

Tested on the ARM PB11MPCore with its cascaded GIC.

Suggested-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>

diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 4d7294e5d98271493e0ef6d2d90d10108178c83f..bf29a8b2b7c56c91d046ed9e5d83aa18138d8710 100644 (file)
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -8,6 +8,11 @@ config ARM_GIC
        select IRQ_DOMAIN_HIERARCHY
        select MULTI_IRQ_HANDLER
 
+config ARM_GIC_MAX_NR
+       int
+       default 2 if ARCH_REALVIEW
+       default 1
+
 config ARM_GIC_V2M
        bool
        depends on ARM_GIC

diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 7f5f91984c1b0418f4fe6d63053efedb44936b3b..fcbe0b90870db8314756aae20571d82fee1b6ef9 100644 (file)
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -100,11 +100,7 @@ static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
 
 static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE;
 
-#ifndef MAX_GIC_NR
-#define MAX_GIC_NR     1
-#endif
-
-static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly;
+static struct gic_chip_data gic_data[CONFIG_ARM_GIC_MAX_NR] __read_mostly;
 
 #ifdef CONFIG_GIC_NON_BANKED
 static void __iomem *gic_get_percpu_base(union gic_base *base)
@@ -417,8 +413,7 @@ static struct irq_chip gic_eoimode1_chip = {
 
 void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
 {
-       if (gic_nr >= MAX_GIC_NR)
-               BUG();
+       BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
        irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq,
                                         &gic_data[gic_nr]);
 }
@@ -524,7 +519,7 @@ int gic_cpu_if_down(unsigned int gic_nr)
        void __iomem *cpu_base;
        u32 val = 0;
 
-       if (gic_nr >= MAX_GIC_NR)
+       if (gic_nr >= CONFIG_ARM_GIC_MAX_NR)
                return -EINVAL;
 
        cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
@@ -548,8 +543,7 @@ static void gic_dist_save(unsigned int gic_nr)
        void __iomem *dist_base;
        int i;
 
-       if (gic_nr >= MAX_GIC_NR)
-               BUG();
+       BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
 
        gic_irqs = gic_data[gic_nr].gic_irqs;
        dist_base = gic_data_dist_base(&gic_data[gic_nr]);
@@ -587,8 +581,7 @@ static void gic_dist_restore(unsigned int gic_nr)
        unsigned int i;
        void __iomem *dist_base;
 
-       if (gic_nr >= MAX_GIC_NR)
-               BUG();
+       BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
 
        gic_irqs = gic_data[gic_nr].gic_irqs;
        dist_base = gic_data_dist_base(&gic_data[gic_nr]);
@@ -634,8 +627,7 @@ static void gic_cpu_save(unsigned int gic_nr)
        void __iomem *dist_base;
        void __iomem *cpu_base;
 
-       if (gic_nr >= MAX_GIC_NR)
-               BUG();
+       BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
 
        dist_base = gic_data_dist_base(&gic_data[gic_nr]);
        cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
@@ -664,8 +656,7 @@ static void gic_cpu_restore(unsigned int gic_nr)
        void __iomem *dist_base;
        void __iomem *cpu_base;
 
-       if (gic_nr >= MAX_GIC_NR)
-               BUG();
+       BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
 
        dist_base = gic_data_dist_base(&gic_data[gic_nr]);
        cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
@@ -703,7 +694,7 @@ static int gic_notifier(struct notifier_block *self, unsigned long cmd,     void *v)
 {
        int i;
 
-       for (i = 0; i < MAX_GIC_NR; i++) {
+       for (i = 0; i < CONFIG_ARM_GIC_MAX_NR; i++) {
 #ifdef CONFIG_GIC_NON_BANKED
                /* Skip over unused GICs */
                if (!gic_data[i].get_base)
@@ -835,8 +826,7 @@ void gic_migrate_target(unsigned int new_cpu_id)
        int i, ror_val, cpu = smp_processor_id();
        u32 val, cur_target_mask, active_mask;
 
-       if (gic_nr >= MAX_GIC_NR)
-               BUG();
+       BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
 
        dist_base = gic_data_dist_base(&gic_data[gic_nr]);
        if (!dist_base)
@@ -1035,7 +1025,7 @@ static void __init __gic_init_bases(unsigned int gic_nr, int irq_start,
        struct gic_chip_data *gic;
        int gic_irqs, irq_base, i;
 
-       BUG_ON(gic_nr >= MAX_GIC_NR);
+       BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
 
        gic_check_cpu_features();