8 select IRQ_DOMAIN_HIERARCHY
9 select MULTI_IRQ_HANDLER
13 default 2 if ARCH_REALVIEW
19 depends on PCI && PCI_MSI
20 select PCI_MSI_IRQ_DOMAIN
28 select MULTI_IRQ_HANDLER
29 select IRQ_DOMAIN_HIERARCHY
33 select PCI_MSI_IRQ_DOMAIN
38 select IRQ_DOMAIN_HIERARCHY
39 select GENERIC_IRQ_CHIP
44 select MULTI_IRQ_HANDLER
48 default 4 if ARCH_S5PV210
52 The maximum number of VICs available in the system, for
57 select GENERIC_IRQ_CHIP
59 select MULTI_IRQ_HANDLER
64 select GENERIC_IRQ_CHIP
66 select MULTI_IRQ_HANDLER
75 select GENERIC_IRQ_CHIP
80 select GENERIC_IRQ_CHIP
85 select GENERIC_IRQ_CHIP
90 select GENERIC_IRQ_CHIP
95 select GENERIC_IRQ_CHIP
100 select GENERIC_IRQ_CHIP
103 config CLPS711X_IRQCHIP
105 depends on ARCH_CLPS711X
107 select MULTI_IRQ_HANDLER
117 select GENERIC_IRQ_CHIP
123 select MULTI_IRQ_HANDLER
125 config RENESAS_INTC_IRQPIN
131 select GENERIC_IRQ_CHIP
139 Enables SysCfg Controlled IRQs on STi based platforms.
144 select GENERIC_IRQ_CHIP
146 config VERSATILE_FPGA_IRQ
150 config VERSATILE_FPGA_IRQ_NR
153 depends on VERSATILE_FPGA_IRQ
162 Support for a CROSSBAR ip that precedes the main interrupt controller.
163 The primary irqchip invokes the crossbar's callback which inturn allocates
164 a free irq and configures the IP. Thus the peripheral interrupts are
165 routed to one of the free irqchip interrupt lines.
168 tristate "Keystone 2 IRQ controller IP"
169 depends on ARCH_KEYSTONE
171 Support for Texas Instruments Keystone 2 IRQ controller IP which
172 is part of the Keystone 2 IPC mechanism
180 depends on MACH_INGENIC
183 config RENESAS_H8300H_INTC
187 config RENESAS_H8S_INTC
195 Enables the wakeup IRQs for IMX platforms with GPCv2 block
198 def_bool y if MACH_ASM9260 || ARCH_MXS