dm: gpio: vf610: Add GPIO driver support
authorBhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Thu, 9 Apr 2015 14:17:21 +0000 (19:47 +0530)
committerStefan Agner <stefan.agner@toradex.com>
Wed, 22 Apr 2015 16:09:48 +0000 (18:09 +0200)
Add GPIO support to Freescale VF610

Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
arch/arm/imx-common/iomux-v3.c
arch/arm/include/asm/arch-vf610/gpio.h [new file with mode: 0644]
arch/arm/include/asm/arch-vf610/imx-regs.h
arch/arm/include/asm/imx-common/iomux-v3.h
drivers/gpio/Makefile
drivers/gpio/vybrid_gpio.c [new file with mode: 0644]

index e88e6e2a9881d0dcd00af5477453afe219ed79b1..22c536e0c398f85c91feae010b9152c807a0c625 100644 (file)
@@ -92,3 +92,22 @@ void imx_iomux_set_gpr_register(int group, int start_bit,
        reg |= (value << start_bit);
        writel(reg, base + group * 4);
 }
+
+#ifdef CONFIG_IOMUX_SHARE_CONF_REG
+void imx_iomux_gpio_set_direction(unsigned int gpio,
+                               unsigned int direction)
+{
+        u32 reg;
+       /*
+        * Only on Vybrid the input/output buffer enable flags
+        * are part of the shared mux/conf register.
+        */
+       reg = readl(base + (gpio << 2));
+        if(direction)
+                reg |= 0x2;
+        else
+               reg &= ~0x2;
+
+        writel(reg, (base + (gpio << 2)));
+}
+#endif
diff --git a/arch/arm/include/asm/arch-vf610/gpio.h b/arch/arm/include/asm/arch-vf610/gpio.h
new file mode 100644 (file)
index 0000000..57d50c3
--- /dev/null
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2015
+ * Bhuvanchandra DV, Toradex, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0
+ */
+
+#ifndef __ASM_ARCH_VF610_GPIO_H
+#define __ASM_ARCH_VF610_GPIO_H
+
+#define VYBRID_GPIO_COUNT              32
+#define VF610_GPIO_DIRECTION_IN                0x0
+#define VF610_GPIO_DIRECTION_OUT       0x1
+
+/* GPIO registers */
+struct vybrid_gpio_regs {
+       u32 gpio_pdor;
+       u32 gpio_psor;
+       u32 gpio_pcor;
+       u32 gpio_ptor;
+       u32 gpio_pdir;
+};
+
+struct vybrid_gpio_platdata {
+       unsigned int chip;
+       u32 base;
+};
+#endif /* __ASM_ARCH_VF610_GPIO_H */
index 512bc1fdb53b0df05bb8b1ce0e21edb56052753f..5ca3abba587d473fb36097eca58d55374d6e4a22 100644 (file)
 #define VREG_DIG_BASE_ADDR     (AIPS0_BASE_ADDR + 0x0006D000)
 #define SRC_BASE_ADDR          (AIPS0_BASE_ADDR + 0x0006E000)
 #define CMU_BASE_ADDR          (AIPS0_BASE_ADDR + 0x0006F000)
+#define GPIO0_BASE_ADDR                (AIPS0_BASE_ADDR + 0x000FF000)
+#define GPIO1_BASE_ADDR                (AIPS0_BASE_ADDR + 0x000FF040)
+#define GPIO2_BASE_ADDR                (AIPS0_BASE_ADDR + 0x000FF080)
+#define GPIO3_BASE_ADDR                (AIPS0_BASE_ADDR + 0x000FF0C0)
+#define GPIO4_BASE_ADDR                (AIPS0_BASE_ADDR + 0x000FF100)
 
 /* AIPS 1 */
 #define OCOTP_BASE_ADDR                (AIPS1_BASE_ADDR + 0x00025000)
index 5f161bb5f1976d5a7a177b078d18ee79575f8b98..a817b0cc03b2f92802f324ecf59bd4f6cba786b4 100644 (file)
@@ -190,6 +190,8 @@ void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
 */
 void imx_iomux_set_gpr_register(int group, int start_bit,
                                         int num_bits, int value);
+void imx_iomux_gpio_set_direction(unsigned int gpio,
+                               unsigned int direction);
 
 /* macros for declaring and using pinmux array */
 #if defined(CONFIG_MX6QDL)
index 85f71c5d4a773172ece61eecc3f9af6640231925..62c73042b76410ad9c00f83b6e7c827a49c1f8a9 100644 (file)
@@ -42,3 +42,4 @@ obj-$(CONFIG_TCA642X)         += tca642x.o
 oby-$(CONFIG_SX151X)           += sx151x.o
 obj-$(CONFIG_SUNXI_GPIO)       += sunxi_gpio.o
 obj-$(CONFIG_LPC32XX_GPIO)     += lpc32xx_gpio.o
+obj-$(CONFIG_VYBRID_GPIO)      += vybrid_gpio.o
diff --git a/drivers/gpio/vybrid_gpio.c b/drivers/gpio/vybrid_gpio.c
new file mode 100644 (file)
index 0000000..9fa0762
--- /dev/null
@@ -0,0 +1,122 @@
+/*
+ * Copyright (C) 2015
+ * Bhuvanchandra DV, Toradex, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/io.h>
+#include <malloc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct vybrid_gpios {
+       unsigned int chip;
+       struct vybrid_gpio_regs *reg;
+};
+
+static int vybrid_gpio_direction_input(struct udevice *dev, unsigned gpio)
+{
+       const struct vybrid_gpios *gpios = dev_get_priv(dev);
+
+       gpio = gpio + (gpios->chip * VYBRID_GPIO_COUNT);
+       imx_iomux_gpio_set_direction(gpio, VF610_GPIO_DIRECTION_IN);
+
+       return 0;
+}
+
+static int vybrid_gpio_direction_output(struct udevice *dev, unsigned gpio,
+                                        int value)
+{
+       const struct vybrid_gpios *gpios = dev_get_priv(dev);
+
+       gpio = gpio + (gpios->chip * VYBRID_GPIO_COUNT);
+       gpio_set_value(gpio, value);
+       imx_iomux_gpio_set_direction(gpio, VF610_GPIO_DIRECTION_OUT);
+
+       return 0;
+}
+
+static int vybrid_gpio_get_value(struct udevice *dev, unsigned gpio)
+{
+       const struct vybrid_gpios *gpios = dev_get_priv(dev);
+
+       return ((readl(&gpios->reg->gpio_pdir) & (1 << gpio))) ? 1 : 0;
+}
+
+static int vybrid_gpio_set_value(struct udevice *dev, unsigned gpio,
+                                 int value)
+{
+       const struct vybrid_gpios *gpios = dev_get_priv(dev);
+       if (value)
+               writel((1 << gpio), &gpios->reg->gpio_psor);
+       else
+               writel((1 << gpio), &gpios->reg->gpio_pcor);
+
+       return 0;
+}
+
+static const struct dm_gpio_ops gpio_vybrid_ops = {
+       .direction_input        = vybrid_gpio_direction_input,
+       .direction_output       = vybrid_gpio_direction_output,
+       .get_value              = vybrid_gpio_get_value,
+       .set_value              = vybrid_gpio_set_value,
+};
+
+static int vybrid_gpio_probe(struct udevice *dev)
+{
+       struct vybrid_gpios *gpios = dev_get_priv(dev);
+       struct vybrid_gpio_platdata *plat = dev_get_platdata(dev);
+       struct gpio_dev_priv *uc_priv = dev->uclass_priv;
+
+       uc_priv->bank_name = "GPIO";
+       uc_priv->gpio_count = VYBRID_GPIO_COUNT;
+       gpios->reg = (struct vybrid_gpio_regs *)plat->base;
+       gpios->chip = plat->chip;
+
+       return 0;
+}
+
+static int vybrid_gpio_bind(struct udevice *dev)
+{
+       struct vybrid_gpio_platdata *plat = dev->platdata;
+       fdt_addr_t base_addr;
+
+       if (plat)
+               return 0;
+
+       base_addr = dev_get_addr(dev);
+       if (base_addr == FDT_ADDR_T_NONE)
+               return -ENODEV;
+
+       plat = calloc(1, sizeof(*plat));
+       if (!plat)
+               return -ENOMEM;
+
+       plat->base = base_addr;
+       plat->chip = dev->req_seq;
+       dev->platdata = plat;
+
+       return 0;
+}
+
+static const struct udevice_id vybrid_gpio_ids[] = {
+       { .compatible = "fsl,vf610-gpio" },
+       { }
+};
+
+U_BOOT_DRIVER(gpio_vybrid) = {
+       .name   = "gpio_vybrid",
+       .id     = UCLASS_GPIO,
+       .ops    = &gpio_vybrid_ops,
+       .probe  = vybrid_gpio_probe,
+       .priv_auto_alloc_size = sizeof(struct vybrid_gpios),
+       .of_match = vybrid_gpio_ids,
+       .bind   = vybrid_gpio_bind,
+};