+++ /dev/null
-/*
- * Copyright (C) 2007-2008 Michal Simek <monstr@monstr.eu>
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-
-#ifndef _ASM_MICROBLAZE_SELFMOD_H
-#define _ASM_MICROBLAZE_SELFMOD_H
-
-/*
- * BARRIER_BASE_ADDR is constant address for selfmod function.
- * do not change this value - selfmod function is in
- * arch/microblaze/kernel/selfmod.c: selfmod_function()
- *
- * last 16 bits is used for storing register offset
- */
-
-#define BARRIER_BASE_ADDR 0x1234ff00
-
-void selfmod_function(const int *arr_fce, const unsigned int base);
-
-#endif /* _ASM_MICROBLAZE_SELFMOD_H */
CFLAGS_REMOVE_timer.o = -pg
CFLAGS_REMOVE_intc.o = -pg
CFLAGS_REMOVE_early_printk.o = -pg
-CFLAGS_REMOVE_selfmod.o = -pg
CFLAGS_REMOVE_heartbeat.o = -pg
CFLAGS_REMOVE_ftrace.o = -pg
CFLAGS_REMOVE_process.o = -pg
obj-y += cpu/
obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
-obj-$(CONFIG_SELFMOD) += selfmod.o
obj-$(CONFIG_HEART_BEAT) += heartbeat.o
obj-$(CONFIG_MODULES) += microblaze_ksyms.o module.o
obj-$(CONFIG_MMU) += misc.o
#include <asm/prom.h>
#include <asm/irq.h>
-#ifdef CONFIG_SELFMOD_INTC
-#include <asm/selfmod.h>
-#define INTC_BASE BARRIER_BASE_ADDR
-#else
static unsigned int intc_baseaddr;
-#define INTC_BASE intc_baseaddr
-#endif
/* No one else should require these constants, so define them locally here. */
#define ISR 0x00 /* Interrupt Status Register */
* acks the irq before calling the interrupt handler
*/
if (irqd_is_level_type(d))
- out_be32(INTC_BASE + IAR, mask);
+ out_be32(intc_baseaddr + IAR, mask);
- out_be32(INTC_BASE + SIE, mask);
+ out_be32(intc_baseaddr + SIE, mask);
}
static void intc_disable_or_mask(struct irq_data *d)
{
pr_debug("disable: %ld\n", d->hwirq);
- out_be32(INTC_BASE + CIE, 1 << d->hwirq);
+ out_be32(intc_baseaddr + CIE, 1 << d->hwirq);
}
static void intc_ack(struct irq_data *d)
{
pr_debug("ack: %ld\n", d->hwirq);
- out_be32(INTC_BASE + IAR, 1 << d->hwirq);
+ out_be32(intc_baseaddr + IAR, 1 << d->hwirq);
}
static void intc_mask_ack(struct irq_data *d)
unsigned long mask = 1 << d->hwirq;
pr_debug("disable_and_ack: %ld\n", d->hwirq);
- out_be32(INTC_BASE + CIE, mask);
- out_be32(INTC_BASE + IAR, mask);
+ out_be32(intc_baseaddr + CIE, mask);
+ out_be32(intc_baseaddr + IAR, mask);
}
static struct irq_chip intc_dev = {
{
unsigned int hwirq, irq = -1;
- hwirq = in_be32(INTC_BASE + IVR);
+ hwirq = in_be32(intc_baseaddr + IVR);
if (hwirq != -1U)
irq = irq_find_mapping(root_domain, hwirq);
{
u32 nr_irq, intr_mask;
struct device_node *intc = NULL;
-#ifdef CONFIG_SELFMOD_INTC
- unsigned int intc_baseaddr = 0;
- static int arr_func[] = {
- (int)&get_irq,
- (int)&intc_enable_or_unmask,
- (int)&intc_disable_or_mask,
- (int)&intc_mask_ack,
- (int)&intc_ack,
- (int)&intc_end,
- 0
- };
-#endif
+
intc = of_find_compatible_node(NULL, NULL, "xlnx,xps-intc-1.00.a");
BUG_ON(!intc);
if (intr_mask > (u32)((1ULL << nr_irq) - 1))
pr_info(" ERROR: Mismatch in kind-of-intr param\n");
-#ifdef CONFIG_SELFMOD_INTC
- selfmod_function((int *) arr_func, intc_baseaddr);
-#endif
pr_info("%s #0 at 0x%08x, num_irq=%d, edge=0x%x\n",
intc->name, intc_baseaddr, nr_irq, intr_mask);
+++ /dev/null
-/*
- * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
- * Copyright (C) 2009 PetaLogix
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-
-#include <linux/interrupt.h>
-#include <asm/selfmod.h>
-
-#undef DEBUG
-
-#if __GNUC__ > 3
-#error GCC 4 unsupported SELFMOD. Please disable SELFMOD from menuconfig.
-#endif
-
-#define OPCODE_IMM 0xB0000000
-#define OPCODE_LWI 0xE8000000
-#define OPCODE_LWI_MASK 0xEC000000
-#define OPCODE_RTSD 0xB60F0008 /* return from func: rtsd r15, 8 */
-#define OPCODE_ADDIK 0x30000000
-#define OPCODE_ADDIK_MASK 0xFC000000
-
-#define IMM_BASE (OPCODE_IMM | (BARRIER_BASE_ADDR >> 16))
-#define LWI_BASE (OPCODE_LWI | (BARRIER_BASE_ADDR & 0x0000ff00))
-#define LWI_BASE_MASK (OPCODE_LWI_MASK | (BARRIER_BASE_ADDR & 0x0000ff00))
-#define ADDIK_BASE (OPCODE_ADDIK | (BARRIER_BASE_ADDR & 0x0000ff00))
-#define ADDIK_BASE_MASK (OPCODE_ADDIK_MASK | (BARRIER_BASE_ADDR & 0x0000ff00))
-
-#define MODIFY_INSTR { \
- pr_debug("%s: curr instr, (%d):0x%x, next(%d):0x%x\n", \
- __func__, i, addr[i], i + 1, addr[i + 1]); \
- addr[i] = OPCODE_IMM + (base >> 16); \
- /* keep instruction opcode and add only last 16bits */ \
- addr[i + 1] = (addr[i + 1] & 0xffff00ff) + (base & 0xffff); \
- __invalidate_icache(addr[i]); \
- __invalidate_icache(addr[i + 1]); \
- pr_debug("%s: hack instr, (%d):0x%x, next(%d):0x%x\n", \
- __func__, i, addr[i], i + 1, addr[i + 1]); }
-
-/* NOTE
- * self-modified part of code for improvement of interrupt controller
- * save instruction in interrupt rutine
- */
-void selfmod_function(const int *arr_fce, const unsigned int base)
-{
- unsigned int flags, i, j, *addr = NULL;
-
- local_irq_save(flags);
- __disable_icache();
-
- /* zero terminated array */
- for (j = 0; arr_fce[j] != 0; j++) {
- /* get start address of function */
- addr = (unsigned int *) arr_fce[j];
- pr_debug("%s: func(%d) at 0x%x\n",
- __func__, j, (unsigned int) addr);
- for (i = 0; ; i++) {
- pr_debug("%s: instruction code at %d: 0x%x\n",
- __func__, i, addr[i]);
- if (addr[i] == IMM_BASE) {
- /* detecting of lwi (0xE8) or swi (0xF8) instr
- * I can detect both opcode with one mask */
- if ((addr[i + 1] & LWI_BASE_MASK) == LWI_BASE) {
- MODIFY_INSTR;
- } else /* detection addik for ack */
- if ((addr[i + 1] & ADDIK_BASE_MASK) ==
- ADDIK_BASE) {
- MODIFY_INSTR;
- }
- } else if (addr[i] == OPCODE_RTSD) {
- /* return from function means end of function */
- pr_debug("%s: end of array %d\n", __func__, i);
- break;
- }
- }
- }
- local_irq_restore(flags);
-} /* end of self-modified code */
xilinx_pci_init();
-#if defined(CONFIG_SELFMOD_INTC) || defined(CONFIG_SELFMOD_TIMER)
- pr_notice("Self modified code enable\n");
-#endif
-
#ifdef CONFIG_VT
#if defined(CONFIG_XILINX_CONSOLE)
conswitchp = &xil_con;
#include <asm/irq.h>
#include <linux/cnt32_to_63.h>
-#ifdef CONFIG_SELFMOD_TIMER
-#include <asm/selfmod.h>
-#define TIMER_BASE BARRIER_BASE_ADDR
-#else
static unsigned int timer_baseaddr;
-#define TIMER_BASE timer_baseaddr
-#endif
static unsigned int freq_div_hz;
static unsigned int timer_clock_freq;
static inline void microblaze_timer0_stop(void)
{
- out_be32(TIMER_BASE + TCSR0, in_be32(TIMER_BASE + TCSR0) & ~TCSR_ENT);
+ out_be32(timer_baseaddr + TCSR0,
+ in_be32(timer_baseaddr + TCSR0) & ~TCSR_ENT);
}
static inline void microblaze_timer0_start_periodic(unsigned long load_val)
{
if (!load_val)
load_val = 1;
- out_be32(TIMER_BASE + TLR0, load_val); /* loading value to timer reg */
+ /* loading value to timer reg */
+ out_be32(timer_baseaddr + TLR0, load_val);
/* load the initial value */
- out_be32(TIMER_BASE + TCSR0, TCSR_LOAD);
+ out_be32(timer_baseaddr + TCSR0, TCSR_LOAD);
/* see timer data sheet for detail
* !ENALL - don't enable 'em all
* UDT - set the timer as down counter
* !MDT0 - generate mode
*/
- out_be32(TIMER_BASE + TCSR0,
+ out_be32(timer_baseaddr + TCSR0,
TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT);
}
{
if (!load_val)
load_val = 1;
- out_be32(TIMER_BASE + TLR0, load_val); /* loading value to timer reg */
+ /* loading value to timer reg */
+ out_be32(timer_baseaddr + TLR0, load_val);
/* load the initial value */
- out_be32(TIMER_BASE + TCSR0, TCSR_LOAD);
+ out_be32(timer_baseaddr + TCSR0, TCSR_LOAD);
- out_be32(TIMER_BASE + TCSR0,
+ out_be32(timer_baseaddr + TCSR0,
TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT);
}
static inline void timer_ack(void)
{
- out_be32(TIMER_BASE + TCSR0, in_be32(TIMER_BASE + TCSR0));
+ out_be32(timer_baseaddr + TCSR0, in_be32(timer_baseaddr + TCSR0));
}
static irqreturn_t timer_interrupt(int irq, void *dev_id)
static cycle_t microblaze_read(struct clocksource *cs)
{
/* reading actual value of timer 1 */
- return (cycle_t) (in_be32(TIMER_BASE + TCR1));
+ return (cycle_t) (in_be32(timer_baseaddr + TCR1));
}
static struct timecounter microblaze_tc = {
panic("failed to register clocksource");
/* stop timer1 */
- out_be32(TIMER_BASE + TCSR1, in_be32(TIMER_BASE + TCSR1) & ~TCSR_ENT);
+ out_be32(timer_baseaddr + TCSR1,
+ in_be32(timer_baseaddr + TCSR1) & ~TCSR_ENT);
/* start timer1 - up counting without interrupt */
- out_be32(TIMER_BASE + TCSR1, TCSR_TINT|TCSR_ENT|TCSR_ARHT);
+ out_be32(timer_baseaddr + TCSR1, TCSR_TINT|TCSR_ENT|TCSR_ARHT);
/* register timecounter - for ftrace support */
init_microblaze_timecounter();
u32 timer_num = 1;
struct device_node *timer = NULL;
const void *prop;
-#ifdef CONFIG_SELFMOD_TIMER
- unsigned int timer_baseaddr = 0;
- int arr_func[] = {
- (int)µblaze_read,
- (int)&timer_interrupt,
- (int)µblaze_clocksource_init,
- (int)µblaze_timer_set_mode,
- (int)µblaze_timer_set_next_event,
- 0
- };
-#endif
+
prop = of_get_property(of_chosen, "system-timer", NULL);
if (prop)
timer = of_find_node_by_phandle(be32_to_cpup(prop));
BUG();
}
-#ifdef CONFIG_SELFMOD_TIMER
- selfmod_function((int *) arr_func, timer_baseaddr);
-#endif
pr_info("%s #0 at 0x%08x, irq=%d\n",
timer->name, timer_baseaddr, irq);
endchoice
-config SELFMOD
- bool "Use self modified code for intc/timer"
- depends on NO_MMU
- default n
- help
- This choice enables self-modified code for interrupt controller
- and timer.
-
-config SELFMOD_INTC
- bool "Use self modified code for intc"
- depends on SELFMOD
- default y
- help
- This choice enables self-modified code for interrupt controller.
-
-config SELFMOD_TIMER
- bool "Use self modified code for timer"
- depends on SELFMOD
- default y
- help
- This choice enables self-modified code for timer.
-
config OPT_LIB_FUNCTION
bool "Optimalized lib function"
default y
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