Merge tag 'tags/cleanup2-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm...
authorLinus Torvalds <torvalds@linux-foundation.org>
Sat, 5 Apr 2014 22:46:37 +0000 (15:46 -0700)
committerLinus Torvalds <torvalds@linux-foundation.org>
Sat, 5 Apr 2014 22:46:37 +0000 (15:46 -0700)
Pull ARM SoC late cleanups from Arnd Bergmann:
 "These could not be part of the first cleanup branch, because they
  either came too late in the cycle, or they have dependencies on other
  branches.  Important changes are:

   - The integrator platform is almost multiplatform capable after some
     reorganization (Linus Walleij)
   - Minor cleanups on Zynq (Michal Simek)
   - Lots of changes for Exynos and other Samsung platforms, including
     further preparations for multiplatform support and the clocks
     bindings are rearranged"

* tag 'tags/cleanup2-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (54 commits)
  devicetree: fix newly added exynos sata bindings
  ARM: EXYNOS: Fix compilation error in cpuidle.c
  ARM: S5P64X0: Explicitly include linux/serial_s3c.h in mach/pm-core.h
  ARM: EXYNOS: Remove hardware.h file
  ARM: SAMSUNG: Remove hardware.h inclusion
  ARM: S3C24XX: Remove invalid code from hardware.h
  dt-bindings: clock: Move exynos-audss-clk.h to dt-bindings/clock
  ARM: dts: Keep some essential LDOs enabled for arndale-octa board
  ARM: dts: Disable MDMA1 node for arndale-octa board
  ARM: S3C64XX: Fix build for implicit serial_s3c.h inclusion
  serial: s3c: Fix build of header without serial_core.h preinclusion
  ARM: EXYNOS: Allow wake-up using GIC interrupts
  ARM: EXYNOS: Stop using legacy Samsung PM code
  ARM: EXYNOS: Remove PM initcalls and useless indirection
  ARM: EXYNOS: Fix abuse of CONFIG_PM
  ARM: SAMSUNG: Move s3c_pm_check_* prototypes to plat/pm-common.h
  ARM: SAMSUNG: Move common save/restore helpers to separate file
  ARM: SAMSUNG: Move Samsung PM debug code into separate file
  ARM: SAMSUNG: Consolidate PM debug functions
  ARM: SAMSUNG: Use debug_ll_addr() to get UART base address
  ...

1  2 
Documentation/devicetree/bindings/phy/samsung-phy.txt
arch/arm/Kconfig.debug
arch/arm/boot/dts/exynos5250-arndale.dts
arch/arm/boot/dts/zynq-7000.dtsi
arch/arm/mach-exynos/Kconfig
arch/arm/mach-exynos/cpuidle.c
arch/arm/mach-exynos/exynos.c
arch/arm/mach-integrator/integrator_ap.c
arch/arm/mach-zynq/Kconfig
arch/arm/mach-zynq/common.c
arch/arm/plat-samsung/init.c

index 28f9edb8f19c6f9966610fdac0589407245f3ea7,67d38b3176cf992fedebfb982ef86f2507da5c6c..b422e38946d7851c47a0c9a97772944ab70e60ce
@@@ -21,56 -21,42 +21,96 @@@ Required properties
  - reg : offset and length of the Display Port PHY register set;
  - #phy-cells : from the generic PHY bindings, must be 0;
  
 +Samsung S5P/EXYNOS SoC series USB PHY
 +-------------------------------------------------
 +
 +Required properties:
 +- compatible : should be one of the listed compatibles:
 +      - "samsung,exynos4210-usb2-phy"
 +      - "samsung,exynos4x12-usb2-phy"
 +      - "samsung,exynos5250-usb2-phy"
 +- reg : a list of registers used by phy driver
 +      - first and obligatory is the location of phy modules registers
 +- samsung,sysreg-phandle - handle to syscon used to control the system registers
 +- samsung,pmureg-phandle - handle to syscon used to control PMU registers
 +- #phy-cells : from the generic phy bindings, must be 1;
 +- clocks and clock-names:
 +      - the "phy" clock is required by the phy module, used as a gate
 +      - the "ref" clock is used to get the rate of the clock provided to the
 +        PHY module
 +
 +The first phandle argument in the PHY specifier identifies the PHY, its
 +meaning is compatible dependent. For the currently supported SoCs (Exynos 4210
 +and Exynos 4212) it is as follows:
 +  0 - USB device ("device"),
 +  1 - USB host ("host"),
 +  2 - HSIC0 ("hsic0"),
 +  3 - HSIC1 ("hsic1"),
 +
 +Exynos 4210 and Exynos 4212 use mode switching and require that mode switch
 +register is supplied.
 +
 +Example:
 +
 +For Exynos 4412 (compatible with Exynos 4212):
 +
 +usbphy: phy@125b0000 {
 +      compatible = "samsung,exynos4x12-usb2-phy";
 +      reg = <0x125b0000 0x100>;
 +      clocks = <&clock 305>, <&clock 2>;
 +      clock-names = "phy", "ref";
 +      status = "okay";
 +      #phy-cells = <1>;
 +      samsung,sysreg-phandle = <&sys_reg>;
 +      samsung,pmureg-phandle = <&pmu_reg>;
 +};
 +
 +Then the PHY can be used in other nodes such as:
 +
 +phy-consumer@12340000 {
 +      phys = <&usbphy 2>;
 +      phy-names = "phy";
 +};
 +
 +Refer to DT bindings documentation of particular PHY consumer devices for more
 +information about required PHYs and the way of specification.
++
+ Samsung SATA PHY Controller
+ ---------------------------
+ SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
+ Each SATA PHY controller should have its own node.
+ Required properties:
+ - compatible        : compatible list, contains "samsung,exynos5250-sata-phy"
+ - reg : offset and length of the SATA PHY register set;
+ - #phy-cells : must be zero
+ - clocks : must be exactly one entry
+ - clock-names : must be "sata_phyctrl"
+ - samsung,exynos-sataphy-i2c-phandle : a phandle to the I2C device, no arguments
+ - samsung,syscon-phandle : a phandle to the PMU system controller, no arguments
+ Example:
+       sata_phy: sata-phy@12170000 {
+               compatible = "samsung,exynos5250-sata-phy";
+               reg = <0x12170000 0x1ff>;
+               clocks = <&clock 287>;
+               clock-names = "sata_phyctrl";
+               #phy-cells = <0>;
+               samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>;
+               samsung,syscon-phandle = <&pmu_syscon>;
+       };
+ Device-Tree bindings for sataphy i2c client driver
+ --------------------------------------------------
+ Required properties:
+ compatible: Should be "samsung,exynos-sataphy-i2c"
+ - reg: I2C address of the sataphy i2c device.
+ Example:
+       sata_phy_i2c:sata-phy@38 {
+               compatible = "samsung,exynos-sataphy-i2c";
+               reg = <0x38>;
+       };
index 8983919a4421ac943abcdd1d67be4ccf271ab069,a160744312abc37ba0974d468d998e9d65d585de..4a2fc0bf6fc913683c29bc2113b85b1f3db9bdd3
@@@ -1158,7 -1162,7 +1158,7 @@@ config DEBUG_UNCOMPRES
  config UNCOMPRESS_INCLUDE
        string
        default "debug/uncompress.h" if ARCH_MULTIPLATFORM || ARCH_MSM || \
-                                       ARCH_EXYNOS || ARCH_EFM32
 -                                      PLAT_SAMSUNG
++                                      PLAT_SAMSUNG || ARCH_EFM32
        default "mach/uncompress.h"
  
  config EARLY_PRINTK
Simple merge
Simple merge
Simple merge
index 0000000000000000000000000000000000000000,4987ec7711c3a1c44473b31d69fb940790c5456c..b32a907d021d4a2b5a809a22899cb237464d0d57
mode 000000,100644..100644
--- /dev/null
@@@ -1,0 -1,409 +1,411 @@@
 -      l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
 -      clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
+ /*
+  * SAMSUNG EXYNOS Flattened Device Tree enabled machine
+  *
+  * Copyright (c) 2010-2014 Samsung Electronics Co., Ltd.
+  *            http://www.samsung.com
+  *
+  * This program is free software; you can redistribute it and/or modify
+  * it under the terms of the GNU General Public License version 2 as
+  * published by the Free Software Foundation.
+  */
+ #include <linux/init.h>
+ #include <linux/io.h>
+ #include <linux/kernel.h>
+ #include <linux/serial_s3c.h>
+ #include <linux/of.h>
+ #include <linux/of_address.h>
+ #include <linux/of_fdt.h>
+ #include <linux/of_platform.h>
+ #include <linux/platform_device.h>
+ #include <linux/pm_domain.h>
+ #include <asm/cacheflush.h>
+ #include <asm/hardware/cache-l2x0.h>
+ #include <asm/mach/arch.h>
+ #include <asm/mach/map.h>
+ #include <asm/memory.h>
+ #include <plat/cpu.h>
+ #include "common.h"
+ #include "mfc.h"
+ #include "regs-pmu.h"
+ #define L2_AUX_VAL 0x7C470001
+ #define L2_AUX_MASK 0xC200ffff
+ static struct map_desc exynos4_iodesc[] __initdata = {
+       {
+               .virtual        = (unsigned long)S3C_VA_SYS,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSCON),
+               .length         = SZ_64K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S3C_VA_TIMER,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_TIMER),
+               .length         = SZ_16K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S3C_VA_WATCHDOG,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_SROMC,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_SROMC),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_SYSTIMER,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_PMU,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_PMU),
+               .length         = SZ_64K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_COMBINER),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_GIC_CPU,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
+               .length         = SZ_64K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_GIC_DIST,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
+               .length         = SZ_64K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_CMU,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_CMU),
+               .length         = SZ_128K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_COREPERI_BASE,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_COREPERI),
+               .length         = SZ_8K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_L2CC,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_L2CC),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_DMC0,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC0),
+               .length         = SZ_64K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_DMC1,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC1),
+               .length         = SZ_64K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_HSPHY),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       },
+ };
+ static struct map_desc exynos4_iodesc0[] __initdata = {
+       {
+               .virtual        = (unsigned long)S5P_VA_SYSRAM,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       },
+ };
+ static struct map_desc exynos4_iodesc1[] __initdata = {
+       {
+               .virtual        = (unsigned long)S5P_VA_SYSRAM,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       },
+ };
+ static struct map_desc exynos4210_iodesc[] __initdata = {
+       {
+               .virtual        = (unsigned long)S5P_VA_SYSRAM_NS,
+               .pfn            = __phys_to_pfn(EXYNOS4210_PA_SYSRAM_NS),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       },
+ };
+ static struct map_desc exynos4x12_iodesc[] __initdata = {
+       {
+               .virtual        = (unsigned long)S5P_VA_SYSRAM_NS,
+               .pfn            = __phys_to_pfn(EXYNOS4x12_PA_SYSRAM_NS),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       },
+ };
+ static struct map_desc exynos5250_iodesc[] __initdata = {
+       {
+               .virtual        = (unsigned long)S5P_VA_SYSRAM_NS,
+               .pfn            = __phys_to_pfn(EXYNOS5250_PA_SYSRAM_NS),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       },
+ };
+ static struct map_desc exynos5_iodesc[] __initdata = {
+       {
+               .virtual        = (unsigned long)S3C_VA_SYS,
+               .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSCON),
+               .length         = SZ_64K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S3C_VA_TIMER,
+               .pfn            = __phys_to_pfn(EXYNOS5_PA_TIMER),
+               .length         = SZ_16K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S3C_VA_WATCHDOG,
+               .pfn            = __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_SROMC,
+               .pfn            = __phys_to_pfn(EXYNOS5_PA_SROMC),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_SYSRAM,
+               .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_CMU,
+               .pfn            = __phys_to_pfn(EXYNOS5_PA_CMU),
+               .length         = 144 * SZ_1K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_PMU,
+               .pfn            = __phys_to_pfn(EXYNOS5_PA_PMU),
+               .length         = SZ_64K,
+               .type           = MT_DEVICE,
+       },
+ };
+ void exynos_restart(enum reboot_mode mode, const char *cmd)
+ {
+       struct device_node *np;
+       u32 val = 0x1;
+       void __iomem *addr = EXYNOS_SWRESET;
+       if (of_machine_is_compatible("samsung,exynos5440")) {
+               u32 status;
+               np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock");
+               addr = of_iomap(np, 0) + 0xbc;
+               status = __raw_readl(addr);
+               addr = of_iomap(np, 0) + 0xcc;
+               val = __raw_readl(addr);
+               val = (val & 0xffff0000) | (status & 0xffff);
+       }
+       __raw_writel(val, addr);
+ }
+ static struct platform_device exynos_cpuidle = {
+       .name           = "exynos_cpuidle",
+       .id             = -1,
+ };
+ void __init exynos_cpuidle_init(void)
+ {
+       platform_device_register(&exynos_cpuidle);
+ }
+ void __init exynos_cpufreq_init(void)
+ {
+       platform_device_register_simple("exynos-cpufreq", -1, NULL, 0);
+ }
+ void __init exynos_init_late(void)
+ {
+       if (of_machine_is_compatible("samsung,exynos5440"))
+               /* to be supported later */
+               return;
+       pm_genpd_poweroff_unused();
+       exynos_pm_init();
+ }
+ static int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
+                                       int depth, void *data)
+ {
+       struct map_desc iodesc;
+       __be32 *reg;
+       unsigned long len;
+       if (!of_flat_dt_is_compatible(node, "samsung,exynos4210-chipid") &&
+               !of_flat_dt_is_compatible(node, "samsung,exynos5440-clock"))
+               return 0;
+       reg = of_get_flat_dt_prop(node, "reg", &len);
+       if (reg == NULL || len != (sizeof(unsigned long) * 2))
+               return 0;
+       iodesc.pfn = __phys_to_pfn(be32_to_cpu(reg[0]));
+       iodesc.length = be32_to_cpu(reg[1]) - 1;
+       iodesc.virtual = (unsigned long)S5P_VA_CHIPID;
+       iodesc.type = MT_DEVICE;
+       iotable_init(&iodesc, 1);
+       return 1;
+ }
+ /*
+  * exynos_map_io
+  *
+  * register the standard cpu IO areas
+  */
+ static void __init exynos_map_io(void)
+ {
+       if (soc_is_exynos4())
+               iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
+       if (soc_is_exynos5())
+               iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
+       if (soc_is_exynos4210()) {
+               if (samsung_rev() == EXYNOS4210_REV_0)
+                       iotable_init(exynos4_iodesc0,
+                                               ARRAY_SIZE(exynos4_iodesc0));
+               else
+                       iotable_init(exynos4_iodesc1,
+                                               ARRAY_SIZE(exynos4_iodesc1));
+               iotable_init(exynos4210_iodesc, ARRAY_SIZE(exynos4210_iodesc));
+       }
+       if (soc_is_exynos4212() || soc_is_exynos4412())
+               iotable_init(exynos4x12_iodesc, ARRAY_SIZE(exynos4x12_iodesc));
+       if (soc_is_exynos5250())
+               iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
+ }
+ void __init exynos_init_io(void)
+ {
+       debug_ll_io_init();
+       of_scan_flat_dt(exynos_fdt_map_chipid, NULL);
+       /* detect cpu id and rev. */
+       s5p_init_cpu(S5P_VA_CHIPID);
+       exynos_map_io();
+ }
+ struct bus_type exynos_subsys = {
+       .name           = "exynos-core",
+       .dev_name       = "exynos-core",
+ };
+ static int __init exynos_core_init(void)
+ {
+       return subsys_system_register(&exynos_subsys, NULL);
+ }
+ core_initcall(exynos_core_init);
+ static int __init exynos4_l2x0_cache_init(void)
+ {
+       int ret;
+       ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
+       if (ret)
+               return ret;
++      if (IS_ENABLED(CONFIG_S5P_SLEEP)) {
++              l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
++              clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
++      }
+       return 0;
+ }
+ early_initcall(exynos4_l2x0_cache_init);
+ static void __init exynos_dt_machine_init(void)
+ {
+       struct device_node *i2c_np;
+       const char *i2c_compat = "samsung,s3c2440-i2c";
+       unsigned int tmp;
+       int id;
+       /*
+        * Exynos5's legacy i2c controller and new high speed i2c
+        * controller have muxed interrupt sources. By default the
+        * interrupts for 4-channel HS-I2C controller are enabled.
+        * If node for first four channels of legacy i2c controller
+        * are available then re-configure the interrupts via the
+        * system register.
+        */
+       if (soc_is_exynos5()) {
+               for_each_compatible_node(i2c_np, NULL, i2c_compat) {
+                       if (of_device_is_available(i2c_np)) {
+                               id = of_alias_get_id(i2c_np, "i2c");
+                               if (id < 4) {
+                                       tmp = readl(EXYNOS5_SYS_I2C_CFG);
+                                       writel(tmp & ~(0x1 << id),
+                                                       EXYNOS5_SYS_I2C_CFG);
+                               }
+                       }
+               }
+       }
+       exynos_cpuidle_init();
+       exynos_cpufreq_init();
+       of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+ }
+ static char const *exynos_dt_compat[] __initconst = {
+       "samsung,exynos4",
+       "samsung,exynos4210",
+       "samsung,exynos4212",
+       "samsung,exynos4412",
+       "samsung,exynos5",
+       "samsung,exynos5250",
+       "samsung,exynos5420",
+       "samsung,exynos5440",
+       NULL
+ };
+ static void __init exynos_reserve(void)
+ {
+ #ifdef CONFIG_S5P_DEV_MFC
+       int i;
+       char *mfc_mem[] = {
+               "samsung,mfc-v5",
+               "samsung,mfc-v6",
+               "samsung,mfc-v7",
+       };
+       for (i = 0; i < ARRAY_SIZE(mfc_mem); i++)
+               if (of_scan_flat_dt(s5p_fdt_alloc_mfc_mem, mfc_mem[i]))
+                       break;
+ #endif
+ }
+ DT_MACHINE_START(EXYNOS_DT, "SAMSUNG EXYNOS (Flattened Device Tree)")
+       /* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */
+       /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
+       .smp            = smp_ops(exynos_smp_ops),
+       .map_io         = exynos_init_io,
+       .init_early     = exynos_firmware_init,
+       .init_machine   = exynos_dt_machine_init,
+       .init_late      = exynos_init_late,
+       .dt_compat      = exynos_dt_compat,
+       .restart        = exynos_restart,
+       .reserve        = exynos_reserve,
+ MACHINE_END
index 0e001a489a794b87a958fd9468a59d3f1b813132,323e5053cb9fd5c621320f5ea13b9016f0149636..58c2b844e0a3c99cac20e1219d48d1685391fe69
@@@ -7,7 -8,12 +7,8 @@@ config ARCH_ZYN
        select HAVE_ARM_SCU if SMP
        select HAVE_ARM_TWD if SMP
        select ICST
 -      select MIGHT_HAVE_CACHE_L2X0
 -      select USE_OF
 -      select HAVE_SMP
 -      select SPARSE_IRQ
        select CADENCE_TTC_TIMER
 -      select ARM_GLOBAL_TIMER
 +      select ARM_GLOBAL_TIMER if !CPU_FREQ
+       select MFD_SYSCON
        help
          Support for Xilinx Zynq ARM Cortex A9 Platform
index a39be8e8085607c49156af97a4ba46462e0dac26,dca60d5ba756472b4f9e62fba0cfacce0583204c..6fcc584c1a110fb1986ee9ddbb0ae99bfbf907a4
@@@ -74,7 -73,8 +75,9 @@@ static void __init zynq_init_machine(vo
        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
  
        platform_device_register(&zynq_cpuidle_device);
 +      platform_device_register_full(&devinfo);
+       zynq_slcr_init();
  }
  
  static void __init zynq_timer_init(void)
Simple merge