drm/i915: set stc evict disable lra evict w/a
authorDaniel Vetter <daniel.vetter@ffwll.ch>
Wed, 11 Apr 2012 18:42:42 +0000 (20:42 +0200)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Tue, 17 Apr 2012 09:20:06 +0000 (11:20 +0200)
Our workaround list kindly lists that this new default value needs to
be updated in Bspec. Naturally, this did not happen.

Acked-by: Ben Widawsky <ben@bwidawsk.net>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_display.c

index 6d9205436121a3e76c0ebdb191b29b234d56d211..02124a51edad99cf20f519c49303dcea87f6a27c 100644 (file)
 #define   CM0_MASK_SHIFT          16
 #define   CM0_IZ_OPT_DISABLE      (1<<6)
 #define   CM0_ZR_OPT_DISABLE      (1<<5)
+#define          CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5)
 #define   CM0_DEPTH_EVICT_DISABLE (1<<4)
 #define   CM0_COLOR_EVICT_DISABLE (1<<3)
 #define   CM0_DEPTH_WRITE_DISABLE (1<<1)
index 1a6bb6101491b8bd2579e64a9ef55153ba35e9fd..7506a72ee8820bd94004c32aa14e4a293645de3b 100644 (file)
@@ -8878,6 +8878,10 @@ static void gen6_init_clock_gating(struct drm_device *dev)
        I915_WRITE(WM2_LP_ILK, 0);
        I915_WRITE(WM1_LP_ILK, 0);
 
+       /* clear masked bit */
+       I915_WRITE(CACHE_MODE_0,
+                  CM0_STC_EVICT_DISABLE_LRA_SNB << CM0_MASK_SHIFT);
+
        I915_WRITE(GEN6_UCGCTL1,
                   I915_READ(GEN6_UCGCTL1) |
                   GEN6_BLBUNIT_CLOCK_GATE_DISABLE |