drivers/video/pxa3xx-gcu.c

   1 /*
   2  *  pxa3xx-gcu.c - Linux kernel module for PXA3xx graphics controllers
   3  *
   4  *  This driver needs a DirectFB counterpart in user space, communication
   5  *  is handled via mmap()ed memory areas and an ioctl.
   6  *
   7  *  Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
   8  *  Copyright (c) 2009 Janine Kropp <nin@directfb.org>
   9  *  Copyright (c) 2009 Denis Oliver Kropp <dok@directfb.org>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify
  12  *  it under the terms of the GNU General Public License as published by
  13  *  the Free Software Foundation; either version 2 of the License, or
  14  *  (at your option) any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful,
  17  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *  GNU General Public License for more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License
  22  *  along with this program; if not, write to the Free Software
  23  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  24  */
  25
  26 /*
  27  * WARNING: This controller is attached to System Bus 2 of the PXA which
  28  * needs its arbiter to be enabled explicitly (CKENB & 1<<9).
  29  * There is currently no way to do this from Linux, so you need to teach
  30  * your bootloader for now.
  31  */
  32
  33 #include <linux/module.h>
  34 #include <linux/platform_device.h>
  35 #include <linux/dma-mapping.h>
  36 #include <linux/miscdevice.h>
  37 #include <linux/interrupt.h>
  38 #include <linux/spinlock.h>
  39 #include <linux/uaccess.h>
  40 #include <linux/ioctl.h>
  41 #include <linux/delay.h>
  42 #include <linux/sched.h>
  43 #include <linux/slab.h>
  44 #include <linux/clk.h>
  45 #include <linux/fs.h>
  46 #include <linux/io.h>
  47
  48 #include "pxa3xx-gcu.h"
  49
  50 #define DRV_NAME        "pxa3xx-gcu"
  51 #define MISCDEV_MINOR   197
  52
  53 #define REG_GCCR        0x00
  54 #define GCCR_SYNC_CLR   (1 << 9)
  55 #define GCCR_BP_RST     (1 << 8)
  56 #define GCCR_ABORT      (1 << 6)
  57 #define GCCR_STOP       (1 << 4)
  58
  59 #define REG_GCISCR      0x04
  60 #define REG_GCIECR      0x08
  61 #define REG_GCRBBR      0x20
  62 #define REG_GCRBLR      0x24
  63 #define REG_GCRBHR      0x28
  64 #define REG_GCRBTR      0x2C
  65 #define REG_GCRBEXHR    0x30
  66
  67 #define IE_EOB          (1 << 0)
  68 #define IE_EEOB         (1 << 5)
  69 #define IE_ALL          0xff
  70
  71 #define SHARED_SIZE     PAGE_ALIGN(sizeof(struct pxa3xx_gcu_shared))
  72
  73 /* #define PXA3XX_GCU_DEBUG */
  74 /* #define PXA3XX_GCU_DEBUG_TIMER */
  75
  76 #ifdef PXA3XX_GCU_DEBUG
  77 #define QDUMP(msg)                                      \
  78         do {                                            \
  79                 QPRINT(priv, KERN_DEBUG, msg);          \
  80         } while (0)
  81 #else
  82 #define QDUMP(msg)      do {} while (0)
  83 #endif
  84
  85 #define QERROR(msg)                                     \
  86         do {                                            \
  87                 QPRINT(priv, KERN_ERR, msg);            \
  88         } while (0)
  89
  90 struct pxa3xx_gcu_batch {
  91         struct pxa3xx_gcu_batch *next;
  92         u32                     *ptr;
  93         dma_addr_t               phys;
  94         unsigned long            length;
  95 };
  96
  97 struct pxa3xx_gcu_priv {
  98         void __iomem             *mmio_base;
  99         struct clk               *clk;
 100         struct pxa3xx_gcu_shared *shared;
 101         dma_addr_t                shared_phys;
 102         struct resource          *resource_mem;
 103         struct miscdevice         misc_dev;
 104         wait_queue_head_t         wait_idle;
 105         wait_queue_head_t         wait_free;
 106         spinlock_t                spinlock;
 107         struct timeval            base_time;
 108
 109         struct pxa3xx_gcu_batch *free;
 110         struct pxa3xx_gcu_batch *ready;
 111         struct pxa3xx_gcu_batch *ready_last;
 112         struct pxa3xx_gcu_batch *running;
 113 };
 114
 115 static inline unsigned long
 116 gc_readl(struct pxa3xx_gcu_priv *priv, unsigned int off)
 117 {
 118         return __raw_readl(priv->mmio_base + off);
 119 }
 120
 121 static inline void
 122 gc_writel(struct pxa3xx_gcu_priv *priv, unsigned int off, unsigned long val)
 123 {
 124         __raw_writel(val, priv->mmio_base + off);
 125 }
 126
 127 #define QPRINT(priv, level, msg)                                        \
 128         do {                                                            \
 129                 struct timeval tv;                                      \
 130                 struct pxa3xx_gcu_shared *shared = priv->shared;        \
 131                 u32 base = gc_readl(priv, REG_GCRBBR);                  \
 132                                                                         \
 133                 do_gettimeofday(&tv);                                   \
 134                                                                         \
 135                 printk(level "%ld.%03ld.%03ld - %-17s: %-21s (%s, "     \
 136                         "STATUS "                                       \
 137                         "0x%02lx, B 0x%08lx [%ld], E %5ld, H %5ld, "    \
 138                         "T %5ld)\n",                                    \
 139                         tv.tv_sec - priv->base_time.tv_sec,             \
 140                         tv.tv_usec / 1000, tv.tv_usec % 1000,           \
 141                         __func__, msg,                                  \
 142                         shared->hw_running ? "running" : "   idle",     \
 143                         gc_readl(priv, REG_GCISCR),                     \
 144                         gc_readl(priv, REG_GCRBBR),                     \
 145                         gc_readl(priv, REG_GCRBLR),                     \
 146                         (gc_readl(priv, REG_GCRBEXHR) - base) / 4,      \
 147                         (gc_readl(priv, REG_GCRBHR) - base) / 4,        \
 148                         (gc_readl(priv, REG_GCRBTR) - base) / 4);       \
 149         } while (0)
 150
 151 static void
 152 pxa3xx_gcu_reset(struct pxa3xx_gcu_priv *priv)
 153 {
 154         QDUMP("RESET");
 155
 156         /* disable interrupts */
 157         gc_writel(priv, REG_GCIECR, 0);
 158
 159         /* reset hardware */
 160         gc_writel(priv, REG_GCCR, GCCR_ABORT);
 161         gc_writel(priv, REG_GCCR, 0);
 162
 163         memset(priv->shared, 0, SHARED_SIZE);
 164         priv->shared->buffer_phys = priv->shared_phys;
 165         priv->shared->magic = PXA3XX_GCU_SHARED_MAGIC;
 166
 167         do_gettimeofday(&priv->base_time);
 168
 169         /* set up the ring buffer pointers */
 170         gc_writel(priv, REG_GCRBLR, 0);
 171         gc_writel(priv, REG_GCRBBR, priv->shared_phys);
 172         gc_writel(priv, REG_GCRBTR, priv->shared_phys);
 173
 174         /* enable all IRQs except EOB */
 175         gc_writel(priv, REG_GCIECR, IE_ALL & ~IE_EOB);
 176 }
 177
 178 static void
 179 dump_whole_state(struct pxa3xx_gcu_priv *priv)
 180 {
 181         struct pxa3xx_gcu_shared *sh = priv->shared;
 182         u32 base = gc_readl(priv, REG_GCRBBR);
 183
 184         QDUMP("DUMP");
 185
 186         printk(KERN_DEBUG "== PXA3XX-GCU DUMP ==\n"
 187                 "%s, STATUS 0x%02lx, B 0x%08lx [%ld], E %5ld, H %5ld, T %5ld\n",
 188                 sh->hw_running ? "running" : "idle   ",
 189                 gc_readl(priv, REG_GCISCR),
 190                 gc_readl(priv, REG_GCRBBR),
 191                 gc_readl(priv, REG_GCRBLR),
 192                 (gc_readl(priv, REG_GCRBEXHR) - base) / 4,
 193                 (gc_readl(priv, REG_GCRBHR) - base) / 4,
 194                 (gc_readl(priv, REG_GCRBTR) - base) / 4);
 195 }
 196
 197 static void
 198 flush_running(struct pxa3xx_gcu_priv *priv)
 199 {
 200         struct pxa3xx_gcu_batch *running = priv->running;
 201         struct pxa3xx_gcu_batch *next;
 202
 203         while (running) {
 204                 next = running->next;
 205                 running->next = priv->free;
 206                 priv->free = running;
 207                 running = next;
 208         }
 209
 210         priv->running = NULL;
 211 }
 212
 213 static void
 214 run_ready(struct pxa3xx_gcu_priv *priv)
 215 {
 216         unsigned int num = 0;
 217         struct pxa3xx_gcu_shared *shared = priv->shared;
 218         struct pxa3xx_gcu_batch *ready = priv->ready;
 219
 220         QDUMP("Start");
 221
 222         BUG_ON(!ready);
 223
 224         shared->buffer[num++] = 0x05000000;
 225
 226         while (ready) {
 227                 shared->buffer[num++] = 0x00000001;
 228                 shared->buffer[num++] = ready->phys;
 229                 ready = ready->next;
 230         }
 231
 232         shared->buffer[num++] = 0x05000000;
 233         priv->running = priv->ready;
 234         priv->ready = priv->ready_last = NULL;
 235         gc_writel(priv, REG_GCRBLR, 0);
 236         shared->hw_running = 1;
 237
 238         /* ring base address */
 239         gc_writel(priv, REG_GCRBBR, shared->buffer_phys);
 240
 241         /* ring tail address */
 242         gc_writel(priv, REG_GCRBTR, shared->buffer_phys + num * 4);
 243
 244         /* ring length */
 245         gc_writel(priv, REG_GCRBLR, ((num + 63) & ~63) * 4);
 246 }
 247
 248 static irqreturn_t
 249 pxa3xx_gcu_handle_irq(int irq, void *ctx)
 250 {
 251         struct pxa3xx_gcu_priv *priv = ctx;
 252         struct pxa3xx_gcu_shared *shared = priv->shared;
 253         u32 status = gc_readl(priv, REG_GCISCR) & IE_ALL;
 254
 255         QDUMP("-Interrupt");
 256
 257         if (!status)
 258                 return IRQ_NONE;
 259
 260         spin_lock(&priv->spinlock);
 261         shared->num_interrupts++;
 262
 263         if (status & IE_EEOB) {
 264                 QDUMP(" [EEOB]");
 265
 266                 flush_running(priv);
 267                 wake_up_all(&priv->wait_free);
 268
 269                 if (priv->ready) {
 270                         run_ready(priv);
 271                 } else {
 272                         /* There is no more data prepared by the userspace.
 273                          * Set hw_running = 0 and wait for the next userspace
 274                          * kick-off */
 275                         shared->num_idle++;
 276                         shared->hw_running = 0;
 277
 278                         QDUMP(" '-> Idle.");
 279
 280                         /* set ring buffer length to zero */
 281                         gc_writel(priv, REG_GCRBLR, 0);
 282
 283                         wake_up_all(&priv->wait_idle);
 284                 }
 285
 286                 shared->num_done++;
 287         } else {
 288                 QERROR(" [???]");
 289                 dump_whole_state(priv);
 290         }
 291
 292         /* Clear the interrupt */
 293         gc_writel(priv, REG_GCISCR, status);
 294         spin_unlock(&priv->spinlock);
 295
 296         return IRQ_HANDLED;
 297 }
 298
 299 static int
 300 pxa3xx_gcu_wait_idle(struct pxa3xx_gcu_priv *priv)
 301 {
 302         int ret = 0;
 303
 304         QDUMP("Waiting for idle...");
 305
 306         /* Does not need to be atomic. There's a lock in user space,
 307          * but anyhow, this is just for statistics. */
 308         priv->shared->num_wait_idle++;
 309
 310         while (priv->shared->hw_running) {
 311                 int num = priv->shared->num_interrupts;
 312                 u32 rbexhr = gc_readl(priv, REG_GCRBEXHR);
 313
 314                 ret = wait_event_interruptible_timeout(priv->wait_idle,
 315                                         !priv->shared->hw_running, HZ*4);
 316
 317                 if (ret != 0)
 318                         break;
 319
 320                 if (gc_readl(priv, REG_GCRBEXHR) == rbexhr &&
 321                     priv->shared->num_interrupts == num) {
 322                         QERROR("TIMEOUT");
 323                         ret = -ETIMEDOUT;
 324                         break;
 325                 }
 326         }
 327
 328         QDUMP("done");
 329
 330         return ret;
 331 }
 332
 333 static int
 334 pxa3xx_gcu_wait_free(struct pxa3xx_gcu_priv *priv)
 335 {
 336         int ret = 0;
 337
 338         QDUMP("Waiting for free...");
 339
 340         /* Does not need to be atomic. There's a lock in user space,
 341          * but anyhow, this is just for statistics. */
 342         priv->shared->num_wait_free++;
 343
 344         while (!priv->free) {
 345                 u32 rbexhr = gc_readl(priv, REG_GCRBEXHR);
 346
 347                 ret = wait_event_interruptible_timeout(priv->wait_free,
 348                                                        priv->free, HZ*4);
 349
 350                 if (ret < 0)
 351                         break;
 352
 353                 if (ret > 0)
 354                         continue;
 355
 356                 if (gc_readl(priv, REG_GCRBEXHR) == rbexhr) {
 357                         QERROR("TIMEOUT");
 358                         ret = -ETIMEDOUT;
 359                         break;
 360                 }
 361         }
 362
 363         QDUMP("done");
 364
 365         return ret;
 366 }
 367
 368 /* Misc device layer */
 369
 370 static inline struct pxa3xx_gcu_priv *to_pxa3xx_gcu_priv(struct file *file)
 371 {
 372         struct miscdevice *dev = file->private_data;
 373         return container_of(dev, struct pxa3xx_gcu_priv, misc_dev);
 374 }
 375
 376 static ssize_t
 377 pxa3xx_gcu_write(struct file *file, const char *buff,
 378                  size_t count, loff_t *offp)
 379 {
 380         int ret;
 381         unsigned long flags;
 382         struct pxa3xx_gcu_batch *buffer;
 383         struct pxa3xx_gcu_priv *priv = to_pxa3xx_gcu_priv(file);
 384
 385         int words = count / 4;
 386
 387         /* Does not need to be atomic. There's a lock in user space,
 388          * but anyhow, this is just for statistics. */
 389         priv->shared->num_writes++;
 390         priv->shared->num_words += words;
 391
 392         /* Last word reserved for batch buffer end command */
 393         if (words >= PXA3XX_GCU_BATCH_WORDS)
 394                 return -E2BIG;
 395
 396         /* Wait for a free buffer */
 397         if (!priv->free) {
 398                 ret = pxa3xx_gcu_wait_free(priv);
 399                 if (ret < 0)
 400                         return ret;
 401         }
 402
 403         /*
 404          * Get buffer from free list
 405          */
 406         spin_lock_irqsave(&priv->spinlock, flags);
 407         buffer = priv->free;
 408         priv->free = buffer->next;
 409         spin_unlock_irqrestore(&priv->spinlock, flags);
 410
 411
 412         /* Copy data from user into buffer */
 413         ret = copy_from_user(buffer->ptr, buff, words * 4);
 414         if (ret) {
 415                 spin_lock_irqsave(&priv->spinlock, flags);
 416                 buffer->next = priv->free;
 417                 priv->free = buffer;
 418                 spin_unlock_irqrestore(&priv->spinlock, flags);
 419                 return -EFAULT;
 420         }
 421
 422         buffer->length = words;
 423
 424         /* Append batch buffer end command */
 425         buffer->ptr[words] = 0x01000000;
 426
 427         /*
 428          * Add buffer to ready list
 429          */
 430         spin_lock_irqsave(&priv->spinlock, flags);
 431
 432         buffer->next = NULL;
 433
 434         if (priv->ready) {
 435                 BUG_ON(priv->ready_last == NULL);
 436
 437                 priv->ready_last->next = buffer;
 438         } else
 439                 priv->ready = buffer;
 440
 441         priv->ready_last = buffer;
 442
 443         if (!priv->shared->hw_running)
 444                 run_ready(priv);
 445
 446         spin_unlock_irqrestore(&priv->spinlock, flags);
 447
 448         return words * 4;
 449 }
 450
 451
 452 static long
 453 pxa3xx_gcu_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
 454 {
 455         unsigned long flags;
 456         struct pxa3xx_gcu_priv *priv = to_pxa3xx_gcu_priv(file);
 457
 458         switch (cmd) {
 459         case PXA3XX_GCU_IOCTL_RESET:
 460                 spin_lock_irqsave(&priv->spinlock, flags);
 461                 pxa3xx_gcu_reset(priv);
 462                 spin_unlock_irqrestore(&priv->spinlock, flags);
 463                 return 0;
 464
 465         case PXA3XX_GCU_IOCTL_WAIT_IDLE:
 466                 return pxa3xx_gcu_wait_idle(priv);
 467         }
 468
 469         return -ENOSYS;
 470 }
 471
 472 static int
 473 pxa3xx_gcu_mmap(struct file *file, struct vm_area_struct *vma)
 474 {
 475         unsigned int size = vma->vm_end - vma->vm_start;
 476         struct pxa3xx_gcu_priv *priv = to_pxa3xx_gcu_priv(file);
 477
 478         switch (vma->vm_pgoff) {
 479         case 0:
 480                 /* hand out the shared data area */
 481                 if (size != SHARED_SIZE)
 482                         return -EINVAL;
 483
 484                 return dma_mmap_coherent(NULL, vma,
 485                         priv->shared, priv->shared_phys, size);
 486
 487         case SHARED_SIZE >> PAGE_SHIFT:
 488                 /* hand out the MMIO base for direct register access
 489                  * from userspace */
 490                 if (size != resource_size(priv->resource_mem))
 491                         return -EINVAL;
 492
 493                 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
 494
 495                 return io_remap_pfn_range(vma, vma->vm_start,
 496                                 priv->resource_mem->start >> PAGE_SHIFT,
 497                                 size, vma->vm_page_prot);
 498         }
 499
 500         return -EINVAL;
 501 }
 502
 503
 504 #ifdef PXA3XX_GCU_DEBUG_TIMER
 505 static struct timer_list pxa3xx_gcu_debug_timer;
 506
 507 static void pxa3xx_gcu_debug_timedout(unsigned long ptr)
 508 {
 509         struct pxa3xx_gcu_priv *priv = (struct pxa3xx_gcu_priv *) ptr;
 510
 511         QERROR("Timer DUMP");
 512
 513         /* init the timer structure */
 514         init_timer(&pxa3xx_gcu_debug_timer);
 515         pxa3xx_gcu_debug_timer.function = pxa3xx_gcu_debug_timedout;
 516         pxa3xx_gcu_debug_timer.data = ptr;
 517         pxa3xx_gcu_debug_timer.expires = jiffies + 5*HZ; /* one second */
 518
 519         add_timer(&pxa3xx_gcu_debug_timer);
 520 }
 521
 522 static void pxa3xx_gcu_init_debug_timer(void)
 523 {
 524         pxa3xx_gcu_debug_timedout((unsigned long) &pxa3xx_gcu_debug_timer);
 525 }
 526 #else
 527 static inline void pxa3xx_gcu_init_debug_timer(void) {}
 528 #endif
 529
 530 static int
 531 pxa3xx_gcu_add_buffer(struct platform_device *dev,
 532                       struct pxa3xx_gcu_priv *priv)
 533 {
 534         struct pxa3xx_gcu_batch *buffer;
 535
 536         buffer = kzalloc(sizeof(struct pxa3xx_gcu_batch), GFP_KERNEL);
 537         if (!buffer)
 538                 return -ENOMEM;
 539
 540         buffer->ptr = dma_alloc_coherent(&dev->dev, PXA3XX_GCU_BATCH_WORDS * 4,
 541                                          &buffer->phys, GFP_KERNEL);
 542         if (!buffer->ptr) {
 543                 kfree(buffer);
 544                 return -ENOMEM;
 545         }
 546
 547         buffer->next = priv->free;
 548         priv->free = buffer;
 549
 550         return 0;
 551 }
 552
 553 static void
 554 pxa3xx_gcu_free_buffers(struct platform_device *dev,
 555                         struct pxa3xx_gcu_priv *priv)
 556 {
 557         struct pxa3xx_gcu_batch *next, *buffer = priv->free;
 558
 559         while (buffer) {
 560                 next = buffer->next;
 561
 562                 dma_free_coherent(&dev->dev, PXA3XX_GCU_BATCH_WORDS * 4,
 563                                   buffer->ptr, buffer->phys);
 564
 565                 kfree(buffer);
 566                 buffer = next;
 567         }
 568
 569         priv->free = NULL;
 570 }
 571
 572 static const struct file_operations pxa3xx_gcu_miscdev_fops = {
 573         .owner =                THIS_MODULE,
 574         .write =                pxa3xx_gcu_write,
 575         .unlocked_ioctl =       pxa3xx_gcu_ioctl,
 576         .mmap =                 pxa3xx_gcu_mmap,
 577 };
 578
 579 static int pxa3xx_gcu_probe(struct platform_device *dev)
 580 {
 581         int i, ret, irq;
 582         struct resource *r;
 583         struct pxa3xx_gcu_priv *priv;
 584
 585         priv = kzalloc(sizeof(struct pxa3xx_gcu_priv), GFP_KERNEL);
 586         if (!priv)
 587                 return -ENOMEM;
 588
 589         for (i = 0; i < 8; i++) {
 590                 ret = pxa3xx_gcu_add_buffer(dev, priv);
 591                 if (ret) {
 592                         dev_err(&dev->dev, "failed to allocate DMA memory\n");
 593                         goto err_free_priv;
 594                 }
 595         }
 596
 597         init_waitqueue_head(&priv->wait_idle);
 598         init_waitqueue_head(&priv->wait_free);
 599         spin_lock_init(&priv->spinlock);
 600
 601         /* we allocate the misc device structure as part of our own allocation,
 602          * so we can get a pointer to our priv structure later on with
 603          * container_of(). This isn't really necessary as we have a fixed minor
 604          * number anyway, but this is to avoid statics. */
 605
 606         priv->misc_dev.minor    = MISCDEV_MINOR,
 607         priv->misc_dev.name     = DRV_NAME,
 608         priv->misc_dev.fops     = &pxa3xx_gcu_miscdev_fops;
 609
 610         /* register misc device */
 611         ret = misc_register(&priv->misc_dev);
 612         if (ret < 0) {
 613                 dev_err(&dev->dev, "misc_register() for minor %d failed\n",
 614                         MISCDEV_MINOR);
 615                 goto err_free_priv;
 616         }
 617
 618         /* handle IO resources */
 619         r = platform_get_resource(dev, IORESOURCE_MEM, 0);
 620         if (r == NULL) {
 621                 dev_err(&dev->dev, "no I/O memory resource defined\n");
 622                 ret = -ENODEV;
 623                 goto err_misc_deregister;
 624         }
 625
 626         if (!request_mem_region(r->start, resource_size(r), dev->name)) {
 627                 dev_err(&dev->dev, "failed to request I/O memory\n");
 628                 ret = -EBUSY;
 629                 goto err_misc_deregister;
 630         }
 631
 632         priv->mmio_base = ioremap_nocache(r->start, resource_size(r));
 633         if (!priv->mmio_base) {
 634                 dev_err(&dev->dev, "failed to map I/O memory\n");
 635                 ret = -EBUSY;
 636                 goto err_free_mem_region;
 637         }
 638
 639         /* allocate dma memory */
 640         priv->shared = dma_alloc_coherent(&dev->dev, SHARED_SIZE,
 641                                           &priv->shared_phys, GFP_KERNEL);
 642
 643         if (!priv->shared) {
 644                 dev_err(&dev->dev, "failed to allocate DMA memory\n");
 645                 ret = -ENOMEM;
 646                 goto err_free_io;
 647         }
 648
 649         /* enable the clock */
 650         priv->clk = clk_get(&dev->dev, NULL);
 651         if (IS_ERR(priv->clk)) {
 652                 dev_err(&dev->dev, "failed to get clock\n");
 653                 ret = -ENODEV;
 654                 goto err_free_dma;
 655         }
 656
 657         ret = clk_enable(priv->clk);
 658         if (ret < 0) {
 659                 dev_err(&dev->dev, "failed to enable clock\n");
 660                 goto err_put_clk;
 661         }
 662
 663         /* request the IRQ */
 664         irq = platform_get_irq(dev, 0);
 665         if (irq < 0) {
 666                 dev_err(&dev->dev, "no IRQ defined\n");
 667                 ret = -ENODEV;
 668                 goto err_put_clk;
 669         }
 670
 671         ret = request_irq(irq, pxa3xx_gcu_handle_irq,
 672                           0, DRV_NAME, priv);
 673         if (ret) {
 674                 dev_err(&dev->dev, "request_irq failed\n");
 675                 ret = -EBUSY;
 676                 goto err_put_clk;
 677         }
 678
 679         platform_set_drvdata(dev, priv);
 680         priv->resource_mem = r;
 681         pxa3xx_gcu_reset(priv);
 682         pxa3xx_gcu_init_debug_timer();
 683
 684         dev_info(&dev->dev, "registered @0x%p, DMA 0x%p (%d bytes), IRQ %d\n",
 685                         (void *) r->start, (void *) priv->shared_phys,
 686                         SHARED_SIZE, irq);
 687         return 0;
 688
 689 err_put_clk:
 690         clk_disable(priv->clk);
 691         clk_put(priv->clk);
 692
 693 err_free_dma:
 694         dma_free_coherent(&dev->dev, SHARED_SIZE,
 695                         priv->shared, priv->shared_phys);
 696
 697 err_free_io:
 698         iounmap(priv->mmio_base);
 699
 700 err_free_mem_region:
 701         release_mem_region(r->start, resource_size(r));
 702
 703 err_misc_deregister:
 704         misc_deregister(&priv->misc_dev);
 705
 706 err_free_priv:
 707         pxa3xx_gcu_free_buffers(dev, priv);
 708         kfree(priv);
 709         return ret;
 710 }
 711
 712 static int pxa3xx_gcu_remove(struct platform_device *dev)
 713 {
 714         struct pxa3xx_gcu_priv *priv = platform_get_drvdata(dev);
 715         struct resource *r = priv->resource_mem;
 716
 717         pxa3xx_gcu_wait_idle(priv);
 718
 719         misc_deregister(&priv->misc_dev);
 720         dma_free_coherent(&dev->dev, SHARED_SIZE,
 721                         priv->shared, priv->shared_phys);
 722         iounmap(priv->mmio_base);
 723         release_mem_region(r->start, resource_size(r));
 724         clk_disable(priv->clk);
 725         pxa3xx_gcu_free_buffers(dev, priv);
 726         kfree(priv);
 727
 728         return 0;
 729 }
 730
 731 static struct platform_driver pxa3xx_gcu_driver = {
 732         .probe    = pxa3xx_gcu_probe,
 733         .remove  = pxa3xx_gcu_remove,
 734         .driver  = {
 735                 .owner  = THIS_MODULE,
 736                 .name   = DRV_NAME,
 737         },
 738 };
 739
 740 module_platform_driver(pxa3xx_gcu_driver);
 741
 742 MODULE_DESCRIPTION("PXA3xx graphics controller unit driver");
 743 MODULE_LICENSE("GPL");
 744 MODULE_ALIAS_MISCDEV(MISCDEV_MINOR);
 745 MODULE_AUTHOR("Janine Kropp <nin@directfb.org>, "
 746                 "Denis Oliver Kropp <dok@directfb.org>, "
 747                 "Daniel Mack <daniel@caiaq.de>");