2 * Xilinx SPI controller driver (master mode only)
4 * Author: MontaVista Software, Inc.
7 * Copyright (c) 2010 Secret Lab Technologies, Ltd.
8 * Copyright (c) 2009 Intel Corporation
9 * 2002-2007 (c) MontaVista Software, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <linux/module.h>
17 #include <linux/init.h>
18 #include <linux/interrupt.h>
20 #include <linux/platform_device.h>
21 #include <linux/spi/spi.h>
22 #include <linux/spi/spi_bitbang.h>
23 #include <linux/spi/xilinx_spi.h>
26 #define XILINX_SPI_NAME "xilinx_spi"
28 /* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e)
29 * Product Specification", DS464
31 #define XSPI_CR_OFFSET 0x60 /* Control Register */
33 #define XSPI_CR_LOOP 0x01
34 #define XSPI_CR_ENABLE 0x02
35 #define XSPI_CR_MASTER_MODE 0x04
36 #define XSPI_CR_CPOL 0x08
37 #define XSPI_CR_CPHA 0x10
38 #define XSPI_CR_MODE_MASK (XSPI_CR_CPHA | XSPI_CR_CPOL)
39 #define XSPI_CR_TXFIFO_RESET 0x20
40 #define XSPI_CR_RXFIFO_RESET 0x40
41 #define XSPI_CR_MANUAL_SSELECT 0x80
42 #define XSPI_CR_TRANS_INHIBIT 0x100
43 #define XSPI_CR_LSB_FIRST 0x200
45 #define XSPI_SR_OFFSET 0x64 /* Status Register */
47 #define XSPI_SR_RX_EMPTY_MASK 0x01 /* Receive FIFO is empty */
48 #define XSPI_SR_RX_FULL_MASK 0x02 /* Receive FIFO is full */
49 #define XSPI_SR_TX_EMPTY_MASK 0x04 /* Transmit FIFO is empty */
50 #define XSPI_SR_TX_FULL_MASK 0x08 /* Transmit FIFO is full */
51 #define XSPI_SR_MODE_FAULT_MASK 0x10 /* Mode fault error */
53 #define XSPI_TXD_OFFSET 0x68 /* Data Transmit Register */
54 #define XSPI_RXD_OFFSET 0x6c /* Data Receive Register */
56 #define XSPI_SSR_OFFSET 0x70 /* 32-bit Slave Select Register */
58 /* Register definitions as per "OPB IPIF (v3.01c) Product Specification", DS414
59 * IPIF registers are 32 bit
61 #define XIPIF_V123B_DGIER_OFFSET 0x1c /* IPIF global int enable reg */
62 #define XIPIF_V123B_GINTR_ENABLE 0x80000000
64 #define XIPIF_V123B_IISR_OFFSET 0x20 /* IPIF interrupt status reg */
65 #define XIPIF_V123B_IIER_OFFSET 0x28 /* IPIF interrupt enable reg */
67 #define XSPI_INTR_MODE_FAULT 0x01 /* Mode fault error */
68 #define XSPI_INTR_SLAVE_MODE_FAULT 0x02 /* Selected as slave while
70 #define XSPI_INTR_TX_EMPTY 0x04 /* TxFIFO is empty */
71 #define XSPI_INTR_TX_UNDERRUN 0x08 /* TxFIFO was underrun */
72 #define XSPI_INTR_RX_FULL 0x10 /* RxFIFO is full */
73 #define XSPI_INTR_RX_OVERRUN 0x20 /* RxFIFO was overrun */
74 #define XSPI_INTR_TX_HALF_EMPTY 0x40 /* TxFIFO is half empty */
76 #define XIPIF_V123B_RESETR_OFFSET 0x40 /* IPIF reset register */
77 #define XIPIF_V123B_RESET_MASK 0x0a /* the value to write */
80 /* bitbang has to be first */
81 struct spi_bitbang bitbang;
82 struct completion done;
83 struct resource mem; /* phys mem */
84 void __iomem *regs; /* virt. address of the control registers */
88 u8 *rx_ptr; /* pointer in the Tx buffer */
89 const u8 *tx_ptr; /* pointer in the Rx buffer */
90 int remaining_bytes; /* the number of bytes left to transfer */
92 unsigned int (*read_fn) (void __iomem *);
93 void (*write_fn) (u32, void __iomem *);
94 void (*tx_fn) (struct xilinx_spi *);
95 void (*rx_fn) (struct xilinx_spi *);
98 static void xspi_write32(u32 val, void __iomem *addr)
100 iowrite32(val, addr);
103 static unsigned int xspi_read32(void __iomem *addr)
105 return ioread32(addr);
108 static void xspi_write32_be(u32 val, void __iomem *addr)
110 iowrite32be(val, addr);
113 static unsigned int xspi_read32_be(void __iomem *addr)
115 return ioread32be(addr);
118 static void xspi_tx8(struct xilinx_spi *xspi)
120 xspi->write_fn(*xspi->tx_ptr, xspi->regs + XSPI_TXD_OFFSET);
124 static void xspi_tx16(struct xilinx_spi *xspi)
126 xspi->write_fn(*(u16 *)(xspi->tx_ptr), xspi->regs + XSPI_TXD_OFFSET);
130 static void xspi_tx32(struct xilinx_spi *xspi)
132 xspi->write_fn(*(u32 *)(xspi->tx_ptr), xspi->regs + XSPI_TXD_OFFSET);
136 static void xspi_rx8(struct xilinx_spi *xspi)
138 u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
140 *xspi->rx_ptr = data & 0xff;
145 static void xspi_rx16(struct xilinx_spi *xspi)
147 u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
149 *(u16 *)(xspi->rx_ptr) = data & 0xffff;
154 static void xspi_rx32(struct xilinx_spi *xspi)
156 u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
158 *(u32 *)(xspi->rx_ptr) = data;
163 static void xspi_init_hw(struct xilinx_spi *xspi)
165 void __iomem *regs_base = xspi->regs;
167 /* Reset the SPI device */
168 xspi->write_fn(XIPIF_V123B_RESET_MASK,
169 regs_base + XIPIF_V123B_RESETR_OFFSET);
170 /* Disable all the interrupts just in case */
171 xspi->write_fn(0, regs_base + XIPIF_V123B_IIER_OFFSET);
172 /* Enable the global IPIF interrupt */
173 xspi->write_fn(XIPIF_V123B_GINTR_ENABLE,
174 regs_base + XIPIF_V123B_DGIER_OFFSET);
175 /* Deselect the slave on the SPI bus */
176 xspi->write_fn(0xffff, regs_base + XSPI_SSR_OFFSET);
177 /* Disable the transmitter, enable Manual Slave Select Assertion,
178 * put SPI controller into master mode, and enable it */
179 xspi->write_fn(XSPI_CR_TRANS_INHIBIT | XSPI_CR_MANUAL_SSELECT |
180 XSPI_CR_MASTER_MODE | XSPI_CR_ENABLE | XSPI_CR_TXFIFO_RESET |
181 XSPI_CR_RXFIFO_RESET, regs_base + XSPI_CR_OFFSET);
184 static void xilinx_spi_chipselect(struct spi_device *spi, int is_on)
186 struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
188 if (is_on == BITBANG_CS_INACTIVE) {
189 /* Deselect the slave on the SPI bus */
190 xspi->write_fn(0xffff, xspi->regs + XSPI_SSR_OFFSET);
191 } else if (is_on == BITBANG_CS_ACTIVE) {
192 /* Set the SPI clock phase and polarity */
193 u16 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET)
194 & ~XSPI_CR_MODE_MASK;
195 if (spi->mode & SPI_CPHA)
197 if (spi->mode & SPI_CPOL)
199 xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
201 /* We do not check spi->max_speed_hz here as the SPI clock
202 * frequency is not software programmable (the IP block design
206 /* Activate the chip select */
207 xspi->write_fn(~(0x0001 << spi->chip_select),
208 xspi->regs + XSPI_SSR_OFFSET);
212 /* spi_bitbang requires custom setup_transfer() to be defined if there is a
213 * custom txrx_bufs(). We have nothing to setup here as the SPI IP block
214 * supports 8 or 16 bits per word which cannot be changed in software.
215 * SPI clock can't be changed in software either.
216 * Check for correct bits per word. Chip select delay calculations could be
217 * added here as soon as bitbang_work() can be made aware of the delay value.
219 static int xilinx_spi_setup_transfer(struct spi_device *spi,
220 struct spi_transfer *t)
222 struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
225 bits_per_word = (t && t->bits_per_word)
226 ? t->bits_per_word : spi->bits_per_word;
227 if (bits_per_word != xspi->bits_per_word) {
228 dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
229 __func__, bits_per_word);
236 static void xilinx_spi_fill_tx_fifo(struct xilinx_spi *xspi)
240 /* Fill the Tx FIFO with as many bytes as possible */
241 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
242 while ((sr & XSPI_SR_TX_FULL_MASK) == 0 && xspi->remaining_bytes > 0) {
246 xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET);
247 xspi->remaining_bytes -= xspi->bits_per_word / 8;
248 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
252 static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
254 struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
257 /* We get here with transmitter inhibited */
259 xspi->tx_ptr = t->tx_buf;
260 xspi->rx_ptr = t->rx_buf;
261 xspi->remaining_bytes = t->len;
262 INIT_COMPLETION(xspi->done);
265 /* Enable the transmit empty interrupt, which we use to determine
266 * progress on the transmission.
268 ipif_ier = xspi->read_fn(xspi->regs + XIPIF_V123B_IIER_OFFSET);
269 xspi->write_fn(ipif_ier | XSPI_INTR_TX_EMPTY,
270 xspi->regs + XIPIF_V123B_IIER_OFFSET);
276 xilinx_spi_fill_tx_fifo(xspi);
278 /* Start the transfer by not inhibiting the transmitter any
281 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) &
282 ~XSPI_CR_TRANS_INHIBIT;
283 xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
285 wait_for_completion(&xspi->done);
287 /* A transmit has just completed. Process received data and
288 * check for more data to transmit. Always inhibit the
289 * transmitter while the Isr refills the transmit register/FIFO,
290 * or make sure it is stopped if we're done.
292 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
293 xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT,
294 xspi->regs + XSPI_CR_OFFSET);
296 /* Read out all the data from the Rx FIFO */
297 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
298 while ((sr & XSPI_SR_RX_EMPTY_MASK) == 0) {
300 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
303 /* See if there is more data to send */
304 if (xspi->remaining_bytes <= 0)
308 /* Disable the transmit empty interrupt */
309 xspi->write_fn(ipif_ier, xspi->regs + XIPIF_V123B_IIER_OFFSET);
311 return t->len - xspi->remaining_bytes;
315 /* This driver supports single master mode only. Hence Tx FIFO Empty
316 * is the only interrupt we care about.
317 * Receive FIFO Overrun, Transmit FIFO Underrun, Mode Fault, and Slave Mode
318 * Fault are not to happen.
320 static irqreturn_t xilinx_spi_irq(int irq, void *dev_id)
322 struct xilinx_spi *xspi = dev_id;
325 /* Get the IPIF interrupts, and clear them immediately */
326 ipif_isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET);
327 xspi->write_fn(ipif_isr, xspi->regs + XIPIF_V123B_IISR_OFFSET);
329 if (ipif_isr & XSPI_INTR_TX_EMPTY) { /* Transmission completed */
330 complete(&xspi->done);
336 static const struct of_device_id xilinx_spi_of_match[] = {
337 { .compatible = "xlnx,xps-spi-2.00.a", },
338 { .compatible = "xlnx,xps-spi-2.00.b", },
341 MODULE_DEVICE_TABLE(of, xilinx_spi_of_match);
343 static int xilinx_spi_probe(struct platform_device *pdev)
345 struct xilinx_spi *xspi;
346 struct xspi_platform_data *pdata;
348 int ret, irq, num_cs = 0, bits_per_word = 8;
349 struct spi_master *master;
353 pdata = pdev->dev.platform_data;
355 num_cs = pdata->num_chipselect;
356 bits_per_word = pdata->bits_per_word;
360 if (pdev->dev.of_node) {
364 /* number of slave select bits is required */
365 prop = of_get_property(pdev->dev.of_node, "xlnx,num-ss-bits",
367 if (prop && len >= sizeof(*prop))
368 num_cs = __be32_to_cpup(prop);
374 "Missing slave select configuration data\n");
378 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
382 irq = platform_get_irq(pdev, 0);
386 master = spi_alloc_master(&pdev->dev, sizeof(struct xilinx_spi));
390 /* the spi->mode bits understood by this driver: */
391 master->mode_bits = SPI_CPOL | SPI_CPHA;
393 xspi = spi_master_get_devdata(master);
394 xspi->bitbang.master = spi_master_get(master);
395 xspi->bitbang.chipselect = xilinx_spi_chipselect;
396 xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer;
397 xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs;
398 init_completion(&xspi->done);
400 xspi->regs = devm_ioremap_resource(&pdev->dev, r);
401 if (IS_ERR(xspi->regs)) {
402 ret = PTR_ERR(xspi->regs);
406 master->bus_num = pdev->dev.id;
407 master->num_chipselect = num_cs;
408 master->dev.of_node = pdev->dev.of_node;
414 * Detect endianess on the IP via loop bit in CR. Detection
415 * must be done before reset is sent because incorrect reset
416 * value generates error interrupt.
417 * Setup little endian helper functions first and try to use them
418 * and check if bit was correctly setup or not.
420 xspi->read_fn = xspi_read32;
421 xspi->write_fn = xspi_write32;
423 xspi->write_fn(XSPI_CR_LOOP, xspi->regs + XSPI_CR_OFFSET);
424 tmp = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
426 if (tmp != XSPI_CR_LOOP) {
427 xspi->read_fn = xspi_read32_be;
428 xspi->write_fn = xspi_write32_be;
431 xspi->bits_per_word = bits_per_word;
432 if (xspi->bits_per_word == 8) {
433 xspi->tx_fn = xspi_tx8;
434 xspi->rx_fn = xspi_rx8;
435 } else if (xspi->bits_per_word == 16) {
436 xspi->tx_fn = xspi_tx16;
437 xspi->rx_fn = xspi_rx16;
438 } else if (xspi->bits_per_word == 32) {
439 xspi->tx_fn = xspi_tx32;
440 xspi->rx_fn = xspi_rx32;
447 /* SPI controller initializations */
450 /* Register for SPI Interrupt */
451 ret = request_irq(xspi->irq, xilinx_spi_irq, 0, XILINX_SPI_NAME, xspi);
455 ret = spi_bitbang_start(&xspi->bitbang);
457 dev_err(&pdev->dev, "spi_bitbang_start FAILED\n");
461 dev_info(&pdev->dev, "at 0x%08llX mapped to 0x%p, irq=%d\n",
462 (unsigned long long)r->start, xspi->regs, xspi->irq);
465 for (i = 0; i < pdata->num_devices; i++)
466 spi_new_device(master, pdata->devices + i);
469 platform_set_drvdata(pdev, master);
473 free_irq(xspi->irq, xspi);
475 spi_master_put(master);
480 static int xilinx_spi_remove(struct platform_device *pdev)
482 struct spi_master *master = platform_get_drvdata(pdev);
483 struct xilinx_spi *xspi = spi_master_get_devdata(master);
485 spi_bitbang_stop(&xspi->bitbang);
486 free_irq(xspi->irq, xspi);
488 spi_master_put(xspi->bitbang.master);
493 /* work with hotplug and coldplug */
494 MODULE_ALIAS("platform:" XILINX_SPI_NAME);
496 static struct platform_driver xilinx_spi_driver = {
497 .probe = xilinx_spi_probe,
498 .remove = xilinx_spi_remove,
500 .name = XILINX_SPI_NAME,
501 .owner = THIS_MODULE,
502 .of_match_table = xilinx_spi_of_match,
505 module_platform_driver(xilinx_spi_driver);
507 MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
508 MODULE_DESCRIPTION("Xilinx SPI driver");
509 MODULE_LICENSE("GPL");