drivers/i2c/busses/i2c-cadence.c

   1 /*
   2  * I2C bus driver for the Cadence I2C controller.
   3  *
   4  * Copyright (C) 2009 - 2014 Xilinx, Inc.
   5  *
   6  * This program is free software; you can redistribute it
   7  * and/or modify it under the terms of the GNU General Public
   8  * License as published by the Free Software Foundation;
   9  * either version 2 of the License, or (at your option) any
  10  * later version.
  11  */
  12
  13 #include <linux/clk.h>
  14 #include <linux/delay.h>
  15 #include <linux/i2c.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/io.h>
  18 #include <linux/module.h>
  19 #include <linux/platform_device.h>
  20
  21 /* Register offsets for the I2C device. */
  22 #define CDNS_I2C_CR_OFFSET              0x00 /* Control Register, RW */
  23 #define CDNS_I2C_SR_OFFSET              0x04 /* Status Register, RO */
  24 #define CDNS_I2C_ADDR_OFFSET            0x08 /* I2C Address Register, RW */
  25 #define CDNS_I2C_DATA_OFFSET            0x0C /* I2C Data Register, RW */
  26 #define CDNS_I2C_ISR_OFFSET             0x10 /* IRQ Status Register, RW */
  27 #define CDNS_I2C_XFER_SIZE_OFFSET       0x14 /* Transfer Size Register, RW */
  28 #define CDNS_I2C_TIME_OUT_OFFSET        0x1C /* Time Out Register, RW */
  29 #define CDNS_I2C_IER_OFFSET             0x24 /* IRQ Enable Register, WO */
  30 #define CDNS_I2C_IDR_OFFSET             0x28 /* IRQ Disable Register, WO */
  31
  32 /* Control Register Bit mask definitions */
  33 #define CDNS_I2C_CR_HOLD                BIT(4) /* Hold Bus bit */
  34 #define CDNS_I2C_CR_ACK_EN              BIT(3)
  35 #define CDNS_I2C_CR_NEA                 BIT(2)
  36 #define CDNS_I2C_CR_MS                  BIT(1)
  37 /* Read or Write Master transfer 0 = Transmitter, 1 = Receiver */
  38 #define CDNS_I2C_CR_RW                  BIT(0)
  39 /* 1 = Auto init FIFO to zeroes */
  40 #define CDNS_I2C_CR_CLR_FIFO            BIT(6)
  41 #define CDNS_I2C_CR_DIVA_SHIFT          14
  42 #define CDNS_I2C_CR_DIVA_MASK           (3 << CDNS_I2C_CR_DIVA_SHIFT)
  43 #define CDNS_I2C_CR_DIVB_SHIFT          8
  44 #define CDNS_I2C_CR_DIVB_MASK           (0x3f << CDNS_I2C_CR_DIVB_SHIFT)
  45
  46 /* Status Register Bit mask definitions */
  47 #define CDNS_I2C_SR_BA          BIT(8)
  48 #define CDNS_I2C_SR_RXDV        BIT(5)
  49
  50 /*
  51  * I2C Address Register Bit mask definitions
  52  * Normal addressing mode uses [6:0] bits. Extended addressing mode uses [9:0]
  53  * bits. A write access to this register always initiates a transfer if the I2C
  54  * is in master mode.
  55  */
  56 #define CDNS_I2C_ADDR_MASK      0x000003FF /* I2C Address Mask */
  57
  58 /*
  59  * I2C Interrupt Registers Bit mask definitions
  60  * All the four interrupt registers (Status/Mask/Enable/Disable) have the same
  61  * bit definitions.
  62  */
  63 #define CDNS_I2C_IXR_ARB_LOST           BIT(9)
  64 #define CDNS_I2C_IXR_RX_UNF             BIT(7)
  65 #define CDNS_I2C_IXR_TX_OVF             BIT(6)
  66 #define CDNS_I2C_IXR_RX_OVF             BIT(5)
  67 #define CDNS_I2C_IXR_SLV_RDY            BIT(4)
  68 #define CDNS_I2C_IXR_TO                 BIT(3)
  69 #define CDNS_I2C_IXR_NACK               BIT(2)
  70 #define CDNS_I2C_IXR_DATA               BIT(1)
  71 #define CDNS_I2C_IXR_COMP               BIT(0)
  72
  73 #define CDNS_I2C_IXR_ALL_INTR_MASK      (CDNS_I2C_IXR_ARB_LOST | \
  74                                          CDNS_I2C_IXR_RX_UNF | \
  75                                          CDNS_I2C_IXR_TX_OVF | \
  76                                          CDNS_I2C_IXR_RX_OVF | \
  77                                          CDNS_I2C_IXR_SLV_RDY | \
  78                                          CDNS_I2C_IXR_TO | \
  79                                          CDNS_I2C_IXR_NACK | \
  80                                          CDNS_I2C_IXR_DATA | \
  81                                          CDNS_I2C_IXR_COMP)
  82
  83 #define CDNS_I2C_IXR_ERR_INTR_MASK      (CDNS_I2C_IXR_ARB_LOST | \
  84                                          CDNS_I2C_IXR_RX_UNF | \
  85                                          CDNS_I2C_IXR_TX_OVF | \
  86                                          CDNS_I2C_IXR_RX_OVF | \
  87                                          CDNS_I2C_IXR_NACK)
  88
  89 #define CDNS_I2C_ENABLED_INTR_MASK      (CDNS_I2C_IXR_ARB_LOST | \
  90                                          CDNS_I2C_IXR_RX_UNF | \
  91                                          CDNS_I2C_IXR_TX_OVF | \
  92                                          CDNS_I2C_IXR_RX_OVF | \
  93                                          CDNS_I2C_IXR_NACK | \
  94                                          CDNS_I2C_IXR_DATA | \
  95                                          CDNS_I2C_IXR_COMP)
  96
  97 #define CDNS_I2C_TIMEOUT                msecs_to_jiffies(1000)
  98
  99 #define CDNS_I2C_FIFO_DEPTH             16
 100 /* FIFO depth at which the DATA interrupt occurs */
 101 #define CDNS_I2C_DATA_INTR_DEPTH        (CDNS_I2C_FIFO_DEPTH - 2)
 102 #define CDNS_I2C_MAX_TRANSFER_SIZE      255
 103 /* Transfer size in multiples of data interrupt depth */
 104 #define CDNS_I2C_TRANSFER_SIZE  (CDNS_I2C_MAX_TRANSFER_SIZE - 3)
 105
 106 #define DRIVER_NAME             "cdns-i2c"
 107
 108 #define CDNS_I2C_SPEED_MAX      400000
 109 #define CDNS_I2C_SPEED_DEFAULT  100000
 110
 111 #define CDNS_I2C_DIVA_MAX       4
 112 #define CDNS_I2C_DIVB_MAX       64
 113
 114 #define cdns_i2c_readreg(offset)       readl_relaxed(id->membase + offset)
 115 #define cdns_i2c_writereg(val, offset) writel_relaxed(val, id->membase + offset)
 116
 117 /**
 118  * struct cdns_i2c - I2C device private data structure
 119  * @membase:            Base address of the I2C device
 120  * @adap:               I2C adapter instance
 121  * @p_msg:              Message pointer
 122  * @err_status:         Error status in Interrupt Status Register
 123  * @xfer_done:          Transfer complete status
 124  * @p_send_buf:         Pointer to transmit buffer
 125  * @p_recv_buf:         Pointer to receive buffer
 126  * @suspended:          Flag holding the device's PM status
 127  * @send_count:         Number of bytes still expected to send
 128  * @recv_count:         Number of bytes still expected to receive
 129  * @irq:                IRQ number
 130  * @input_clk:          Input clock to I2C controller
 131  * @i2c_clk:            Maximum I2C clock speed
 132  * @bus_hold_flag:      Flag used in repeated start for clearing HOLD bit
 133  * @clk:                Pointer to struct clk
 134  * @clk_rate_change_nb: Notifier block for clock rate changes
 135  */
 136 struct cdns_i2c {
 137         void __iomem *membase;
 138         struct i2c_adapter adap;
 139         struct i2c_msg *p_msg;
 140         int err_status;
 141         struct completion xfer_done;
 142         unsigned char *p_send_buf;
 143         unsigned char *p_recv_buf;
 144         u8 suspended;
 145         unsigned int send_count;
 146         unsigned int recv_count;
 147         int irq;
 148         unsigned long input_clk;
 149         unsigned int i2c_clk;
 150         unsigned int bus_hold_flag;
 151         struct clk *clk;
 152         struct notifier_block clk_rate_change_nb;
 153 };
 154
 155 #define to_cdns_i2c(_nb)        container_of(_nb, struct cdns_i2c, \
 156                                              clk_rate_change_nb)
 157
 158 /**
 159  * cdns_i2c_clear_bus_hold() - Clear bus hold bit
 160  * @id: Pointer to driver data struct
 161  *
 162  * Helper to clear the controller's bus hold bit.
 163  */
 164 static void cdns_i2c_clear_bus_hold(struct cdns_i2c *id)
 165 {
 166         u32 reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
 167         if (reg & CDNS_I2C_CR_HOLD)
 168                 cdns_i2c_writereg(reg & ~CDNS_I2C_CR_HOLD, CDNS_I2C_CR_OFFSET);
 169 }
 170
 171 /**
 172  * cdns_i2c_isr - Interrupt handler for the I2C device
 173  * @irq:        irq number for the I2C device
 174  * @ptr:        void pointer to cdns_i2c structure
 175  *
 176  * This function handles the data interrupt, transfer complete interrupt and
 177  * the error interrupts of the I2C device.
 178  *
 179  * Return: IRQ_HANDLED always
 180  */
 181 static irqreturn_t cdns_i2c_isr(int irq, void *ptr)
 182 {
 183         unsigned int isr_status, avail_bytes;
 184         unsigned int bytes_to_recv, bytes_to_send;
 185         struct cdns_i2c *id = ptr;
 186         /* Signal completion only after everything is updated */
 187         int done_flag = 0;
 188         irqreturn_t status = IRQ_NONE;
 189
 190         isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
 191
 192         /* Handling nack and arbitration lost interrupt */
 193         if (isr_status & (CDNS_I2C_IXR_NACK | CDNS_I2C_IXR_ARB_LOST)) {
 194                 done_flag = 1;
 195                 status = IRQ_HANDLED;
 196         }
 197
 198         /* Handling Data interrupt */
 199         if ((isr_status & CDNS_I2C_IXR_DATA) &&
 200                         (id->recv_count >= CDNS_I2C_DATA_INTR_DEPTH)) {
 201                 /* Always read data interrupt threshold bytes */
 202                 bytes_to_recv = CDNS_I2C_DATA_INTR_DEPTH;
 203                 id->recv_count -= CDNS_I2C_DATA_INTR_DEPTH;
 204                 avail_bytes = cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET);
 205
 206                 /*
 207                  * if the tranfer size register value is zero, then
 208                  * check for the remaining bytes and update the
 209                  * transfer size register.
 210                  */
 211                 if (!avail_bytes) {
 212                         if (id->recv_count > CDNS_I2C_TRANSFER_SIZE)
 213                                 cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE,
 214                                                 CDNS_I2C_XFER_SIZE_OFFSET);
 215                         else
 216                                 cdns_i2c_writereg(id->recv_count,
 217                                                 CDNS_I2C_XFER_SIZE_OFFSET);
 218                 }
 219
 220                 /* Process the data received */
 221                 while (bytes_to_recv--)
 222                         *(id->p_recv_buf)++ =
 223                                 cdns_i2c_readreg(CDNS_I2C_DATA_OFFSET);
 224
 225                 if (!id->bus_hold_flag &&
 226                                 (id->recv_count <= CDNS_I2C_FIFO_DEPTH))
 227                         cdns_i2c_clear_bus_hold(id);
 228
 229                 status = IRQ_HANDLED;
 230         }
 231
 232         /* Handling Transfer Complete interrupt */
 233         if (isr_status & CDNS_I2C_IXR_COMP) {
 234                 if (!id->p_recv_buf) {
 235                         /*
 236                          * If the device is sending data If there is further
 237                          * data to be sent. Calculate the available space
 238                          * in FIFO and fill the FIFO with that many bytes.
 239                          */
 240                         if (id->send_count) {
 241                                 avail_bytes = CDNS_I2C_FIFO_DEPTH -
 242                                     cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET);
 243                                 if (id->send_count > avail_bytes)
 244                                         bytes_to_send = avail_bytes;
 245                                 else
 246                                         bytes_to_send = id->send_count;
 247
 248                                 while (bytes_to_send--) {
 249                                         cdns_i2c_writereg(
 250                                                 (*(id->p_send_buf)++),
 251                                                  CDNS_I2C_DATA_OFFSET);
 252                                         id->send_count--;
 253                                 }
 254                         } else {
 255                                 /*
 256                                  * Signal the completion of transaction and
 257                                  * clear the hold bus bit if there are no
 258                                  * further messages to be processed.
 259                                  */
 260                                 done_flag = 1;
 261                         }
 262                         if (!id->send_count && !id->bus_hold_flag)
 263                                 cdns_i2c_clear_bus_hold(id);
 264                 } else {
 265                         if (!id->bus_hold_flag)
 266                                 cdns_i2c_clear_bus_hold(id);
 267                         /*
 268                          * If the device is receiving data, then signal
 269                          * the completion of transaction and read the data
 270                          * present in the FIFO. Signal the completion of
 271                          * transaction.
 272                          */
 273                         while (cdns_i2c_readreg(CDNS_I2C_SR_OFFSET) &
 274                                         CDNS_I2C_SR_RXDV) {
 275                                 *(id->p_recv_buf)++ =
 276                                         cdns_i2c_readreg(CDNS_I2C_DATA_OFFSET);
 277                                 id->recv_count--;
 278                         }
 279                         done_flag = 1;
 280                 }
 281
 282                 status = IRQ_HANDLED;
 283         }
 284
 285         /* Update the status for errors */
 286         id->err_status = isr_status & CDNS_I2C_IXR_ERR_INTR_MASK;
 287         if (id->err_status)
 288                 status = IRQ_HANDLED;
 289
 290         cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET);
 291
 292         if (done_flag)
 293                 complete(&id->xfer_done);
 294
 295         return status;
 296 }
 297
 298 /**
 299  * cdns_i2c_mrecv - Prepare and start a master receive operation
 300  * @id:         pointer to the i2c device structure
 301  */
 302 static void cdns_i2c_mrecv(struct cdns_i2c *id)
 303 {
 304         unsigned int ctrl_reg;
 305         unsigned int isr_status;
 306
 307         id->p_recv_buf = id->p_msg->buf;
 308         id->recv_count = id->p_msg->len;
 309
 310         /* Put the controller in master receive mode and clear the FIFO */
 311         ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
 312         ctrl_reg |= CDNS_I2C_CR_RW | CDNS_I2C_CR_CLR_FIFO;
 313
 314         if (id->p_msg->flags & I2C_M_RECV_LEN)
 315                 id->recv_count = I2C_SMBUS_BLOCK_MAX + 1;
 316
 317         /*
 318          * Check for the message size against FIFO depth and set the
 319          * 'hold bus' bit if it is greater than FIFO depth.
 320          */
 321         if (id->recv_count > CDNS_I2C_FIFO_DEPTH)
 322                 ctrl_reg |= CDNS_I2C_CR_HOLD;
 323
 324         cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
 325
 326         /* Clear the interrupts in interrupt status register */
 327         isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
 328         cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET);
 329
 330         /*
 331          * The no. of bytes to receive is checked against the limit of
 332          * max transfer size. Set transfer size register with no of bytes
 333          * receive if it is less than transfer size and transfer size if
 334          * it is more. Enable the interrupts.
 335          */
 336         if (id->recv_count > CDNS_I2C_TRANSFER_SIZE)
 337                 cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE,
 338                                   CDNS_I2C_XFER_SIZE_OFFSET);
 339         else
 340                 cdns_i2c_writereg(id->recv_count, CDNS_I2C_XFER_SIZE_OFFSET);
 341         /* Clear the bus hold flag if bytes to receive is less than FIFO size */
 342         if (!id->bus_hold_flag &&
 343                 ((id->p_msg->flags & I2C_M_RECV_LEN) != I2C_M_RECV_LEN) &&
 344                 (id->recv_count <= CDNS_I2C_FIFO_DEPTH))
 345                         cdns_i2c_clear_bus_hold(id);
 346         /* Set the slave address in address register - triggers operation */
 347         cdns_i2c_writereg(id->p_msg->addr & CDNS_I2C_ADDR_MASK,
 348                                                 CDNS_I2C_ADDR_OFFSET);
 349         cdns_i2c_writereg(CDNS_I2C_ENABLED_INTR_MASK, CDNS_I2C_IER_OFFSET);
 350 }
 351
 352 /**
 353  * cdns_i2c_msend - Prepare and start a master send operation
 354  * @id:         pointer to the i2c device
 355  */
 356 static void cdns_i2c_msend(struct cdns_i2c *id)
 357 {
 358         unsigned int avail_bytes;
 359         unsigned int bytes_to_send;
 360         unsigned int ctrl_reg;
 361         unsigned int isr_status;
 362
 363         id->p_recv_buf = NULL;
 364         id->p_send_buf = id->p_msg->buf;
 365         id->send_count = id->p_msg->len;
 366
 367         /* Set the controller in Master transmit mode and clear the FIFO. */
 368         ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
 369         ctrl_reg &= ~CDNS_I2C_CR_RW;
 370         ctrl_reg |= CDNS_I2C_CR_CLR_FIFO;
 371
 372         /*
 373          * Check for the message size against FIFO depth and set the
 374          * 'hold bus' bit if it is greater than FIFO depth.
 375          */
 376         if (id->send_count > CDNS_I2C_FIFO_DEPTH)
 377                 ctrl_reg |= CDNS_I2C_CR_HOLD;
 378         cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
 379
 380         /* Clear the interrupts in interrupt status register. */
 381         isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
 382         cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET);
 383
 384         /*
 385          * Calculate the space available in FIFO. Check the message length
 386          * against the space available, and fill the FIFO accordingly.
 387          * Enable the interrupts.
 388          */
 389         avail_bytes = CDNS_I2C_FIFO_DEPTH -
 390                                 cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET);
 391
 392         if (id->send_count > avail_bytes)
 393                 bytes_to_send = avail_bytes;
 394         else
 395                 bytes_to_send = id->send_count;
 396
 397         while (bytes_to_send--) {
 398                 cdns_i2c_writereg((*(id->p_send_buf)++), CDNS_I2C_DATA_OFFSET);
 399                 id->send_count--;
 400         }
 401
 402         /*
 403          * Clear the bus hold flag if there is no more data
 404          * and if it is the last message.
 405          */
 406         if (!id->bus_hold_flag && !id->send_count)
 407                 cdns_i2c_clear_bus_hold(id);
 408         /* Set the slave address in address register - triggers operation. */
 409         cdns_i2c_writereg(id->p_msg->addr & CDNS_I2C_ADDR_MASK,
 410                                                 CDNS_I2C_ADDR_OFFSET);
 411
 412         cdns_i2c_writereg(CDNS_I2C_ENABLED_INTR_MASK, CDNS_I2C_IER_OFFSET);
 413 }
 414
 415 /**
 416  * cdns_i2c_master_reset - Reset the interface
 417  * @adap:       pointer to the i2c adapter driver instance
 418  *
 419  * This function cleanup the fifos, clear the hold bit and status
 420  * and disable the interrupts.
 421  */
 422 static void cdns_i2c_master_reset(struct i2c_adapter *adap)
 423 {
 424         struct cdns_i2c *id = adap->algo_data;
 425         u32 regval;
 426
 427         /* Disable the interrupts */
 428         cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK, CDNS_I2C_IDR_OFFSET);
 429         /* Clear the hold bit and fifos */
 430         regval = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
 431         regval &= ~CDNS_I2C_CR_HOLD;
 432         regval |= CDNS_I2C_CR_CLR_FIFO;
 433         cdns_i2c_writereg(regval, CDNS_I2C_CR_OFFSET);
 434         /* Update the transfercount register to zero */
 435         cdns_i2c_writereg(0, CDNS_I2C_XFER_SIZE_OFFSET);
 436         /* Clear the interupt status register */
 437         regval = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
 438         cdns_i2c_writereg(regval, CDNS_I2C_ISR_OFFSET);
 439         /* Clear the status register */
 440         regval = cdns_i2c_readreg(CDNS_I2C_SR_OFFSET);
 441         cdns_i2c_writereg(regval, CDNS_I2C_SR_OFFSET);
 442 }
 443
 444 static int cdns_i2c_process_msg(struct cdns_i2c *id, struct i2c_msg *msg,
 445                 struct i2c_adapter *adap)
 446 {
 447         int ret;
 448         u32 reg;
 449
 450         id->p_msg = msg;
 451         id->err_status = 0;
 452         reinit_completion(&id->xfer_done);
 453
 454         /* Check for the TEN Bit mode on each msg */
 455         reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
 456         if (msg->flags & I2C_M_TEN) {
 457                 if (reg & CDNS_I2C_CR_NEA)
 458                         cdns_i2c_writereg(reg & ~CDNS_I2C_CR_NEA,
 459                                         CDNS_I2C_CR_OFFSET);
 460         } else {
 461                 if (!(reg & CDNS_I2C_CR_NEA))
 462                         cdns_i2c_writereg(reg | CDNS_I2C_CR_NEA,
 463                                         CDNS_I2C_CR_OFFSET);
 464         }
 465
 466         /* Check for the R/W flag on each msg */
 467         if (msg->flags & I2C_M_RD)
 468                 cdns_i2c_mrecv(id);
 469         else
 470                 cdns_i2c_msend(id);
 471
 472         /* Wait for the signal of completion */
 473         ret = wait_for_completion_timeout(&id->xfer_done, adap->timeout);
 474         if (!ret) {
 475                 cdns_i2c_master_reset(adap);
 476                 dev_err(id->adap.dev.parent,
 477                                 "timeout waiting on completion\n");
 478                 return -ETIMEDOUT;
 479         }
 480
 481         cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK,
 482                           CDNS_I2C_IDR_OFFSET);
 483
 484         /* If it is bus arbitration error, try again */
 485         if (id->err_status & CDNS_I2C_IXR_ARB_LOST)
 486                 return -EAGAIN;
 487
 488         return 0;
 489 }
 490
 491 /**
 492  * cdns_i2c_master_xfer - The main i2c transfer function
 493  * @adap:       pointer to the i2c adapter driver instance
 494  * @msgs:       pointer to the i2c message structure
 495  * @num:        the number of messages to transfer
 496  *
 497  * Initiates the send/recv activity based on the transfer message received.
 498  *
 499  * Return: number of msgs processed on success, negative error otherwise
 500  */
 501 static int cdns_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
 502                                 int num)
 503 {
 504         int ret, count;
 505         u32 reg;
 506         struct cdns_i2c *id = adap->algo_data;
 507
 508         /* Check if the bus is free */
 509         if (cdns_i2c_readreg(CDNS_I2C_SR_OFFSET) & CDNS_I2C_SR_BA)
 510                 return -EAGAIN;
 511
 512         /*
 513          * Set the flag to one when multiple messages are to be
 514          * processed with a repeated start.
 515          */
 516         if (num > 1) {
 517                 id->bus_hold_flag = 1;
 518                 reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
 519                 reg |= CDNS_I2C_CR_HOLD;
 520                 cdns_i2c_writereg(reg, CDNS_I2C_CR_OFFSET);
 521         } else {
 522                 id->bus_hold_flag = 0;
 523         }
 524
 525         /* Process the msg one by one */
 526         for (count = 0; count < num; count++, msgs++) {
 527                 if (count == (num - 1))
 528                         id->bus_hold_flag = 0;
 529
 530                 ret = cdns_i2c_process_msg(id, msgs, adap);
 531                 if (ret)
 532                         return ret;
 533
 534                 /* Report the other error interrupts to application */
 535                 if (id->err_status) {
 536                         cdns_i2c_master_reset(adap);
 537
 538                         if (id->err_status & CDNS_I2C_IXR_NACK)
 539                                 return -ENXIO;
 540
 541                         return -EIO;
 542                 }
 543         }
 544
 545         return num;
 546 }
 547
 548 /**
 549  * cdns_i2c_func - Returns the supported features of the I2C driver
 550  * @adap:       pointer to the i2c adapter structure
 551  *
 552  * Return: 32 bit value, each bit corresponding to a feature
 553  */
 554 static u32 cdns_i2c_func(struct i2c_adapter *adap)
 555 {
 556         return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR |
 557                 (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
 558                 I2C_FUNC_SMBUS_BLOCK_DATA;
 559 }
 560
 561 static const struct i2c_algorithm cdns_i2c_algo = {
 562         .master_xfer    = cdns_i2c_master_xfer,
 563         .functionality  = cdns_i2c_func,
 564 };
 565
 566 /**
 567  * cdns_i2c_calc_divs - Calculate clock dividers
 568  * @f:          I2C clock frequency
 569  * @input_clk:  Input clock frequency
 570  * @a:          First divider (return value)
 571  * @b:          Second divider (return value)
 572  *
 573  * f is used as input and output variable. As input it is used as target I2C
 574  * frequency. On function exit f holds the actually resulting I2C frequency.
 575  *
 576  * Return: 0 on success, negative errno otherwise.
 577  */
 578 static int cdns_i2c_calc_divs(unsigned long *f, unsigned long input_clk,
 579                 unsigned int *a, unsigned int *b)
 580 {
 581         unsigned long fscl = *f, best_fscl = *f, actual_fscl, temp;
 582         unsigned int div_a, div_b, calc_div_a = 0, calc_div_b = 0;
 583         unsigned int last_error, current_error;
 584
 585         /* calculate (divisor_a+1) x (divisor_b+1) */
 586         temp = input_clk / (22 * fscl);
 587
 588         /*
 589          * If the calculated value is negative or 0, the fscl input is out of
 590          * range. Return error.
 591          */
 592         if (!temp || (temp > (CDNS_I2C_DIVA_MAX * CDNS_I2C_DIVB_MAX)))
 593                 return -EINVAL;
 594
 595         last_error = -1;
 596         for (div_a = 0; div_a < CDNS_I2C_DIVA_MAX; div_a++) {
 597                 div_b = DIV_ROUND_UP(input_clk, 22 * fscl * (div_a + 1));
 598
 599                 if ((div_b < 1) || (div_b > CDNS_I2C_DIVB_MAX))
 600                         continue;
 601                 div_b--;
 602
 603                 actual_fscl = input_clk / (22 * (div_a + 1) * (div_b + 1));
 604
 605                 if (actual_fscl > fscl)
 606                         continue;
 607
 608                 current_error = ((actual_fscl > fscl) ? (actual_fscl - fscl) :
 609                                                         (fscl - actual_fscl));
 610
 611                 if (last_error > current_error) {
 612                         calc_div_a = div_a;
 613                         calc_div_b = div_b;
 614                         best_fscl = actual_fscl;
 615                         last_error = current_error;
 616                 }
 617         }
 618
 619         *a = calc_div_a;
 620         *b = calc_div_b;
 621         *f = best_fscl;
 622
 623         return 0;
 624 }
 625
 626 /**
 627  * cdns_i2c_setclk - This function sets the serial clock rate for the I2C device
 628  * @clk_in:     I2C clock input frequency in Hz
 629  * @id:         Pointer to the I2C device structure
 630  *
 631  * The device must be idle rather than busy transferring data before setting
 632  * these device options.
 633  * The data rate is set by values in the control register.
 634  * The formula for determining the correct register values is
 635  *      Fscl = Fpclk/(22 x (divisor_a+1) x (divisor_b+1))
 636  * See the hardware data sheet for a full explanation of setting the serial
 637  * clock rate. The clock can not be faster than the input clock divide by 22.
 638  * The two most common clock rates are 100KHz and 400KHz.
 639  *
 640  * Return: 0 on success, negative error otherwise
 641  */
 642 static int cdns_i2c_setclk(unsigned long clk_in, struct cdns_i2c *id)
 643 {
 644         unsigned int div_a, div_b;
 645         unsigned int ctrl_reg;
 646         int ret = 0;
 647         unsigned long fscl = id->i2c_clk;
 648
 649         ret = cdns_i2c_calc_divs(&fscl, clk_in, &div_a, &div_b);
 650         if (ret)
 651                 return ret;
 652
 653         ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
 654         ctrl_reg &= ~(CDNS_I2C_CR_DIVA_MASK | CDNS_I2C_CR_DIVB_MASK);
 655         ctrl_reg |= ((div_a << CDNS_I2C_CR_DIVA_SHIFT) |
 656                         (div_b << CDNS_I2C_CR_DIVB_SHIFT));
 657         cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
 658
 659         return 0;
 660 }
 661
 662 /**
 663  * cdns_i2c_clk_notifier_cb - Clock rate change callback
 664  * @nb:         Pointer to notifier block
 665  * @event:      Notification reason
 666  * @data:       Pointer to notification data object
 667  *
 668  * This function is called when the cdns_i2c input clock frequency changes.
 669  * The callback checks whether a valid bus frequency can be generated after the
 670  * change. If so, the change is acknowledged, otherwise the change is aborted.
 671  * New dividers are written to the HW in the pre- or post change notification
 672  * depending on the scaling direction.
 673  *
 674  * Return:      NOTIFY_STOP if the rate change should be aborted, NOTIFY_OK
 675  *              to acknowedge the change, NOTIFY_DONE if the notification is
 676  *              considered irrelevant.
 677  */
 678 static int cdns_i2c_clk_notifier_cb(struct notifier_block *nb, unsigned long
 679                 event, void *data)
 680 {
 681         struct clk_notifier_data *ndata = data;
 682         struct cdns_i2c *id = to_cdns_i2c(nb);
 683
 684         if (id->suspended)
 685                 return NOTIFY_OK;
 686
 687         switch (event) {
 688         case PRE_RATE_CHANGE:
 689         {
 690                 unsigned long input_clk = ndata->new_rate;
 691                 unsigned long fscl = id->i2c_clk;
 692                 unsigned int div_a, div_b;
 693                 int ret;
 694
 695                 ret = cdns_i2c_calc_divs(&fscl, input_clk, &div_a, &div_b);
 696                 if (ret) {
 697                         dev_warn(id->adap.dev.parent,
 698                                         "clock rate change rejected\n");
 699                         return NOTIFY_STOP;
 700                 }
 701
 702                 /* scale up */
 703                 if (ndata->new_rate > ndata->old_rate)
 704                         cdns_i2c_setclk(ndata->new_rate, id);
 705
 706                 return NOTIFY_OK;
 707         }
 708         case POST_RATE_CHANGE:
 709                 id->input_clk = ndata->new_rate;
 710                 /* scale down */
 711                 if (ndata->new_rate < ndata->old_rate)
 712                         cdns_i2c_setclk(ndata->new_rate, id);
 713                 return NOTIFY_OK;
 714         case ABORT_RATE_CHANGE:
 715                 /* scale up */
 716                 if (ndata->new_rate > ndata->old_rate)
 717                         cdns_i2c_setclk(ndata->old_rate, id);
 718                 return NOTIFY_OK;
 719         default:
 720                 return NOTIFY_DONE;
 721         }
 722 }
 723
 724 /**
 725  * cdns_i2c_suspend - Suspend method for the driver
 726  * @_dev:       Address of the platform_device structure
 727  *
 728  * Put the driver into low power mode.
 729  *
 730  * Return: 0 always
 731  */
 732 static int __maybe_unused cdns_i2c_suspend(struct device *_dev)
 733 {
 734         struct platform_device *pdev = container_of(_dev,
 735                         struct platform_device, dev);
 736         struct cdns_i2c *xi2c = platform_get_drvdata(pdev);
 737
 738         clk_disable(xi2c->clk);
 739         xi2c->suspended = 1;
 740
 741         return 0;
 742 }
 743
 744 /**
 745  * cdns_i2c_resume - Resume from suspend
 746  * @_dev:       Address of the platform_device structure
 747  *
 748  * Resume operation after suspend.
 749  *
 750  * Return: 0 on success and error value on error
 751  */
 752 static int __maybe_unused cdns_i2c_resume(struct device *_dev)
 753 {
 754         struct platform_device *pdev = container_of(_dev,
 755                         struct platform_device, dev);
 756         struct cdns_i2c *xi2c = platform_get_drvdata(pdev);
 757         int ret;
 758
 759         ret = clk_enable(xi2c->clk);
 760         if (ret) {
 761                 dev_err(_dev, "Cannot enable clock.\n");
 762                 return ret;
 763         }
 764
 765         xi2c->suspended = 0;
 766
 767         return 0;
 768 }
 769
 770 static SIMPLE_DEV_PM_OPS(cdns_i2c_dev_pm_ops, cdns_i2c_suspend,
 771                          cdns_i2c_resume);
 772
 773 /**
 774  * cdns_i2c_probe - Platform registration call
 775  * @pdev:       Handle to the platform device structure
 776  *
 777  * This function does all the memory allocation and registration for the i2c
 778  * device. User can modify the address mode to 10 bit address mode using the
 779  * ioctl call with option I2C_TENBIT.
 780  *
 781  * Return: 0 on success, negative error otherwise
 782  */
 783 static int cdns_i2c_probe(struct platform_device *pdev)
 784 {
 785         struct resource *r_mem;
 786         struct cdns_i2c *id;
 787         int ret;
 788
 789         id = devm_kzalloc(&pdev->dev, sizeof(*id), GFP_KERNEL);
 790         if (!id)
 791                 return -ENOMEM;
 792
 793         platform_set_drvdata(pdev, id);
 794
 795         r_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 796         id->membase = devm_ioremap_resource(&pdev->dev, r_mem);
 797         if (IS_ERR(id->membase))
 798                 return PTR_ERR(id->membase);
 799
 800         id->irq = platform_get_irq(pdev, 0);
 801
 802         id->adap.dev.of_node = pdev->dev.of_node;
 803         id->adap.algo = &cdns_i2c_algo;
 804         id->adap.timeout = CDNS_I2C_TIMEOUT;
 805         id->adap.retries = 3;           /* Default retry value. */
 806         id->adap.algo_data = id;
 807         id->adap.dev.parent = &pdev->dev;
 808         init_completion(&id->xfer_done);
 809         snprintf(id->adap.name, sizeof(id->adap.name),
 810                  "Cadence I2C at %08lx", (unsigned long)r_mem->start);
 811
 812         id->clk = devm_clk_get(&pdev->dev, NULL);
 813         if (IS_ERR(id->clk)) {
 814                 dev_err(&pdev->dev, "input clock not found.\n");
 815                 return PTR_ERR(id->clk);
 816         }
 817         ret = clk_prepare_enable(id->clk);
 818         if (ret) {
 819                 dev_err(&pdev->dev, "Unable to enable clock.\n");
 820                 return ret;
 821         }
 822         id->clk_rate_change_nb.notifier_call = cdns_i2c_clk_notifier_cb;
 823         if (clk_notifier_register(id->clk, &id->clk_rate_change_nb))
 824                 dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
 825         id->input_clk = clk_get_rate(id->clk);
 826
 827         ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency",
 828                         &id->i2c_clk);
 829         if (ret || (id->i2c_clk > CDNS_I2C_SPEED_MAX))
 830                 id->i2c_clk = CDNS_I2C_SPEED_DEFAULT;
 831
 832         cdns_i2c_writereg(CDNS_I2C_CR_ACK_EN | CDNS_I2C_CR_NEA | CDNS_I2C_CR_MS,
 833                           CDNS_I2C_CR_OFFSET);
 834
 835         ret = cdns_i2c_setclk(id->input_clk, id);
 836         if (ret) {
 837                 dev_err(&pdev->dev, "invalid SCL clock: %u Hz\n", id->i2c_clk);
 838                 ret = -EINVAL;
 839                 goto err_clk_dis;
 840         }
 841
 842         ret = devm_request_irq(&pdev->dev, id->irq, cdns_i2c_isr, 0,
 843                                  DRIVER_NAME, id);
 844         if (ret) {
 845                 dev_err(&pdev->dev, "cannot get irq %d\n", id->irq);
 846                 goto err_clk_dis;
 847         }
 848
 849         ret = i2c_add_adapter(&id->adap);
 850         if (ret < 0) {
 851                 dev_err(&pdev->dev, "reg adap failed: %d\n", ret);
 852                 goto err_clk_dis;
 853         }
 854
 855         dev_info(&pdev->dev, "%u kHz mmio %08lx irq %d\n",
 856                  id->i2c_clk / 1000, (unsigned long)r_mem->start, id->irq);
 857
 858         return 0;
 859
 860 err_clk_dis:
 861         clk_disable_unprepare(id->clk);
 862         return ret;
 863 }
 864
 865 /**
 866  * cdns_i2c_remove - Unregister the device after releasing the resources
 867  * @pdev:       Handle to the platform device structure
 868  *
 869  * This function frees all the resources allocated to the device.
 870  *
 871  * Return: 0 always
 872  */
 873 static int cdns_i2c_remove(struct platform_device *pdev)
 874 {
 875         struct cdns_i2c *id = platform_get_drvdata(pdev);
 876
 877         i2c_del_adapter(&id->adap);
 878         clk_notifier_unregister(id->clk, &id->clk_rate_change_nb);
 879         clk_disable_unprepare(id->clk);
 880
 881         return 0;
 882 }
 883
 884 static const struct of_device_id cdns_i2c_of_match[] = {
 885         { .compatible = "cdns,i2c-r1p10", },
 886         { /* end of table */ }
 887 };
 888 MODULE_DEVICE_TABLE(of, cdns_i2c_of_match);
 889
 890 static struct platform_driver cdns_i2c_drv = {
 891         .driver = {
 892                 .name  = DRIVER_NAME,
 893                 .owner = THIS_MODULE,
 894                 .of_match_table = cdns_i2c_of_match,
 895                 .pm = &cdns_i2c_dev_pm_ops,
 896         },
 897         .probe  = cdns_i2c_probe,
 898         .remove = cdns_i2c_remove,
 899 };
 900
 901 module_platform_driver(cdns_i2c_drv);
 902
 903 MODULE_AUTHOR("Xilinx Inc.");
 904 MODULE_DESCRIPTION("Cadence I2C bus driver");
 905 MODULE_LICENSE("GPL");