drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <drm/drmP.h>
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_edid.h>
  35 #include "intel_drv.h"
  36 #include <drm/i915_drm.h>
  37 #include "i915_drv.h"
  38
  39 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  40
  41 struct dp_link_dpll {
  42         int link_bw;
  43         struct dpll dpll;
  44 };
  45
  46 static const struct dp_link_dpll gen4_dpll[] = {
  47         { DP_LINK_BW_1_62,
  48                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  49         { DP_LINK_BW_2_7,
  50                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  51 };
  52
  53 static const struct dp_link_dpll pch_dpll[] = {
  54         { DP_LINK_BW_1_62,
  55                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  56         { DP_LINK_BW_2_7,
  57                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  58 };
  59
  60 static const struct dp_link_dpll vlv_dpll[] = {
  61         { DP_LINK_BW_1_62,
  62                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  63         { DP_LINK_BW_2_7,
  64                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  65 };
  66
  67 /**
  68  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  69  * @intel_dp: DP struct
  70  *
  71  * If a CPU or PCH DP output is attached to an eDP panel, this function
  72  * will return true, and false otherwise.
  73  */
  74 static bool is_edp(struct intel_dp *intel_dp)
  75 {
  76         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  77
  78         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
  79 }
  80
  81 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
  82 {
  83         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  84
  85         return intel_dig_port->base.base.dev;
  86 }
  87
  88 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
  89 {
  90         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
  91 }
  92
  93 static void intel_dp_link_down(struct intel_dp *intel_dp);
  94 static void edp_panel_vdd_on(struct intel_dp *intel_dp);
  95 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
  96
  97 static int
  98 intel_dp_max_link_bw(struct intel_dp *intel_dp)
  99 {
 100         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 101         struct drm_device *dev = intel_dp->attached_connector->base.dev;
 102
 103         switch (max_link_bw) {
 104         case DP_LINK_BW_1_62:
 105         case DP_LINK_BW_2_7:
 106                 break;
 107         case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
 108                 if ((IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) &&
 109                     intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
 110                         max_link_bw = DP_LINK_BW_5_4;
 111                 else
 112                         max_link_bw = DP_LINK_BW_2_7;
 113                 break;
 114         default:
 115                 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
 116                      max_link_bw);
 117                 max_link_bw = DP_LINK_BW_1_62;
 118                 break;
 119         }
 120         return max_link_bw;
 121 }
 122
 123 /*
 124  * The units on the numbers in the next two are... bizarre.  Examples will
 125  * make it clearer; this one parallels an example in the eDP spec.
 126  *
 127  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 128  *
 129  *     270000 * 1 * 8 / 10 == 216000
 130  *
 131  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 132  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 133  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 134  * 119000.  At 18bpp that's 2142000 kilobits per second.
 135  *
 136  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 137  * get the result in decakilobits instead of kilobits.
 138  */
 139
 140 static int
 141 intel_dp_link_required(int pixel_clock, int bpp)
 142 {
 143         return (pixel_clock * bpp + 9) / 10;
 144 }
 145
 146 static int
 147 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 148 {
 149         return (max_link_clock * max_lanes * 8) / 10;
 150 }
 151
 152 static enum drm_mode_status
 153 intel_dp_mode_valid(struct drm_connector *connector,
 154                     struct drm_display_mode *mode)
 155 {
 156         struct intel_dp *intel_dp = intel_attached_dp(connector);
 157         struct intel_connector *intel_connector = to_intel_connector(connector);
 158         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 159         int target_clock = mode->clock;
 160         int max_rate, mode_rate, max_lanes, max_link_clock;
 161
 162         if (is_edp(intel_dp) && fixed_mode) {
 163                 if (mode->hdisplay > fixed_mode->hdisplay)
 164                         return MODE_PANEL;
 165
 166                 if (mode->vdisplay > fixed_mode->vdisplay)
 167                         return MODE_PANEL;
 168
 169                 target_clock = fixed_mode->clock;
 170         }
 171
 172         max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
 173         max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
 174
 175         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 176         mode_rate = intel_dp_link_required(target_clock, 18);
 177
 178         if (mode_rate > max_rate)
 179                 return MODE_CLOCK_HIGH;
 180
 181         if (mode->clock < 10000)
 182                 return MODE_CLOCK_LOW;
 183
 184         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 185                 return MODE_H_ILLEGAL;
 186
 187         return MODE_OK;
 188 }
 189
 190 static uint32_t
 191 pack_aux(uint8_t *src, int src_bytes)
 192 {
 193         int     i;
 194         uint32_t v = 0;
 195
 196         if (src_bytes > 4)
 197                 src_bytes = 4;
 198         for (i = 0; i < src_bytes; i++)
 199                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 200         return v;
 201 }
 202
 203 static void
 204 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 205 {
 206         int i;
 207         if (dst_bytes > 4)
 208                 dst_bytes = 4;
 209         for (i = 0; i < dst_bytes; i++)
 210                 dst[i] = src >> ((3-i) * 8);
 211 }
 212
 213 /* hrawclock is 1/4 the FSB frequency */
 214 static int
 215 intel_hrawclk(struct drm_device *dev)
 216 {
 217         struct drm_i915_private *dev_priv = dev->dev_private;
 218         uint32_t clkcfg;
 219
 220         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 221         if (IS_VALLEYVIEW(dev))
 222                 return 200;
 223
 224         clkcfg = I915_READ(CLKCFG);
 225         switch (clkcfg & CLKCFG_FSB_MASK) {
 226         case CLKCFG_FSB_400:
 227                 return 100;
 228         case CLKCFG_FSB_533:
 229                 return 133;
 230         case CLKCFG_FSB_667:
 231                 return 166;
 232         case CLKCFG_FSB_800:
 233                 return 200;
 234         case CLKCFG_FSB_1067:
 235                 return 266;
 236         case CLKCFG_FSB_1333:
 237                 return 333;
 238         /* these two are just a guess; one of them might be right */
 239         case CLKCFG_FSB_1600:
 240         case CLKCFG_FSB_1600_ALT:
 241                 return 400;
 242         default:
 243                 return 133;
 244         }
 245 }
 246
 247 static void
 248 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
 249                                     struct intel_dp *intel_dp,
 250                                     struct edp_power_seq *out);
 251 static void
 252 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
 253                                               struct intel_dp *intel_dp,
 254                                               struct edp_power_seq *out);
 255
 256 static enum pipe
 257 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 258 {
 259         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 260         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
 261         struct drm_device *dev = intel_dig_port->base.base.dev;
 262         struct drm_i915_private *dev_priv = dev->dev_private;
 263         enum port port = intel_dig_port->port;
 264         enum pipe pipe;
 265
 266         /* modeset should have pipe */
 267         if (crtc)
 268                 return to_intel_crtc(crtc)->pipe;
 269
 270         /* init time, try to find a pipe with this port selected */
 271         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 272                 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
 273                         PANEL_PORT_SELECT_MASK;
 274                 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
 275                         return pipe;
 276                 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
 277                         return pipe;
 278         }
 279
 280         /* shrug */
 281         return PIPE_A;
 282 }
 283
 284 static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
 285 {
 286         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 287
 288         if (HAS_PCH_SPLIT(dev))
 289                 return PCH_PP_CONTROL;
 290         else
 291                 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
 292 }
 293
 294 static u32 _pp_stat_reg(struct intel_dp *intel_dp)
 295 {
 296         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 297
 298         if (HAS_PCH_SPLIT(dev))
 299                 return PCH_PP_STATUS;
 300         else
 301                 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
 302 }
 303
 304 static bool edp_have_panel_power(struct intel_dp *intel_dp)
 305 {
 306         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 307         struct drm_i915_private *dev_priv = dev->dev_private;
 308
 309         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
 310 }
 311
 312 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
 313 {
 314         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 315         struct drm_i915_private *dev_priv = dev->dev_private;
 316
 317         return (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
 318 }
 319
 320 static void
 321 intel_dp_check_edp(struct intel_dp *intel_dp)
 322 {
 323         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 324         struct drm_i915_private *dev_priv = dev->dev_private;
 325
 326         if (!is_edp(intel_dp))
 327                 return;
 328
 329         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
 330                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 331                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 332                               I915_READ(_pp_stat_reg(intel_dp)),
 333                               I915_READ(_pp_ctrl_reg(intel_dp)));
 334         }
 335 }
 336
 337 static uint32_t
 338 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 339 {
 340         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 341         struct drm_device *dev = intel_dig_port->base.base.dev;
 342         struct drm_i915_private *dev_priv = dev->dev_private;
 343         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 344         uint32_t status;
 345         bool done;
 346
 347 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 348         if (has_aux_irq)
 349                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 350                                           msecs_to_jiffies_timeout(10));
 351         else
 352                 done = wait_for_atomic(C, 10) == 0;
 353         if (!done)
 354                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 355                           has_aux_irq);
 356 #undef C
 357
 358         return status;
 359 }
 360
 361 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 362 {
 363         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 364         struct drm_device *dev = intel_dig_port->base.base.dev;
 365
 366         /*
 367          * The clock divider is based off the hrawclk, and would like to run at
 368          * 2MHz.  So, take the hrawclk value and divide by 2 and use that
 369          */
 370         return index ? 0 : intel_hrawclk(dev) / 2;
 371 }
 372
 373 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 374 {
 375         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 376         struct drm_device *dev = intel_dig_port->base.base.dev;
 377
 378         if (index)
 379                 return 0;
 380
 381         if (intel_dig_port->port == PORT_A) {
 382                 if (IS_GEN6(dev) || IS_GEN7(dev))
 383                         return 200; /* SNB & IVB eDP input clock at 400Mhz */
 384                 else
 385                         return 225; /* eDP input clock at 450Mhz */
 386         } else {
 387                 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 388         }
 389 }
 390
 391 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 392 {
 393         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 394         struct drm_device *dev = intel_dig_port->base.base.dev;
 395         struct drm_i915_private *dev_priv = dev->dev_private;
 396
 397         if (intel_dig_port->port == PORT_A) {
 398                 if (index)
 399                         return 0;
 400                 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
 401         } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 402                 /* Workaround for non-ULT HSW */
 403                 switch (index) {
 404                 case 0: return 63;
 405                 case 1: return 72;
 406                 default: return 0;
 407                 }
 408         } else  {
 409                 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 410         }
 411 }
 412
 413 static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 414 {
 415         return index ? 0 : 100;
 416 }
 417
 418 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
 419                                       bool has_aux_irq,
 420                                       int send_bytes,
 421                                       uint32_t aux_clock_divider)
 422 {
 423         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 424         struct drm_device *dev = intel_dig_port->base.base.dev;
 425         uint32_t precharge, timeout;
 426
 427         if (IS_GEN6(dev))
 428                 precharge = 3;
 429         else
 430                 precharge = 5;
 431
 432         if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
 433                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
 434         else
 435                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
 436
 437         return DP_AUX_CH_CTL_SEND_BUSY |
 438                DP_AUX_CH_CTL_DONE |
 439                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 440                DP_AUX_CH_CTL_TIME_OUT_ERROR |
 441                timeout |
 442                DP_AUX_CH_CTL_RECEIVE_ERROR |
 443                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 444                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 445                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
 446 }
 447
 448 static int
 449 intel_dp_aux_ch(struct intel_dp *intel_dp,
 450                 uint8_t *send, int send_bytes,
 451                 uint8_t *recv, int recv_size)
 452 {
 453         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 454         struct drm_device *dev = intel_dig_port->base.base.dev;
 455         struct drm_i915_private *dev_priv = dev->dev_private;
 456         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 457         uint32_t ch_data = ch_ctl + 4;
 458         uint32_t aux_clock_divider;
 459         int i, ret, recv_bytes;
 460         uint32_t status;
 461         int try, clock = 0;
 462         bool has_aux_irq = HAS_AUX_IRQ(dev);
 463
 464         /* dp aux is extremely sensitive to irq latency, hence request the
 465          * lowest possible wakeup latency and so prevent the cpu from going into
 466          * deep sleep states.
 467          */
 468         pm_qos_update_request(&dev_priv->pm_qos, 0);
 469
 470         intel_dp_check_edp(intel_dp);
 471
 472         intel_aux_display_runtime_get(dev_priv);
 473
 474         /* Try to wait for any previous AUX channel activity */
 475         for (try = 0; try < 3; try++) {
 476                 status = I915_READ_NOTRACE(ch_ctl);
 477                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 478                         break;
 479                 msleep(1);
 480         }
 481
 482         if (try == 3) {
 483                 WARN(1, "dp_aux_ch not started status 0x%08x\n",
 484                      I915_READ(ch_ctl));
 485                 ret = -EBUSY;
 486                 goto out;
 487         }
 488
 489         /* Only 5 data registers! */
 490         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
 491                 ret = -E2BIG;
 492                 goto out;
 493         }
 494
 495         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
 496                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
 497                                                           has_aux_irq,
 498                                                           send_bytes,
 499                                                           aux_clock_divider);
 500
 501                 /* Must try at least 3 times according to DP spec */
 502                 for (try = 0; try < 5; try++) {
 503                         /* Load the send data into the aux channel data registers */
 504                         for (i = 0; i < send_bytes; i += 4)
 505                                 I915_WRITE(ch_data + i,
 506                                            pack_aux(send + i, send_bytes - i));
 507
 508                         /* Send the command and wait for it to complete */
 509                         I915_WRITE(ch_ctl, send_ctl);
 510
 511                         status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
 512
 513                         /* Clear done status and any errors */
 514                         I915_WRITE(ch_ctl,
 515                                    status |
 516                                    DP_AUX_CH_CTL_DONE |
 517                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
 518                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
 519
 520                         if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
 521                                       DP_AUX_CH_CTL_RECEIVE_ERROR))
 522                                 continue;
 523                         if (status & DP_AUX_CH_CTL_DONE)
 524                                 break;
 525                 }
 526                 if (status & DP_AUX_CH_CTL_DONE)
 527                         break;
 528         }
 529
 530         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 531                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 532                 ret = -EBUSY;
 533                 goto out;
 534         }
 535
 536         /* Check for timeout or receive error.
 537          * Timeouts occur when the sink is not connected
 538          */
 539         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 540                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 541                 ret = -EIO;
 542                 goto out;
 543         }
 544
 545         /* Timeouts occur when the device isn't connected, so they're
 546          * "normal" -- don't fill the kernel log with these */
 547         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 548                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 549                 ret = -ETIMEDOUT;
 550                 goto out;
 551         }
 552
 553         /* Unload any bytes sent back from the other side */
 554         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 555                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 556         if (recv_bytes > recv_size)
 557                 recv_bytes = recv_size;
 558
 559         for (i = 0; i < recv_bytes; i += 4)
 560                 unpack_aux(I915_READ(ch_data + i),
 561                            recv + i, recv_bytes - i);
 562
 563         ret = recv_bytes;
 564 out:
 565         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
 566         intel_aux_display_runtime_put(dev_priv);
 567
 568         return ret;
 569 }
 570
 571 /* Write data to the aux channel in native mode */
 572 static int
 573 intel_dp_aux_native_write(struct intel_dp *intel_dp,
 574                           uint16_t address, uint8_t *send, int send_bytes)
 575 {
 576         int ret;
 577         uint8_t msg[20];
 578         int msg_bytes;
 579         uint8_t ack;
 580         int retry;
 581
 582         if (WARN_ON(send_bytes > 16))
 583                 return -E2BIG;
 584
 585         intel_dp_check_edp(intel_dp);
 586         msg[0] = DP_AUX_NATIVE_WRITE << 4;
 587         msg[1] = address >> 8;
 588         msg[2] = address & 0xff;
 589         msg[3] = send_bytes - 1;
 590         memcpy(&msg[4], send, send_bytes);
 591         msg_bytes = send_bytes + 4;
 592         for (retry = 0; retry < 7; retry++) {
 593                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
 594                 if (ret < 0)
 595                         return ret;
 596                 ack >>= 4;
 597                 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK)
 598                         return send_bytes;
 599                 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
 600                         usleep_range(400, 500);
 601                 else
 602                         return -EIO;
 603         }
 604
 605         DRM_ERROR("too many retries, giving up\n");
 606         return -EIO;
 607 }
 608
 609 /* Write a single byte to the aux channel in native mode */
 610 static int
 611 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
 612                             uint16_t address, uint8_t byte)
 613 {
 614         return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
 615 }
 616
 617 /* read bytes from a native aux channel */
 618 static int
 619 intel_dp_aux_native_read(struct intel_dp *intel_dp,
 620                          uint16_t address, uint8_t *recv, int recv_bytes)
 621 {
 622         uint8_t msg[4];
 623         int msg_bytes;
 624         uint8_t reply[20];
 625         int reply_bytes;
 626         uint8_t ack;
 627         int ret;
 628         int retry;
 629
 630         if (WARN_ON(recv_bytes > 19))
 631                 return -E2BIG;
 632
 633         intel_dp_check_edp(intel_dp);
 634         msg[0] = DP_AUX_NATIVE_READ << 4;
 635         msg[1] = address >> 8;
 636         msg[2] = address & 0xff;
 637         msg[3] = recv_bytes - 1;
 638
 639         msg_bytes = 4;
 640         reply_bytes = recv_bytes + 1;
 641
 642         for (retry = 0; retry < 7; retry++) {
 643                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
 644                                       reply, reply_bytes);
 645                 if (ret == 0)
 646                         return -EPROTO;
 647                 if (ret < 0)
 648                         return ret;
 649                 ack = reply[0] >> 4;
 650                 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK) {
 651                         memcpy(recv, reply + 1, ret - 1);
 652                         return ret - 1;
 653                 }
 654                 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
 655                         usleep_range(400, 500);
 656                 else
 657                         return -EIO;
 658         }
 659
 660         DRM_ERROR("too many retries, giving up\n");
 661         return -EIO;
 662 }
 663
 664 static int
 665 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
 666                     uint8_t write_byte, uint8_t *read_byte)
 667 {
 668         struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
 669         struct intel_dp *intel_dp = container_of(adapter,
 670                                                 struct intel_dp,
 671                                                 adapter);
 672         uint16_t address = algo_data->address;
 673         uint8_t msg[5];
 674         uint8_t reply[2];
 675         unsigned retry;
 676         int msg_bytes;
 677         int reply_bytes;
 678         int ret;
 679
 680         edp_panel_vdd_on(intel_dp);
 681         intel_dp_check_edp(intel_dp);
 682         /* Set up the command byte */
 683         if (mode & MODE_I2C_READ)
 684                 msg[0] = DP_AUX_I2C_READ << 4;
 685         else
 686                 msg[0] = DP_AUX_I2C_WRITE << 4;
 687
 688         if (!(mode & MODE_I2C_STOP))
 689                 msg[0] |= DP_AUX_I2C_MOT << 4;
 690
 691         msg[1] = address >> 8;
 692         msg[2] = address;
 693
 694         switch (mode) {
 695         case MODE_I2C_WRITE:
 696                 msg[3] = 0;
 697                 msg[4] = write_byte;
 698                 msg_bytes = 5;
 699                 reply_bytes = 1;
 700                 break;
 701         case MODE_I2C_READ:
 702                 msg[3] = 0;
 703                 msg_bytes = 4;
 704                 reply_bytes = 2;
 705                 break;
 706         default:
 707                 msg_bytes = 3;
 708                 reply_bytes = 1;
 709                 break;
 710         }
 711
 712         /*
 713          * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device is
 714          * required to retry at least seven times upon receiving AUX_DEFER
 715          * before giving up the AUX transaction.
 716          */
 717         for (retry = 0; retry < 7; retry++) {
 718                 ret = intel_dp_aux_ch(intel_dp,
 719                                       msg, msg_bytes,
 720                                       reply, reply_bytes);
 721                 if (ret < 0) {
 722                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 723                         goto out;
 724                 }
 725
 726                 switch ((reply[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK) {
 727                 case DP_AUX_NATIVE_REPLY_ACK:
 728                         /* I2C-over-AUX Reply field is only valid
 729                          * when paired with AUX ACK.
 730                          */
 731                         break;
 732                 case DP_AUX_NATIVE_REPLY_NACK:
 733                         DRM_DEBUG_KMS("aux_ch native nack\n");
 734                         ret = -EREMOTEIO;
 735                         goto out;
 736                 case DP_AUX_NATIVE_REPLY_DEFER:
 737                         /*
 738                          * For now, just give more slack to branch devices. We
 739                          * could check the DPCD for I2C bit rate capabilities,
 740                          * and if available, adjust the interval. We could also
 741                          * be more careful with DP-to-Legacy adapters where a
 742                          * long legacy cable may force very low I2C bit rates.
 743                          */
 744                         if (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
 745                             DP_DWN_STRM_PORT_PRESENT)
 746                                 usleep_range(500, 600);
 747                         else
 748                                 usleep_range(300, 400);
 749                         continue;
 750                 default:
 751                         DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
 752                                   reply[0]);
 753                         ret = -EREMOTEIO;
 754                         goto out;
 755                 }
 756
 757                 switch ((reply[0] >> 4) & DP_AUX_I2C_REPLY_MASK) {
 758                 case DP_AUX_I2C_REPLY_ACK:
 759                         if (mode == MODE_I2C_READ) {
 760                                 *read_byte = reply[1];
 761                         }
 762                         ret = reply_bytes - 1;
 763                         goto out;
 764                 case DP_AUX_I2C_REPLY_NACK:
 765                         DRM_DEBUG_KMS("aux_i2c nack\n");
 766                         ret = -EREMOTEIO;
 767                         goto out;
 768                 case DP_AUX_I2C_REPLY_DEFER:
 769                         DRM_DEBUG_KMS("aux_i2c defer\n");
 770                         udelay(100);
 771                         break;
 772                 default:
 773                         DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
 774                         ret = -EREMOTEIO;
 775                         goto out;
 776                 }
 777         }
 778
 779         DRM_ERROR("too many retries, giving up\n");
 780         ret = -EREMOTEIO;
 781
 782 out:
 783         edp_panel_vdd_off(intel_dp, false);
 784         return ret;
 785 }
 786
 787 static int
 788 intel_dp_i2c_init(struct intel_dp *intel_dp,
 789                   struct intel_connector *intel_connector, const char *name)
 790 {
 791         int     ret;
 792
 793         DRM_DEBUG_KMS("i2c_init %s\n", name);
 794         intel_dp->algo.running = false;
 795         intel_dp->algo.address = 0;
 796         intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
 797
 798         memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
 799         intel_dp->adapter.owner = THIS_MODULE;
 800         intel_dp->adapter.class = I2C_CLASS_DDC;
 801         strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
 802         intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
 803         intel_dp->adapter.algo_data = &intel_dp->algo;
 804         intel_dp->adapter.dev.parent = intel_connector->base.kdev;
 805
 806         ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
 807         return ret;
 808 }
 809
 810 static void
 811 intel_dp_set_clock(struct intel_encoder *encoder,
 812                    struct intel_crtc_config *pipe_config, int link_bw)
 813 {
 814         struct drm_device *dev = encoder->base.dev;
 815         const struct dp_link_dpll *divisor = NULL;
 816         int i, count = 0;
 817
 818         if (IS_G4X(dev)) {
 819                 divisor = gen4_dpll;
 820                 count = ARRAY_SIZE(gen4_dpll);
 821         } else if (IS_HASWELL(dev)) {
 822                 /* Haswell has special-purpose DP DDI clocks. */
 823         } else if (HAS_PCH_SPLIT(dev)) {
 824                 divisor = pch_dpll;
 825                 count = ARRAY_SIZE(pch_dpll);
 826         } else if (IS_VALLEYVIEW(dev)) {
 827                 divisor = vlv_dpll;
 828                 count = ARRAY_SIZE(vlv_dpll);
 829         }
 830
 831         if (divisor && count) {
 832                 for (i = 0; i < count; i++) {
 833                         if (link_bw == divisor[i].link_bw) {
 834                                 pipe_config->dpll = divisor[i].dpll;
 835                                 pipe_config->clock_set = true;
 836                                 break;
 837                         }
 838                 }
 839         }
 840 }
 841
 842 bool
 843 intel_dp_compute_config(struct intel_encoder *encoder,
 844                         struct intel_crtc_config *pipe_config)
 845 {
 846         struct drm_device *dev = encoder->base.dev;
 847         struct drm_i915_private *dev_priv = dev->dev_private;
 848         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
 849         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 850         enum port port = dp_to_dig_port(intel_dp)->port;
 851         struct intel_crtc *intel_crtc = encoder->new_crtc;
 852         struct intel_connector *intel_connector = intel_dp->attached_connector;
 853         int lane_count, clock;
 854         int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
 855         /* Conveniently, the link BW constants become indices with a shift...*/
 856         int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
 857         int bpp, mode_rate;
 858         static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
 859         int link_avail, link_clock;
 860
 861         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
 862                 pipe_config->has_pch_encoder = true;
 863
 864         pipe_config->has_dp_encoder = true;
 865
 866         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
 867                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
 868                                        adjusted_mode);
 869                 if (!HAS_PCH_SPLIT(dev))
 870                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
 871                                                  intel_connector->panel.fitting_mode);
 872                 else
 873                         intel_pch_panel_fitting(intel_crtc, pipe_config,
 874                                                 intel_connector->panel.fitting_mode);
 875         }
 876
 877         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
 878                 return false;
 879
 880         DRM_DEBUG_KMS("DP link computation with max lane count %i "
 881                       "max bw %02x pixel clock %iKHz\n",
 882                       max_lane_count, bws[max_clock],
 883                       adjusted_mode->crtc_clock);
 884
 885         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
 886          * bpc in between. */
 887         bpp = pipe_config->pipe_bpp;
 888         if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
 889             dev_priv->vbt.edp_bpp < bpp) {
 890                 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
 891                               dev_priv->vbt.edp_bpp);
 892                 bpp = dev_priv->vbt.edp_bpp;
 893         }
 894
 895         for (; bpp >= 6*3; bpp -= 2*3) {
 896                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
 897                                                    bpp);
 898
 899                 for (clock = 0; clock <= max_clock; clock++) {
 900                         for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 901                                 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
 902                                 link_avail = intel_dp_max_data_rate(link_clock,
 903                                                                     lane_count);
 904
 905                                 if (mode_rate <= link_avail) {
 906                                         goto found;
 907                                 }
 908                         }
 909                 }
 910         }
 911
 912         return false;
 913
 914 found:
 915         if (intel_dp->color_range_auto) {
 916                 /*
 917                  * See:
 918                  * CEA-861-E - 5.1 Default Encoding Parameters
 919                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
 920                  */
 921                 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
 922                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
 923                 else
 924                         intel_dp->color_range = 0;
 925         }
 926
 927         if (intel_dp->color_range)
 928                 pipe_config->limited_color_range = true;
 929
 930         intel_dp->link_bw = bws[clock];
 931         intel_dp->lane_count = lane_count;
 932         pipe_config->pipe_bpp = bpp;
 933         pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
 934
 935         DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
 936                       intel_dp->link_bw, intel_dp->lane_count,
 937                       pipe_config->port_clock, bpp);
 938         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
 939                       mode_rate, link_avail);
 940
 941         intel_link_compute_m_n(bpp, lane_count,
 942                                adjusted_mode->crtc_clock,
 943                                pipe_config->port_clock,
 944                                &pipe_config->dp_m_n);
 945
 946         intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
 947
 948         return true;
 949 }
 950
 951 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
 952 {
 953         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 954         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
 955         struct drm_device *dev = crtc->base.dev;
 956         struct drm_i915_private *dev_priv = dev->dev_private;
 957         u32 dpa_ctl;
 958
 959         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
 960         dpa_ctl = I915_READ(DP_A);
 961         dpa_ctl &= ~DP_PLL_FREQ_MASK;
 962
 963         if (crtc->config.port_clock == 162000) {
 964                 /* For a long time we've carried around a ILK-DevA w/a for the
 965                  * 160MHz clock. If we're really unlucky, it's still required.
 966                  */
 967                 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
 968                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
 969                 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 970         } else {
 971                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
 972                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 973         }
 974
 975         I915_WRITE(DP_A, dpa_ctl);
 976
 977         POSTING_READ(DP_A);
 978         udelay(500);
 979 }
 980
 981 static void intel_dp_mode_set(struct intel_encoder *encoder)
 982 {
 983         struct drm_device *dev = encoder->base.dev;
 984         struct drm_i915_private *dev_priv = dev->dev_private;
 985         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 986         enum port port = dp_to_dig_port(intel_dp)->port;
 987         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 988         struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
 989
 990         /*
 991          * There are four kinds of DP registers:
 992          *
 993          *      IBX PCH
 994          *      SNB CPU
 995          *      IVB CPU
 996          *      CPT PCH
 997          *
 998          * IBX PCH and CPU are the same for almost everything,
 999          * except that the CPU DP PLL is configured in this
1000          * register
1001          *
1002          * CPT PCH is quite different, having many bits moved
1003          * to the TRANS_DP_CTL register instead. That
1004          * configuration happens (oddly) in ironlake_pch_enable
1005          */
1006
1007         /* Preserve the BIOS-computed detected bit. This is
1008          * supposed to be read-only.
1009          */
1010         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1011
1012         /* Handle DP bits in common between all three register formats */
1013         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1014         intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
1015
1016         if (intel_dp->has_audio) {
1017                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
1018                                  pipe_name(crtc->pipe));
1019                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
1020                 intel_write_eld(&encoder->base, adjusted_mode);
1021         }
1022
1023         /* Split out the IBX/CPU vs CPT settings */
1024
1025         if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1026                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1027                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1028                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1029                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1030                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1031
1032                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1033                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1034
1035                 intel_dp->DP |= crtc->pipe << 29;
1036         } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1037                 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
1038                         intel_dp->DP |= intel_dp->color_range;
1039
1040                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1041                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1042                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1043                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1044                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1045
1046                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1047                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1048
1049                 if (crtc->pipe == 1)
1050                         intel_dp->DP |= DP_PIPEB_SELECT;
1051         } else {
1052                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1053         }
1054
1055         if (port == PORT_A && !IS_VALLEYVIEW(dev))
1056                 ironlake_set_pll_cpu_edp(intel_dp);
1057 }
1058
1059 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
1060 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
1061
1062 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
1063 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
1064
1065 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1066 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1067
1068 static void wait_panel_status(struct intel_dp *intel_dp,
1069                                        u32 mask,
1070                                        u32 value)
1071 {
1072         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1073         struct drm_i915_private *dev_priv = dev->dev_private;
1074         u32 pp_stat_reg, pp_ctrl_reg;
1075
1076         pp_stat_reg = _pp_stat_reg(intel_dp);
1077         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1078
1079         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1080                         mask, value,
1081                         I915_READ(pp_stat_reg),
1082                         I915_READ(pp_ctrl_reg));
1083
1084         if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1085                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1086                                 I915_READ(pp_stat_reg),
1087                                 I915_READ(pp_ctrl_reg));
1088         }
1089
1090         DRM_DEBUG_KMS("Wait complete\n");
1091 }
1092
1093 static void wait_panel_on(struct intel_dp *intel_dp)
1094 {
1095         DRM_DEBUG_KMS("Wait for panel power on\n");
1096         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1097 }
1098
1099 static void wait_panel_off(struct intel_dp *intel_dp)
1100 {
1101         DRM_DEBUG_KMS("Wait for panel power off time\n");
1102         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1103 }
1104
1105 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1106 {
1107         DRM_DEBUG_KMS("Wait for panel power cycle\n");
1108
1109         /* When we disable the VDD override bit last we have to do the manual
1110          * wait. */
1111         wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1112                                        intel_dp->panel_power_cycle_delay);
1113
1114         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1115 }
1116
1117 static void wait_backlight_on(struct intel_dp *intel_dp)
1118 {
1119         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1120                                        intel_dp->backlight_on_delay);
1121 }
1122
1123 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1124 {
1125         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1126                                        intel_dp->backlight_off_delay);
1127 }
1128
1129 /* Read the current pp_control value, unlocking the register if it
1130  * is locked
1131  */
1132
1133 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1134 {
1135         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1136         struct drm_i915_private *dev_priv = dev->dev_private;
1137         u32 control;
1138
1139         control = I915_READ(_pp_ctrl_reg(intel_dp));
1140         control &= ~PANEL_UNLOCK_MASK;
1141         control |= PANEL_UNLOCK_REGS;
1142         return control;
1143 }
1144
1145 static void edp_panel_vdd_on(struct intel_dp *intel_dp)
1146 {
1147         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1148         struct drm_i915_private *dev_priv = dev->dev_private;
1149         u32 pp;
1150         u32 pp_stat_reg, pp_ctrl_reg;
1151
1152         if (!is_edp(intel_dp))
1153                 return;
1154
1155         WARN(intel_dp->want_panel_vdd,
1156              "eDP VDD already requested on\n");
1157
1158         intel_dp->want_panel_vdd = true;
1159
1160         if (edp_have_panel_vdd(intel_dp))
1161                 return;
1162
1163         intel_runtime_pm_get(dev_priv);
1164
1165         DRM_DEBUG_KMS("Turning eDP VDD on\n");
1166
1167         if (!edp_have_panel_power(intel_dp))
1168                 wait_panel_power_cycle(intel_dp);
1169
1170         pp = ironlake_get_pp_control(intel_dp);
1171         pp |= EDP_FORCE_VDD;
1172
1173         pp_stat_reg = _pp_stat_reg(intel_dp);
1174         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1175
1176         I915_WRITE(pp_ctrl_reg, pp);
1177         POSTING_READ(pp_ctrl_reg);
1178         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1179                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1180         /*
1181          * If the panel wasn't on, delay before accessing aux channel
1182          */
1183         if (!edp_have_panel_power(intel_dp)) {
1184                 DRM_DEBUG_KMS("eDP was not running\n");
1185                 msleep(intel_dp->panel_power_up_delay);
1186         }
1187 }
1188
1189 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1190 {
1191         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1192         struct drm_i915_private *dev_priv = dev->dev_private;
1193         u32 pp;
1194         u32 pp_stat_reg, pp_ctrl_reg;
1195
1196         WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1197
1198         if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
1199                 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1200
1201                 pp = ironlake_get_pp_control(intel_dp);
1202                 pp &= ~EDP_FORCE_VDD;
1203
1204                 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1205                 pp_stat_reg = _pp_stat_reg(intel_dp);
1206
1207                 I915_WRITE(pp_ctrl_reg, pp);
1208                 POSTING_READ(pp_ctrl_reg);
1209
1210                 /* Make sure sequencer is idle before allowing subsequent activity */
1211                 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1212                 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1213
1214                 if ((pp & POWER_TARGET_ON) == 0)
1215                         intel_dp->last_power_cycle = jiffies;
1216
1217                 intel_runtime_pm_put(dev_priv);
1218         }
1219 }
1220
1221 static void edp_panel_vdd_work(struct work_struct *__work)
1222 {
1223         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1224                                                  struct intel_dp, panel_vdd_work);
1225         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1226
1227         mutex_lock(&dev->mode_config.mutex);
1228         edp_panel_vdd_off_sync(intel_dp);
1229         mutex_unlock(&dev->mode_config.mutex);
1230 }
1231
1232 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1233 {
1234         if (!is_edp(intel_dp))
1235                 return;
1236
1237         WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1238
1239         intel_dp->want_panel_vdd = false;
1240
1241         if (sync) {
1242                 edp_panel_vdd_off_sync(intel_dp);
1243         } else {
1244                 /*
1245                  * Queue the timer to fire a long
1246                  * time from now (relative to the power down delay)
1247                  * to keep the panel power up across a sequence of operations
1248                  */
1249                 schedule_delayed_work(&intel_dp->panel_vdd_work,
1250                                       msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1251         }
1252 }
1253
1254 void intel_edp_panel_on(struct intel_dp *intel_dp)
1255 {
1256         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1257         struct drm_i915_private *dev_priv = dev->dev_private;
1258         u32 pp;
1259         u32 pp_ctrl_reg;
1260
1261         if (!is_edp(intel_dp))
1262                 return;
1263
1264         DRM_DEBUG_KMS("Turn eDP power on\n");
1265
1266         if (edp_have_panel_power(intel_dp)) {
1267                 DRM_DEBUG_KMS("eDP power already on\n");
1268                 return;
1269         }
1270
1271         wait_panel_power_cycle(intel_dp);
1272
1273         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1274         pp = ironlake_get_pp_control(intel_dp);
1275         if (IS_GEN5(dev)) {
1276                 /* ILK workaround: disable reset around power sequence */
1277                 pp &= ~PANEL_POWER_RESET;
1278                 I915_WRITE(pp_ctrl_reg, pp);
1279                 POSTING_READ(pp_ctrl_reg);
1280         }
1281
1282         pp |= POWER_TARGET_ON;
1283         if (!IS_GEN5(dev))
1284                 pp |= PANEL_POWER_RESET;
1285
1286         I915_WRITE(pp_ctrl_reg, pp);
1287         POSTING_READ(pp_ctrl_reg);
1288
1289         wait_panel_on(intel_dp);
1290         intel_dp->last_power_on = jiffies;
1291
1292         if (IS_GEN5(dev)) {
1293                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1294                 I915_WRITE(pp_ctrl_reg, pp);
1295                 POSTING_READ(pp_ctrl_reg);
1296         }
1297 }
1298
1299 void intel_edp_panel_off(struct intel_dp *intel_dp)
1300 {
1301         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1302         struct drm_i915_private *dev_priv = dev->dev_private;
1303         u32 pp;
1304         u32 pp_ctrl_reg;
1305
1306         if (!is_edp(intel_dp))
1307                 return;
1308
1309         DRM_DEBUG_KMS("Turn eDP power off\n");
1310
1311         edp_wait_backlight_off(intel_dp);
1312
1313         pp = ironlake_get_pp_control(intel_dp);
1314         /* We need to switch off panel power _and_ force vdd, for otherwise some
1315          * panels get very unhappy and cease to work. */
1316         pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1317
1318         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1319
1320         I915_WRITE(pp_ctrl_reg, pp);
1321         POSTING_READ(pp_ctrl_reg);
1322
1323         intel_dp->last_power_cycle = jiffies;
1324         wait_panel_off(intel_dp);
1325 }
1326
1327 void intel_edp_backlight_on(struct intel_dp *intel_dp)
1328 {
1329         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1330         struct drm_device *dev = intel_dig_port->base.base.dev;
1331         struct drm_i915_private *dev_priv = dev->dev_private;
1332         u32 pp;
1333         u32 pp_ctrl_reg;
1334
1335         if (!is_edp(intel_dp))
1336                 return;
1337
1338         DRM_DEBUG_KMS("\n");
1339         /*
1340          * If we enable the backlight right away following a panel power
1341          * on, we may see slight flicker as the panel syncs with the eDP
1342          * link.  So delay a bit to make sure the image is solid before
1343          * allowing it to appear.
1344          */
1345         wait_backlight_on(intel_dp);
1346         pp = ironlake_get_pp_control(intel_dp);
1347         pp |= EDP_BLC_ENABLE;
1348
1349         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1350
1351         I915_WRITE(pp_ctrl_reg, pp);
1352         POSTING_READ(pp_ctrl_reg);
1353
1354         intel_panel_enable_backlight(intel_dp->attached_connector);
1355 }
1356
1357 void intel_edp_backlight_off(struct intel_dp *intel_dp)
1358 {
1359         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1360         struct drm_i915_private *dev_priv = dev->dev_private;
1361         u32 pp;
1362         u32 pp_ctrl_reg;
1363
1364         if (!is_edp(intel_dp))
1365                 return;
1366
1367         intel_panel_disable_backlight(intel_dp->attached_connector);
1368
1369         DRM_DEBUG_KMS("\n");
1370         pp = ironlake_get_pp_control(intel_dp);
1371         pp &= ~EDP_BLC_ENABLE;
1372
1373         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1374
1375         I915_WRITE(pp_ctrl_reg, pp);
1376         POSTING_READ(pp_ctrl_reg);
1377         intel_dp->last_backlight_off = jiffies;
1378 }
1379
1380 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1381 {
1382         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1383         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1384         struct drm_device *dev = crtc->dev;
1385         struct drm_i915_private *dev_priv = dev->dev_private;
1386         u32 dpa_ctl;
1387
1388         assert_pipe_disabled(dev_priv,
1389                              to_intel_crtc(crtc)->pipe);
1390
1391         DRM_DEBUG_KMS("\n");
1392         dpa_ctl = I915_READ(DP_A);
1393         WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1394         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1395
1396         /* We don't adjust intel_dp->DP while tearing down the link, to
1397          * facilitate link retraining (e.g. after hotplug). Hence clear all
1398          * enable bits here to ensure that we don't enable too much. */
1399         intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1400         intel_dp->DP |= DP_PLL_ENABLE;
1401         I915_WRITE(DP_A, intel_dp->DP);
1402         POSTING_READ(DP_A);
1403         udelay(200);
1404 }
1405
1406 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1407 {
1408         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1409         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1410         struct drm_device *dev = crtc->dev;
1411         struct drm_i915_private *dev_priv = dev->dev_private;
1412         u32 dpa_ctl;
1413
1414         assert_pipe_disabled(dev_priv,
1415                              to_intel_crtc(crtc)->pipe);
1416
1417         dpa_ctl = I915_READ(DP_A);
1418         WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1419              "dp pll off, should be on\n");
1420         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1421
1422         /* We can't rely on the value tracked for the DP register in
1423          * intel_dp->DP because link_down must not change that (otherwise link
1424          * re-training will fail. */
1425         dpa_ctl &= ~DP_PLL_ENABLE;
1426         I915_WRITE(DP_A, dpa_ctl);
1427         POSTING_READ(DP_A);
1428         udelay(200);
1429 }
1430
1431 /* If the sink supports it, try to set the power state appropriately */
1432 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1433 {
1434         int ret, i;
1435
1436         /* Should have a valid DPCD by this point */
1437         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1438                 return;
1439
1440         if (mode != DRM_MODE_DPMS_ON) {
1441                 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1442                                                   DP_SET_POWER_D3);
1443                 if (ret != 1)
1444                         DRM_DEBUG_DRIVER("failed to write sink power state\n");
1445         } else {
1446                 /*
1447                  * When turning on, we need to retry for 1ms to give the sink
1448                  * time to wake up.
1449                  */
1450                 for (i = 0; i < 3; i++) {
1451                         ret = intel_dp_aux_native_write_1(intel_dp,
1452                                                           DP_SET_POWER,
1453                                                           DP_SET_POWER_D0);
1454                         if (ret == 1)
1455                                 break;
1456                         msleep(1);
1457                 }
1458         }
1459 }
1460
1461 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1462                                   enum pipe *pipe)
1463 {
1464         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1465         enum port port = dp_to_dig_port(intel_dp)->port;
1466         struct drm_device *dev = encoder->base.dev;
1467         struct drm_i915_private *dev_priv = dev->dev_private;
1468         u32 tmp = I915_READ(intel_dp->output_reg);
1469
1470         if (!(tmp & DP_PORT_EN))
1471                 return false;
1472
1473         if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1474                 *pipe = PORT_TO_PIPE_CPT(tmp);
1475         } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1476                 *pipe = PORT_TO_PIPE(tmp);
1477         } else {
1478                 u32 trans_sel;
1479                 u32 trans_dp;
1480                 int i;
1481
1482                 switch (intel_dp->output_reg) {
1483                 case PCH_DP_B:
1484                         trans_sel = TRANS_DP_PORT_SEL_B;
1485                         break;
1486                 case PCH_DP_C:
1487                         trans_sel = TRANS_DP_PORT_SEL_C;
1488                         break;
1489                 case PCH_DP_D:
1490                         trans_sel = TRANS_DP_PORT_SEL_D;
1491                         break;
1492                 default:
1493                         return true;
1494                 }
1495
1496                 for_each_pipe(i) {
1497                         trans_dp = I915_READ(TRANS_DP_CTL(i));
1498                         if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1499                                 *pipe = i;
1500                                 return true;
1501                         }
1502                 }
1503
1504                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1505                               intel_dp->output_reg);
1506         }
1507
1508         return true;
1509 }
1510
1511 static void intel_dp_get_config(struct intel_encoder *encoder,
1512                                 struct intel_crtc_config *pipe_config)
1513 {
1514         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1515         u32 tmp, flags = 0;
1516         struct drm_device *dev = encoder->base.dev;
1517         struct drm_i915_private *dev_priv = dev->dev_private;
1518         enum port port = dp_to_dig_port(intel_dp)->port;
1519         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1520         int dotclock;
1521
1522         if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1523                 tmp = I915_READ(intel_dp->output_reg);
1524                 if (tmp & DP_SYNC_HS_HIGH)
1525                         flags |= DRM_MODE_FLAG_PHSYNC;
1526                 else
1527                         flags |= DRM_MODE_FLAG_NHSYNC;
1528
1529                 if (tmp & DP_SYNC_VS_HIGH)
1530                         flags |= DRM_MODE_FLAG_PVSYNC;
1531                 else
1532                         flags |= DRM_MODE_FLAG_NVSYNC;
1533         } else {
1534                 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1535                 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1536                         flags |= DRM_MODE_FLAG_PHSYNC;
1537                 else
1538                         flags |= DRM_MODE_FLAG_NHSYNC;
1539
1540                 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1541                         flags |= DRM_MODE_FLAG_PVSYNC;
1542                 else
1543                         flags |= DRM_MODE_FLAG_NVSYNC;
1544         }
1545
1546         pipe_config->adjusted_mode.flags |= flags;
1547
1548         pipe_config->has_dp_encoder = true;
1549
1550         intel_dp_get_m_n(crtc, pipe_config);
1551
1552         if (port == PORT_A) {
1553                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1554                         pipe_config->port_clock = 162000;
1555                 else
1556                         pipe_config->port_clock = 270000;
1557         }
1558
1559         dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1560                                             &pipe_config->dp_m_n);
1561
1562         if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1563                 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1564
1565         pipe_config->adjusted_mode.crtc_clock = dotclock;
1566
1567         if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1568             pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1569                 /*
1570                  * This is a big fat ugly hack.
1571                  *
1572                  * Some machines in UEFI boot mode provide us a VBT that has 18
1573                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1574                  * unknown we fail to light up. Yet the same BIOS boots up with
1575                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1576                  * max, not what it tells us to use.
1577                  *
1578                  * Note: This will still be broken if the eDP panel is not lit
1579                  * up by the BIOS, and thus we can't get the mode at module
1580                  * load.
1581                  */
1582                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1583                               pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1584                 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1585         }
1586 }
1587
1588 static bool is_edp_psr(struct drm_device *dev)
1589 {
1590         struct drm_i915_private *dev_priv = dev->dev_private;
1591
1592         return dev_priv->psr.sink_support;
1593 }
1594
1595 static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1596 {
1597         struct drm_i915_private *dev_priv = dev->dev_private;
1598
1599         if (!HAS_PSR(dev))
1600                 return false;
1601
1602         return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1603 }
1604
1605 static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1606                                     struct edp_vsc_psr *vsc_psr)
1607 {
1608         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1609         struct drm_device *dev = dig_port->base.base.dev;
1610         struct drm_i915_private *dev_priv = dev->dev_private;
1611         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1612         u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1613         u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1614         uint32_t *data = (uint32_t *) vsc_psr;
1615         unsigned int i;
1616
1617         /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1618            the video DIP being updated before program video DIP data buffer
1619            registers for DIP being updated. */
1620         I915_WRITE(ctl_reg, 0);
1621         POSTING_READ(ctl_reg);
1622
1623         for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1624                 if (i < sizeof(struct edp_vsc_psr))
1625                         I915_WRITE(data_reg + i, *data++);
1626                 else
1627                         I915_WRITE(data_reg + i, 0);
1628         }
1629
1630         I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1631         POSTING_READ(ctl_reg);
1632 }
1633
1634 static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1635 {
1636         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1637         struct drm_i915_private *dev_priv = dev->dev_private;
1638         struct edp_vsc_psr psr_vsc;
1639
1640         if (intel_dp->psr_setup_done)
1641                 return;
1642
1643         /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1644         memset(&psr_vsc, 0, sizeof(psr_vsc));
1645         psr_vsc.sdp_header.HB0 = 0;
1646         psr_vsc.sdp_header.HB1 = 0x7;
1647         psr_vsc.sdp_header.HB2 = 0x2;
1648         psr_vsc.sdp_header.HB3 = 0x8;
1649         intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1650
1651         /* Avoid continuous PSR exit by masking memup and hpd */
1652         I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
1653                    EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
1654
1655         intel_dp->psr_setup_done = true;
1656 }
1657
1658 static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1659 {
1660         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1661         struct drm_i915_private *dev_priv = dev->dev_private;
1662         uint32_t aux_clock_divider;
1663         int precharge = 0x3;
1664         int msg_size = 5;       /* Header(4) + Message(1) */
1665
1666         aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1667
1668         /* Enable PSR in sink */
1669         if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
1670                 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1671                                             DP_PSR_ENABLE &
1672                                             ~DP_PSR_MAIN_LINK_ACTIVE);
1673         else
1674                 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1675                                             DP_PSR_ENABLE |
1676                                             DP_PSR_MAIN_LINK_ACTIVE);
1677
1678         /* Setup AUX registers */
1679         I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1680         I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1681         I915_WRITE(EDP_PSR_AUX_CTL(dev),
1682                    DP_AUX_CH_CTL_TIME_OUT_400us |
1683                    (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1684                    (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1685                    (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1686 }
1687
1688 static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1689 {
1690         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1691         struct drm_i915_private *dev_priv = dev->dev_private;
1692         uint32_t max_sleep_time = 0x1f;
1693         uint32_t idle_frames = 1;
1694         uint32_t val = 0x0;
1695         const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
1696
1697         if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1698                 val |= EDP_PSR_LINK_STANDBY;
1699                 val |= EDP_PSR_TP2_TP3_TIME_0us;
1700                 val |= EDP_PSR_TP1_TIME_0us;
1701                 val |= EDP_PSR_SKIP_AUX_EXIT;
1702         } else
1703                 val |= EDP_PSR_LINK_DISABLE;
1704
1705         I915_WRITE(EDP_PSR_CTL(dev), val |
1706                    IS_BROADWELL(dev) ? 0 : link_entry_time |
1707                    max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1708                    idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1709                    EDP_PSR_ENABLE);
1710 }
1711
1712 static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1713 {
1714         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1715         struct drm_device *dev = dig_port->base.base.dev;
1716         struct drm_i915_private *dev_priv = dev->dev_private;
1717         struct drm_crtc *crtc = dig_port->base.base.crtc;
1718         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1719         struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj;
1720         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1721
1722         dev_priv->psr.source_ok = false;
1723
1724         if (!HAS_PSR(dev)) {
1725                 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1726                 return false;
1727         }
1728
1729         if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1730             (dig_port->port != PORT_A)) {
1731                 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1732                 return false;
1733         }
1734
1735         if (!i915.enable_psr) {
1736                 DRM_DEBUG_KMS("PSR disable by flag\n");
1737                 return false;
1738         }
1739
1740         crtc = dig_port->base.base.crtc;
1741         if (crtc == NULL) {
1742                 DRM_DEBUG_KMS("crtc not active for PSR\n");
1743                 return false;
1744         }
1745
1746         intel_crtc = to_intel_crtc(crtc);
1747         if (!intel_crtc_active(crtc)) {
1748                 DRM_DEBUG_KMS("crtc not active for PSR\n");
1749                 return false;
1750         }
1751
1752         obj = to_intel_framebuffer(crtc->fb)->obj;
1753         if (obj->tiling_mode != I915_TILING_X ||
1754             obj->fence_reg == I915_FENCE_REG_NONE) {
1755                 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
1756                 return false;
1757         }
1758
1759         if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1760                 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
1761                 return false;
1762         }
1763
1764         if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1765             S3D_ENABLE) {
1766                 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1767                 return false;
1768         }
1769
1770         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
1771                 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1772                 return false;
1773         }
1774
1775         dev_priv->psr.source_ok = true;
1776         return true;
1777 }
1778
1779 static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
1780 {
1781         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1782
1783         if (!intel_edp_psr_match_conditions(intel_dp) ||
1784             intel_edp_is_psr_enabled(dev))
1785                 return;
1786
1787         /* Setup PSR once */
1788         intel_edp_psr_setup(intel_dp);
1789
1790         /* Enable PSR on the panel */
1791         intel_edp_psr_enable_sink(intel_dp);
1792
1793         /* Enable PSR on the host */
1794         intel_edp_psr_enable_source(intel_dp);
1795 }
1796
1797 void intel_edp_psr_enable(struct intel_dp *intel_dp)
1798 {
1799         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1800
1801         if (intel_edp_psr_match_conditions(intel_dp) &&
1802             !intel_edp_is_psr_enabled(dev))
1803                 intel_edp_psr_do_enable(intel_dp);
1804 }
1805
1806 void intel_edp_psr_disable(struct intel_dp *intel_dp)
1807 {
1808         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1809         struct drm_i915_private *dev_priv = dev->dev_private;
1810
1811         if (!intel_edp_is_psr_enabled(dev))
1812                 return;
1813
1814         I915_WRITE(EDP_PSR_CTL(dev),
1815                    I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
1816
1817         /* Wait till PSR is idle */
1818         if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
1819                        EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1820                 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1821 }
1822
1823 void intel_edp_psr_update(struct drm_device *dev)
1824 {
1825         struct intel_encoder *encoder;
1826         struct intel_dp *intel_dp = NULL;
1827
1828         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1829                 if (encoder->type == INTEL_OUTPUT_EDP) {
1830                         intel_dp = enc_to_intel_dp(&encoder->base);
1831
1832                         if (!is_edp_psr(dev))
1833                                 return;
1834
1835                         if (!intel_edp_psr_match_conditions(intel_dp))
1836                                 intel_edp_psr_disable(intel_dp);
1837                         else
1838                                 if (!intel_edp_is_psr_enabled(dev))
1839                                         intel_edp_psr_do_enable(intel_dp);
1840                 }
1841 }
1842
1843 static void intel_disable_dp(struct intel_encoder *encoder)
1844 {
1845         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1846         enum port port = dp_to_dig_port(intel_dp)->port;
1847         struct drm_device *dev = encoder->base.dev;
1848
1849         /* Make sure the panel is off before trying to change the mode. But also
1850          * ensure that we have vdd while we switch off the panel. */
1851         intel_edp_backlight_off(intel_dp);
1852         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
1853         intel_edp_panel_off(intel_dp);
1854
1855         /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1856         if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
1857                 intel_dp_link_down(intel_dp);
1858 }
1859
1860 static void intel_post_disable_dp(struct intel_encoder *encoder)
1861 {
1862         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1863         enum port port = dp_to_dig_port(intel_dp)->port;
1864         struct drm_device *dev = encoder->base.dev;
1865
1866         if (port == PORT_A || IS_VALLEYVIEW(dev)) {
1867                 intel_dp_link_down(intel_dp);
1868                 if (!IS_VALLEYVIEW(dev))
1869                         ironlake_edp_pll_off(intel_dp);
1870         }
1871 }
1872
1873 static void intel_enable_dp(struct intel_encoder *encoder)
1874 {
1875         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1876         struct drm_device *dev = encoder->base.dev;
1877         struct drm_i915_private *dev_priv = dev->dev_private;
1878         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1879
1880         if (WARN_ON(dp_reg & DP_PORT_EN))
1881                 return;
1882
1883         edp_panel_vdd_on(intel_dp);
1884         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1885         intel_dp_start_link_train(intel_dp);
1886         intel_edp_panel_on(intel_dp);
1887         edp_panel_vdd_off(intel_dp, true);
1888         intel_dp_complete_link_train(intel_dp);
1889         intel_dp_stop_link_train(intel_dp);
1890 }
1891
1892 static void g4x_enable_dp(struct intel_encoder *encoder)
1893 {
1894         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1895
1896         intel_enable_dp(encoder);
1897         intel_edp_backlight_on(intel_dp);
1898 }
1899
1900 static void vlv_enable_dp(struct intel_encoder *encoder)
1901 {
1902         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1903
1904         intel_edp_backlight_on(intel_dp);
1905 }
1906
1907 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
1908 {
1909         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1910         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1911
1912         if (dport->port == PORT_A)
1913                 ironlake_edp_pll_on(intel_dp);
1914 }
1915
1916 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
1917 {
1918         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1919         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1920         struct drm_device *dev = encoder->base.dev;
1921         struct drm_i915_private *dev_priv = dev->dev_private;
1922         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1923         enum dpio_channel port = vlv_dport_to_channel(dport);
1924         int pipe = intel_crtc->pipe;
1925         struct edp_power_seq power_seq;
1926         u32 val;
1927
1928         mutex_lock(&dev_priv->dpio_lock);
1929
1930         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1931         val = 0;
1932         if (pipe)
1933                 val |= (1<<21);
1934         else
1935                 val &= ~(1<<21);
1936         val |= 0x001000c4;
1937         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1938         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1939         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1940
1941         mutex_unlock(&dev_priv->dpio_lock);
1942
1943         if (is_edp(intel_dp)) {
1944                 /* init power sequencer on this pipe and port */
1945                 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
1946                 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
1947                                                               &power_seq);
1948         }
1949
1950         intel_enable_dp(encoder);
1951
1952         vlv_wait_port_ready(dev_priv, dport);
1953 }
1954
1955 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
1956 {
1957         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1958         struct drm_device *dev = encoder->base.dev;
1959         struct drm_i915_private *dev_priv = dev->dev_private;
1960         struct intel_crtc *intel_crtc =
1961                 to_intel_crtc(encoder->base.crtc);
1962         enum dpio_channel port = vlv_dport_to_channel(dport);
1963         int pipe = intel_crtc->pipe;
1964
1965         /* Program Tx lane resets to default */
1966         mutex_lock(&dev_priv->dpio_lock);
1967         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1968                          DPIO_PCS_TX_LANE2_RESET |
1969                          DPIO_PCS_TX_LANE1_RESET);
1970         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1971                          DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1972                          DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1973                          (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1974                                  DPIO_PCS_CLK_SOFT_RESET);
1975
1976         /* Fix up inter-pair skew failure */
1977         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1978         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1979         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1980         mutex_unlock(&dev_priv->dpio_lock);
1981 }
1982
1983 /*
1984  * Native read with retry for link status and receiver capability reads for
1985  * cases where the sink may still be asleep.
1986  */
1987 static bool
1988 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1989                                uint8_t *recv, int recv_bytes)
1990 {
1991         int ret, i;
1992
1993         /*
1994          * Sinks are *supposed* to come up within 1ms from an off state,
1995          * but we're also supposed to retry 3 times per the spec.
1996          */
1997         for (i = 0; i < 3; i++) {
1998                 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1999                                                recv_bytes);
2000                 if (ret == recv_bytes)
2001                         return true;
2002                 msleep(1);
2003         }
2004
2005         return false;
2006 }
2007
2008 /*
2009  * Fetch AUX CH registers 0x202 - 0x207 which contain
2010  * link status information
2011  */
2012 static bool
2013 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2014 {
2015         return intel_dp_aux_native_read_retry(intel_dp,
2016                                               DP_LANE0_1_STATUS,
2017                                               link_status,
2018                                               DP_LINK_STATUS_SIZE);
2019 }
2020
2021 /*
2022  * These are source-specific values; current Intel hardware supports
2023  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
2024  */
2025
2026 static uint8_t
2027 intel_dp_voltage_max(struct intel_dp *intel_dp)
2028 {
2029         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2030         enum port port = dp_to_dig_port(intel_dp)->port;
2031
2032         if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev))
2033                 return DP_TRAIN_VOLTAGE_SWING_1200;
2034         else if (IS_GEN7(dev) && port == PORT_A)
2035                 return DP_TRAIN_VOLTAGE_SWING_800;
2036         else if (HAS_PCH_CPT(dev) && port != PORT_A)
2037                 return DP_TRAIN_VOLTAGE_SWING_1200;
2038         else
2039                 return DP_TRAIN_VOLTAGE_SWING_800;
2040 }
2041
2042 static uint8_t
2043 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2044 {
2045         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2046         enum port port = dp_to_dig_port(intel_dp)->port;
2047
2048         if (IS_BROADWELL(dev)) {
2049                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2050                 case DP_TRAIN_VOLTAGE_SWING_400:
2051                 case DP_TRAIN_VOLTAGE_SWING_600:
2052                         return DP_TRAIN_PRE_EMPHASIS_6;
2053                 case DP_TRAIN_VOLTAGE_SWING_800:
2054                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2055                 case DP_TRAIN_VOLTAGE_SWING_1200:
2056                 default:
2057                         return DP_TRAIN_PRE_EMPHASIS_0;
2058                 }
2059         } else if (IS_HASWELL(dev)) {
2060                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2061                 case DP_TRAIN_VOLTAGE_SWING_400:
2062                         return DP_TRAIN_PRE_EMPHASIS_9_5;
2063                 case DP_TRAIN_VOLTAGE_SWING_600:
2064                         return DP_TRAIN_PRE_EMPHASIS_6;
2065                 case DP_TRAIN_VOLTAGE_SWING_800:
2066                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2067                 case DP_TRAIN_VOLTAGE_SWING_1200:
2068                 default:
2069                         return DP_TRAIN_PRE_EMPHASIS_0;
2070                 }
2071         } else if (IS_VALLEYVIEW(dev)) {
2072                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2073                 case DP_TRAIN_VOLTAGE_SWING_400:
2074                         return DP_TRAIN_PRE_EMPHASIS_9_5;
2075                 case DP_TRAIN_VOLTAGE_SWING_600:
2076                         return DP_TRAIN_PRE_EMPHASIS_6;
2077                 case DP_TRAIN_VOLTAGE_SWING_800:
2078                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2079                 case DP_TRAIN_VOLTAGE_SWING_1200:
2080                 default:
2081                         return DP_TRAIN_PRE_EMPHASIS_0;
2082                 }
2083         } else if (IS_GEN7(dev) && port == PORT_A) {
2084                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2085                 case DP_TRAIN_VOLTAGE_SWING_400:
2086                         return DP_TRAIN_PRE_EMPHASIS_6;
2087                 case DP_TRAIN_VOLTAGE_SWING_600:
2088                 case DP_TRAIN_VOLTAGE_SWING_800:
2089                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2090                 default:
2091                         return DP_TRAIN_PRE_EMPHASIS_0;
2092                 }
2093         } else {
2094                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2095                 case DP_TRAIN_VOLTAGE_SWING_400:
2096                         return DP_TRAIN_PRE_EMPHASIS_6;
2097                 case DP_TRAIN_VOLTAGE_SWING_600:
2098                         return DP_TRAIN_PRE_EMPHASIS_6;
2099                 case DP_TRAIN_VOLTAGE_SWING_800:
2100                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2101                 case DP_TRAIN_VOLTAGE_SWING_1200:
2102                 default:
2103                         return DP_TRAIN_PRE_EMPHASIS_0;
2104                 }
2105         }
2106 }
2107
2108 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2109 {
2110         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2111         struct drm_i915_private *dev_priv = dev->dev_private;
2112         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2113         struct intel_crtc *intel_crtc =
2114                 to_intel_crtc(dport->base.base.crtc);
2115         unsigned long demph_reg_value, preemph_reg_value,
2116                 uniqtranscale_reg_value;
2117         uint8_t train_set = intel_dp->train_set[0];
2118         enum dpio_channel port = vlv_dport_to_channel(dport);
2119         int pipe = intel_crtc->pipe;
2120
2121         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2122         case DP_TRAIN_PRE_EMPHASIS_0:
2123                 preemph_reg_value = 0x0004000;
2124                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2125                 case DP_TRAIN_VOLTAGE_SWING_400:
2126                         demph_reg_value = 0x2B405555;
2127                         uniqtranscale_reg_value = 0x552AB83A;
2128                         break;
2129                 case DP_TRAIN_VOLTAGE_SWING_600:
2130                         demph_reg_value = 0x2B404040;
2131                         uniqtranscale_reg_value = 0x5548B83A;
2132                         break;
2133                 case DP_TRAIN_VOLTAGE_SWING_800:
2134                         demph_reg_value = 0x2B245555;
2135                         uniqtranscale_reg_value = 0x5560B83A;
2136                         break;
2137                 case DP_TRAIN_VOLTAGE_SWING_1200:
2138                         demph_reg_value = 0x2B405555;
2139                         uniqtranscale_reg_value = 0x5598DA3A;
2140                         break;
2141                 default:
2142                         return 0;
2143                 }
2144                 break;
2145         case DP_TRAIN_PRE_EMPHASIS_3_5:
2146                 preemph_reg_value = 0x0002000;
2147                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2148                 case DP_TRAIN_VOLTAGE_SWING_400:
2149                         demph_reg_value = 0x2B404040;
2150                         uniqtranscale_reg_value = 0x5552B83A;
2151                         break;
2152                 case DP_TRAIN_VOLTAGE_SWING_600:
2153                         demph_reg_value = 0x2B404848;
2154                         uniqtranscale_reg_value = 0x5580B83A;
2155                         break;
2156                 case DP_TRAIN_VOLTAGE_SWING_800:
2157                         demph_reg_value = 0x2B404040;
2158                         uniqtranscale_reg_value = 0x55ADDA3A;
2159                         break;
2160                 default:
2161                         return 0;
2162                 }
2163                 break;
2164         case DP_TRAIN_PRE_EMPHASIS_6:
2165                 preemph_reg_value = 0x0000000;
2166                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2167                 case DP_TRAIN_VOLTAGE_SWING_400:
2168                         demph_reg_value = 0x2B305555;
2169                         uniqtranscale_reg_value = 0x5570B83A;
2170                         break;
2171                 case DP_TRAIN_VOLTAGE_SWING_600:
2172                         demph_reg_value = 0x2B2B4040;
2173                         uniqtranscale_reg_value = 0x55ADDA3A;
2174                         break;
2175                 default:
2176                         return 0;
2177                 }
2178                 break;
2179         case DP_TRAIN_PRE_EMPHASIS_9_5:
2180                 preemph_reg_value = 0x0006000;
2181                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2182                 case DP_TRAIN_VOLTAGE_SWING_400:
2183                         demph_reg_value = 0x1B405555;
2184                         uniqtranscale_reg_value = 0x55ADDA3A;
2185                         break;
2186                 default:
2187                         return 0;
2188                 }
2189                 break;
2190         default:
2191                 return 0;
2192         }
2193
2194         mutex_lock(&dev_priv->dpio_lock);
2195         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2196         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2197         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
2198                          uniqtranscale_reg_value);
2199         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2200         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2201         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2202         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
2203         mutex_unlock(&dev_priv->dpio_lock);
2204
2205         return 0;
2206 }
2207
2208 static void
2209 intel_get_adjust_train(struct intel_dp *intel_dp,
2210                        const uint8_t link_status[DP_LINK_STATUS_SIZE])
2211 {
2212         uint8_t v = 0;
2213         uint8_t p = 0;
2214         int lane;
2215         uint8_t voltage_max;
2216         uint8_t preemph_max;
2217
2218         for (lane = 0; lane < intel_dp->lane_count; lane++) {
2219                 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2220                 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
2221
2222                 if (this_v > v)
2223                         v = this_v;
2224                 if (this_p > p)
2225                         p = this_p;
2226         }
2227
2228         voltage_max = intel_dp_voltage_max(intel_dp);
2229         if (v >= voltage_max)
2230                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
2231
2232         preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2233         if (p >= preemph_max)
2234                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
2235
2236         for (lane = 0; lane < 4; lane++)
2237                 intel_dp->train_set[lane] = v | p;
2238 }
2239
2240 static uint32_t
2241 intel_gen4_signal_levels(uint8_t train_set)
2242 {
2243         uint32_t        signal_levels = 0;
2244
2245         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2246         case DP_TRAIN_VOLTAGE_SWING_400:
2247         default:
2248                 signal_levels |= DP_VOLTAGE_0_4;
2249                 break;
2250         case DP_TRAIN_VOLTAGE_SWING_600:
2251                 signal_levels |= DP_VOLTAGE_0_6;
2252                 break;
2253         case DP_TRAIN_VOLTAGE_SWING_800:
2254                 signal_levels |= DP_VOLTAGE_0_8;
2255                 break;
2256         case DP_TRAIN_VOLTAGE_SWING_1200:
2257                 signal_levels |= DP_VOLTAGE_1_2;
2258                 break;
2259         }
2260         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2261         case DP_TRAIN_PRE_EMPHASIS_0:
2262         default:
2263                 signal_levels |= DP_PRE_EMPHASIS_0;
2264                 break;
2265         case DP_TRAIN_PRE_EMPHASIS_3_5:
2266                 signal_levels |= DP_PRE_EMPHASIS_3_5;
2267                 break;
2268         case DP_TRAIN_PRE_EMPHASIS_6:
2269                 signal_levels |= DP_PRE_EMPHASIS_6;
2270                 break;
2271         case DP_TRAIN_PRE_EMPHASIS_9_5:
2272                 signal_levels |= DP_PRE_EMPHASIS_9_5;
2273                 break;
2274         }
2275         return signal_levels;
2276 }
2277
2278 /* Gen6's DP voltage swing and pre-emphasis control */
2279 static uint32_t
2280 intel_gen6_edp_signal_levels(uint8_t train_set)
2281 {
2282         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2283                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2284         switch (signal_levels) {
2285         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2286         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2287                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2288         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2289                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
2290         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2291         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2292                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
2293         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2294         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2295                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
2296         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2297         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2298                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
2299         default:
2300                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2301                               "0x%x\n", signal_levels);
2302                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2303         }
2304 }
2305
2306 /* Gen7's DP voltage swing and pre-emphasis control */
2307 static uint32_t
2308 intel_gen7_edp_signal_levels(uint8_t train_set)
2309 {
2310         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2311                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2312         switch (signal_levels) {
2313         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2314                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2315         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2316                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2317         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2318                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2319
2320         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2321                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2322         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2323                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2324
2325         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2326                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2327         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2328                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2329
2330         default:
2331                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2332                               "0x%x\n", signal_levels);
2333                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2334         }
2335 }
2336
2337 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2338 static uint32_t
2339 intel_hsw_signal_levels(uint8_t train_set)
2340 {
2341         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2342                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2343         switch (signal_levels) {
2344         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2345                 return DDI_BUF_EMP_400MV_0DB_HSW;
2346         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2347                 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2348         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2349                 return DDI_BUF_EMP_400MV_6DB_HSW;
2350         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2351                 return DDI_BUF_EMP_400MV_9_5DB_HSW;
2352
2353         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2354                 return DDI_BUF_EMP_600MV_0DB_HSW;
2355         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2356                 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2357         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2358                 return DDI_BUF_EMP_600MV_6DB_HSW;
2359
2360         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2361                 return DDI_BUF_EMP_800MV_0DB_HSW;
2362         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2363                 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2364         default:
2365                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2366                               "0x%x\n", signal_levels);
2367                 return DDI_BUF_EMP_400MV_0DB_HSW;
2368         }
2369 }
2370
2371 static uint32_t
2372 intel_bdw_signal_levels(uint8_t train_set)
2373 {
2374         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2375                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2376         switch (signal_levels) {
2377         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2378                 return DDI_BUF_EMP_400MV_0DB_BDW;       /* Sel0 */
2379         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2380                 return DDI_BUF_EMP_400MV_3_5DB_BDW;     /* Sel1 */
2381         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2382                 return DDI_BUF_EMP_400MV_6DB_BDW;       /* Sel2 */
2383
2384         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2385                 return DDI_BUF_EMP_600MV_0DB_BDW;       /* Sel3 */
2386         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2387                 return DDI_BUF_EMP_600MV_3_5DB_BDW;     /* Sel4 */
2388         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2389                 return DDI_BUF_EMP_600MV_6DB_BDW;       /* Sel5 */
2390
2391         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2392                 return DDI_BUF_EMP_800MV_0DB_BDW;       /* Sel6 */
2393         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2394                 return DDI_BUF_EMP_800MV_3_5DB_BDW;     /* Sel7 */
2395
2396         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2397                 return DDI_BUF_EMP_1200MV_0DB_BDW;      /* Sel8 */
2398
2399         default:
2400                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2401                               "0x%x\n", signal_levels);
2402                 return DDI_BUF_EMP_400MV_0DB_BDW;       /* Sel0 */
2403         }
2404 }
2405
2406 /* Properly updates "DP" with the correct signal levels. */
2407 static void
2408 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2409 {
2410         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2411         enum port port = intel_dig_port->port;
2412         struct drm_device *dev = intel_dig_port->base.base.dev;
2413         uint32_t signal_levels, mask;
2414         uint8_t train_set = intel_dp->train_set[0];
2415
2416         if (IS_BROADWELL(dev)) {
2417                 signal_levels = intel_bdw_signal_levels(train_set);
2418                 mask = DDI_BUF_EMP_MASK;
2419         } else if (IS_HASWELL(dev)) {
2420                 signal_levels = intel_hsw_signal_levels(train_set);
2421                 mask = DDI_BUF_EMP_MASK;
2422         } else if (IS_VALLEYVIEW(dev)) {
2423                 signal_levels = intel_vlv_signal_levels(intel_dp);
2424                 mask = 0;
2425         } else if (IS_GEN7(dev) && port == PORT_A) {
2426                 signal_levels = intel_gen7_edp_signal_levels(train_set);
2427                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
2428         } else if (IS_GEN6(dev) && port == PORT_A) {
2429                 signal_levels = intel_gen6_edp_signal_levels(train_set);
2430                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2431         } else {
2432                 signal_levels = intel_gen4_signal_levels(train_set);
2433                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2434         }
2435
2436         DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2437
2438         *DP = (*DP & ~mask) | signal_levels;
2439 }
2440
2441 static bool
2442 intel_dp_set_link_train(struct intel_dp *intel_dp,
2443                         uint32_t *DP,
2444                         uint8_t dp_train_pat)
2445 {
2446         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2447         struct drm_device *dev = intel_dig_port->base.base.dev;
2448         struct drm_i915_private *dev_priv = dev->dev_private;
2449         enum port port = intel_dig_port->port;
2450         uint8_t buf[sizeof(intel_dp->train_set) + 1];
2451         int ret, len;
2452
2453         if (HAS_DDI(dev)) {
2454                 uint32_t temp = I915_READ(DP_TP_CTL(port));
2455
2456                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2457                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2458                 else
2459                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2460
2461                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2462                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2463                 case DP_TRAINING_PATTERN_DISABLE:
2464                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2465
2466                         break;
2467                 case DP_TRAINING_PATTERN_1:
2468                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2469                         break;
2470                 case DP_TRAINING_PATTERN_2:
2471                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2472                         break;
2473                 case DP_TRAINING_PATTERN_3:
2474                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2475                         break;
2476                 }
2477                 I915_WRITE(DP_TP_CTL(port), temp);
2478
2479         } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2480                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2481
2482                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2483                 case DP_TRAINING_PATTERN_DISABLE:
2484                         *DP |= DP_LINK_TRAIN_OFF_CPT;
2485                         break;
2486                 case DP_TRAINING_PATTERN_1:
2487                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2488                         break;
2489                 case DP_TRAINING_PATTERN_2:
2490                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2491                         break;
2492                 case DP_TRAINING_PATTERN_3:
2493                         DRM_ERROR("DP training pattern 3 not supported\n");
2494                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2495                         break;
2496                 }
2497
2498         } else {
2499                 *DP &= ~DP_LINK_TRAIN_MASK;
2500
2501                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2502                 case DP_TRAINING_PATTERN_DISABLE:
2503                         *DP |= DP_LINK_TRAIN_OFF;
2504                         break;
2505                 case DP_TRAINING_PATTERN_1:
2506                         *DP |= DP_LINK_TRAIN_PAT_1;
2507                         break;
2508                 case DP_TRAINING_PATTERN_2:
2509                         *DP |= DP_LINK_TRAIN_PAT_2;
2510                         break;
2511                 case DP_TRAINING_PATTERN_3:
2512                         DRM_ERROR("DP training pattern 3 not supported\n");
2513                         *DP |= DP_LINK_TRAIN_PAT_2;
2514                         break;
2515                 }
2516         }
2517
2518         I915_WRITE(intel_dp->output_reg, *DP);
2519         POSTING_READ(intel_dp->output_reg);
2520
2521         buf[0] = dp_train_pat;
2522         if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
2523             DP_TRAINING_PATTERN_DISABLE) {
2524                 /* don't write DP_TRAINING_LANEx_SET on disable */
2525                 len = 1;
2526         } else {
2527                 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2528                 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
2529                 len = intel_dp->lane_count + 1;
2530         }
2531
2532         ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_PATTERN_SET,
2533                                         buf, len);
2534
2535         return ret == len;
2536 }
2537
2538 static bool
2539 intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2540                         uint8_t dp_train_pat)
2541 {
2542         memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
2543         intel_dp_set_signal_levels(intel_dp, DP);
2544         return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
2545 }
2546
2547 static bool
2548 intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2549                            const uint8_t link_status[DP_LINK_STATUS_SIZE])
2550 {
2551         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2552         struct drm_device *dev = intel_dig_port->base.base.dev;
2553         struct drm_i915_private *dev_priv = dev->dev_private;
2554         int ret;
2555
2556         intel_get_adjust_train(intel_dp, link_status);
2557         intel_dp_set_signal_levels(intel_dp, DP);
2558
2559         I915_WRITE(intel_dp->output_reg, *DP);
2560         POSTING_READ(intel_dp->output_reg);
2561
2562         ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_LANE0_SET,
2563                                         intel_dp->train_set,
2564                                         intel_dp->lane_count);
2565
2566         return ret == intel_dp->lane_count;
2567 }
2568
2569 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2570 {
2571         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2572         struct drm_device *dev = intel_dig_port->base.base.dev;
2573         struct drm_i915_private *dev_priv = dev->dev_private;
2574         enum port port = intel_dig_port->port;
2575         uint32_t val;
2576
2577         if (!HAS_DDI(dev))
2578                 return;
2579
2580         val = I915_READ(DP_TP_CTL(port));
2581         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2582         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2583         I915_WRITE(DP_TP_CTL(port), val);
2584
2585         /*
2586          * On PORT_A we can have only eDP in SST mode. There the only reason
2587          * we need to set idle transmission mode is to work around a HW issue
2588          * where we enable the pipe while not in idle link-training mode.
2589          * In this case there is requirement to wait for a minimum number of
2590          * idle patterns to be sent.
2591          */
2592         if (port == PORT_A)
2593                 return;
2594
2595         if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2596                      1))
2597                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2598 }
2599
2600 /* Enable corresponding port and start training pattern 1 */
2601 void
2602 intel_dp_start_link_train(struct intel_dp *intel_dp)
2603 {
2604         struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
2605         struct drm_device *dev = encoder->dev;
2606         int i;
2607         uint8_t voltage;
2608         int voltage_tries, loop_tries;
2609         uint32_t DP = intel_dp->DP;
2610         uint8_t link_config[2];
2611
2612         if (HAS_DDI(dev))
2613                 intel_ddi_prepare_link_retrain(encoder);
2614
2615         /* Write the link configuration data */
2616         link_config[0] = intel_dp->link_bw;
2617         link_config[1] = intel_dp->lane_count;
2618         if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2619                 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
2620         intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, link_config, 2);
2621
2622         link_config[0] = 0;
2623         link_config[1] = DP_SET_ANSI_8B10B;
2624         intel_dp_aux_native_write(intel_dp, DP_DOWNSPREAD_CTRL, link_config, 2);
2625
2626         DP |= DP_PORT_EN;
2627
2628         /* clock recovery */
2629         if (!intel_dp_reset_link_train(intel_dp, &DP,
2630                                        DP_TRAINING_PATTERN_1 |
2631                                        DP_LINK_SCRAMBLING_DISABLE)) {
2632                 DRM_ERROR("failed to enable link training\n");
2633                 return;
2634         }
2635
2636         voltage = 0xff;
2637         voltage_tries = 0;
2638         loop_tries = 0;
2639         for (;;) {
2640                 uint8_t link_status[DP_LINK_STATUS_SIZE];
2641
2642                 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
2643                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2644                         DRM_ERROR("failed to get link status\n");
2645                         break;
2646                 }
2647
2648                 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2649                         DRM_DEBUG_KMS("clock recovery OK\n");
2650                         break;
2651                 }
2652
2653                 /* Check to see if we've tried the max voltage */
2654                 for (i = 0; i < intel_dp->lane_count; i++)
2655                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
2656                                 break;
2657                 if (i == intel_dp->lane_count) {
2658                         ++loop_tries;
2659                         if (loop_tries == 5) {
2660                                 DRM_ERROR("too many full retries, give up\n");
2661                                 break;
2662                         }
2663                         intel_dp_reset_link_train(intel_dp, &DP,
2664                                                   DP_TRAINING_PATTERN_1 |
2665                                                   DP_LINK_SCRAMBLING_DISABLE);
2666                         voltage_tries = 0;
2667                         continue;
2668                 }
2669
2670                 /* Check to see if we've tried the same voltage 5 times */
2671                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
2672                         ++voltage_tries;
2673                         if (voltage_tries == 5) {
2674                                 DRM_ERROR("too many voltage retries, give up\n");
2675                                 break;
2676                         }
2677                 } else
2678                         voltage_tries = 0;
2679                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
2680
2681                 /* Update training set as requested by target */
2682                 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2683                         DRM_ERROR("failed to update link training\n");
2684                         break;
2685                 }
2686         }
2687
2688         intel_dp->DP = DP;
2689 }
2690
2691 void
2692 intel_dp_complete_link_train(struct intel_dp *intel_dp)
2693 {
2694         bool channel_eq = false;
2695         int tries, cr_tries;
2696         uint32_t DP = intel_dp->DP;
2697         uint32_t training_pattern = DP_TRAINING_PATTERN_2;
2698
2699         /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
2700         if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
2701                 training_pattern = DP_TRAINING_PATTERN_3;
2702
2703         /* channel equalization */
2704         if (!intel_dp_set_link_train(intel_dp, &DP,
2705                                      training_pattern |
2706                                      DP_LINK_SCRAMBLING_DISABLE)) {
2707                 DRM_ERROR("failed to start channel equalization\n");
2708                 return;
2709         }
2710
2711         tries = 0;
2712         cr_tries = 0;
2713         channel_eq = false;
2714         for (;;) {
2715                 uint8_t link_status[DP_LINK_STATUS_SIZE];
2716
2717                 if (cr_tries > 5) {
2718                         DRM_ERROR("failed to train DP, aborting\n");
2719                         break;
2720                 }
2721
2722                 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
2723                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2724                         DRM_ERROR("failed to get link status\n");
2725                         break;
2726                 }
2727
2728                 /* Make sure clock is still ok */
2729                 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2730                         intel_dp_start_link_train(intel_dp);
2731                         intel_dp_set_link_train(intel_dp, &DP,
2732                                                 training_pattern |
2733                                                 DP_LINK_SCRAMBLING_DISABLE);
2734                         cr_tries++;
2735                         continue;
2736                 }
2737
2738                 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2739                         channel_eq = true;
2740                         break;
2741                 }
2742
2743                 /* Try 5 times, then try clock recovery if that fails */
2744                 if (tries > 5) {
2745                         intel_dp_link_down(intel_dp);
2746                         intel_dp_start_link_train(intel_dp);
2747                         intel_dp_set_link_train(intel_dp, &DP,
2748                                                 training_pattern |
2749                                                 DP_LINK_SCRAMBLING_DISABLE);
2750                         tries = 0;
2751                         cr_tries++;
2752                         continue;
2753                 }
2754
2755                 /* Update training set as requested by target */
2756                 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2757                         DRM_ERROR("failed to update link training\n");
2758                         break;
2759                 }
2760                 ++tries;
2761         }
2762
2763         intel_dp_set_idle_link_train(intel_dp);
2764
2765         intel_dp->DP = DP;
2766
2767         if (channel_eq)
2768                 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
2769
2770 }
2771
2772 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2773 {
2774         intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2775                                 DP_TRAINING_PATTERN_DISABLE);
2776 }
2777
2778 static void
2779 intel_dp_link_down(struct intel_dp *intel_dp)
2780 {
2781         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2782         enum port port = intel_dig_port->port;
2783         struct drm_device *dev = intel_dig_port->base.base.dev;
2784         struct drm_i915_private *dev_priv = dev->dev_private;
2785         struct intel_crtc *intel_crtc =
2786                 to_intel_crtc(intel_dig_port->base.base.crtc);
2787         uint32_t DP = intel_dp->DP;
2788
2789         /*
2790          * DDI code has a strict mode set sequence and we should try to respect
2791          * it, otherwise we might hang the machine in many different ways. So we
2792          * really should be disabling the port only on a complete crtc_disable
2793          * sequence. This function is just called under two conditions on DDI
2794          * code:
2795          * - Link train failed while doing crtc_enable, and on this case we
2796          *   really should respect the mode set sequence and wait for a
2797          *   crtc_disable.
2798          * - Someone turned the monitor off and intel_dp_check_link_status
2799          *   called us. We don't need to disable the whole port on this case, so
2800          *   when someone turns the monitor on again,
2801          *   intel_ddi_prepare_link_retrain will take care of redoing the link
2802          *   train.
2803          */
2804         if (HAS_DDI(dev))
2805                 return;
2806
2807         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2808                 return;
2809
2810         DRM_DEBUG_KMS("\n");
2811
2812         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2813                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
2814                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2815         } else {
2816                 DP &= ~DP_LINK_TRAIN_MASK;
2817                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2818         }
2819         POSTING_READ(intel_dp->output_reg);
2820
2821         /* We don't really know why we're doing this */
2822         intel_wait_for_vblank(dev, intel_crtc->pipe);
2823
2824         if (HAS_PCH_IBX(dev) &&
2825             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2826                 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2827
2828                 /* Hardware workaround: leaving our transcoder select
2829                  * set to transcoder B while it's off will prevent the
2830                  * corresponding HDMI output on transcoder A.
2831                  *
2832                  * Combine this with another hardware workaround:
2833                  * transcoder select bit can only be cleared while the
2834                  * port is enabled.
2835                  */
2836                 DP &= ~DP_PIPEB_SELECT;
2837                 I915_WRITE(intel_dp->output_reg, DP);
2838
2839                 /* Changes to enable or select take place the vblank
2840                  * after being written.
2841                  */
2842                 if (WARN_ON(crtc == NULL)) {
2843                         /* We should never try to disable a port without a crtc
2844                          * attached. For paranoia keep the code around for a
2845                          * bit. */
2846                         POSTING_READ(intel_dp->output_reg);
2847                         msleep(50);
2848                 } else
2849                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2850         }
2851
2852         DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2853         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2854         POSTING_READ(intel_dp->output_reg);
2855         msleep(intel_dp->panel_power_down_delay);
2856 }
2857
2858 static bool
2859 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2860 {
2861         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2862         struct drm_device *dev = dig_port->base.base.dev;
2863         struct drm_i915_private *dev_priv = dev->dev_private;
2864
2865         char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2866
2867         if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2868                                            sizeof(intel_dp->dpcd)) == 0)
2869                 return false; /* aux transfer failed */
2870
2871         hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2872                            32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2873         DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2874
2875         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2876                 return false; /* DPCD not present */
2877
2878         /* Check if the panel supports PSR */
2879         memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
2880         if (is_edp(intel_dp)) {
2881                 intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT,
2882                                                intel_dp->psr_dpcd,
2883                                                sizeof(intel_dp->psr_dpcd));
2884                 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
2885                         dev_priv->psr.sink_support = true;
2886                         DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
2887                 }
2888         }
2889
2890         /* Training Pattern 3 support */
2891         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
2892             intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
2893                 intel_dp->use_tps3 = true;
2894                 DRM_DEBUG_KMS("Displayport TPS3 supported");
2895         } else
2896                 intel_dp->use_tps3 = false;
2897
2898         if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2899               DP_DWN_STRM_PORT_PRESENT))
2900                 return true; /* native DP sink */
2901
2902         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2903                 return true; /* no per-port downstream info */
2904
2905         if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2906                                            intel_dp->downstream_ports,
2907                                            DP_MAX_DOWNSTREAM_PORTS) == 0)
2908                 return false; /* downstream port status fetch failed */
2909
2910         return true;
2911 }
2912
2913 static void
2914 intel_dp_probe_oui(struct intel_dp *intel_dp)
2915 {
2916         u8 buf[3];
2917
2918         if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2919                 return;
2920
2921         edp_panel_vdd_on(intel_dp);
2922
2923         if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2924                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2925                               buf[0], buf[1], buf[2]);
2926
2927         if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2928                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2929                               buf[0], buf[1], buf[2]);
2930
2931         edp_panel_vdd_off(intel_dp, false);
2932 }
2933
2934 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
2935 {
2936         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2937         struct drm_device *dev = intel_dig_port->base.base.dev;
2938         struct intel_crtc *intel_crtc =
2939                 to_intel_crtc(intel_dig_port->base.base.crtc);
2940         u8 buf[1];
2941
2942         if (!intel_dp_aux_native_read(intel_dp, DP_TEST_SINK_MISC, buf, 1))
2943                 return -EAGAIN;
2944
2945         if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
2946                 return -ENOTTY;
2947
2948         if (!intel_dp_aux_native_write_1(intel_dp, DP_TEST_SINK,
2949                                          DP_TEST_SINK_START))
2950                 return -EAGAIN;
2951
2952         /* Wait 2 vblanks to be sure we will have the correct CRC value */
2953         intel_wait_for_vblank(dev, intel_crtc->pipe);
2954         intel_wait_for_vblank(dev, intel_crtc->pipe);
2955
2956         if (!intel_dp_aux_native_read(intel_dp, DP_TEST_CRC_R_CR, crc, 6))
2957                 return -EAGAIN;
2958
2959         intel_dp_aux_native_write_1(intel_dp, DP_TEST_SINK, 0);
2960         return 0;
2961 }
2962
2963 static bool
2964 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2965 {
2966         int ret;
2967
2968         ret = intel_dp_aux_native_read_retry(intel_dp,
2969                                              DP_DEVICE_SERVICE_IRQ_VECTOR,
2970                                              sink_irq_vector, 1);
2971         if (!ret)
2972                 return false;
2973
2974         return true;
2975 }
2976
2977 static void
2978 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2979 {
2980         /* NAK by default */
2981         intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
2982 }
2983
2984 /*
2985  * According to DP spec
2986  * 5.1.2:
2987  *  1. Read DPCD
2988  *  2. Configure link according to Receiver Capabilities
2989  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
2990  *  4. Check link status on receipt of hot-plug interrupt
2991  */
2992
2993 void
2994 intel_dp_check_link_status(struct intel_dp *intel_dp)
2995 {
2996         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2997         u8 sink_irq_vector;
2998         u8 link_status[DP_LINK_STATUS_SIZE];
2999
3000         if (!intel_encoder->connectors_active)
3001                 return;
3002
3003         if (WARN_ON(!intel_encoder->base.crtc))
3004                 return;
3005
3006         /* Try to read receiver status if the link appears to be up */
3007         if (!intel_dp_get_link_status(intel_dp, link_status)) {
3008                 return;
3009         }
3010
3011         /* Now read the DPCD to see if it's actually running */
3012         if (!intel_dp_get_dpcd(intel_dp)) {
3013                 return;
3014         }
3015
3016         /* Try to read the source of the interrupt */
3017         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3018             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3019                 /* Clear interrupt source */
3020                 intel_dp_aux_native_write_1(intel_dp,
3021                                             DP_DEVICE_SERVICE_IRQ_VECTOR,
3022                                             sink_irq_vector);
3023
3024                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3025                         intel_dp_handle_test_request(intel_dp);
3026                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3027                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3028         }
3029
3030         if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3031                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
3032                               drm_get_encoder_name(&intel_encoder->base));
3033                 intel_dp_start_link_train(intel_dp);
3034                 intel_dp_complete_link_train(intel_dp);
3035                 intel_dp_stop_link_train(intel_dp);
3036         }
3037 }
3038
3039 /* XXX this is probably wrong for multiple downstream ports */
3040 static enum drm_connector_status
3041 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
3042 {
3043         uint8_t *dpcd = intel_dp->dpcd;
3044         uint8_t type;
3045
3046         if (!intel_dp_get_dpcd(intel_dp))
3047                 return connector_status_disconnected;
3048
3049         /* if there's no downstream port, we're done */
3050         if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
3051                 return connector_status_connected;
3052
3053         /* If we're HPD-aware, SINK_COUNT changes dynamically */
3054         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3055             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
3056                 uint8_t reg;
3057                 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
3058                                                     &reg, 1))
3059                         return connector_status_unknown;
3060                 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3061                                               : connector_status_disconnected;
3062         }
3063
3064         /* If no HPD, poke DDC gently */
3065         if (drm_probe_ddc(&intel_dp->adapter))
3066                 return connector_status_connected;
3067
3068         /* Well we tried, say unknown for unreliable port types */
3069         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3070                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3071                 if (type == DP_DS_PORT_TYPE_VGA ||
3072                     type == DP_DS_PORT_TYPE_NON_EDID)
3073                         return connector_status_unknown;
3074         } else {
3075                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3076                         DP_DWN_STRM_PORT_TYPE_MASK;
3077                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3078                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
3079                         return connector_status_unknown;
3080         }
3081
3082         /* Anything else is out of spec, warn and ignore */
3083         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
3084         return connector_status_disconnected;
3085 }
3086
3087 static enum drm_connector_status
3088 ironlake_dp_detect(struct intel_dp *intel_dp)
3089 {
3090         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3091         struct drm_i915_private *dev_priv = dev->dev_private;
3092         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3093         enum drm_connector_status status;
3094
3095         /* Can't disconnect eDP, but you can close the lid... */
3096         if (is_edp(intel_dp)) {
3097                 status = intel_panel_detect(dev);
3098                 if (status == connector_status_unknown)
3099                         status = connector_status_connected;
3100                 return status;
3101         }
3102
3103         if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3104                 return connector_status_disconnected;
3105
3106         return intel_dp_detect_dpcd(intel_dp);
3107 }
3108
3109 static enum drm_connector_status
3110 g4x_dp_detect(struct intel_dp *intel_dp)
3111 {
3112         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3113         struct drm_i915_private *dev_priv = dev->dev_private;
3114         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3115         uint32_t bit;
3116
3117         /* Can't disconnect eDP, but you can close the lid... */
3118         if (is_edp(intel_dp)) {
3119                 enum drm_connector_status status;
3120
3121                 status = intel_panel_detect(dev);
3122                 if (status == connector_status_unknown)
3123                         status = connector_status_connected;
3124                 return status;
3125         }
3126
3127         if (IS_VALLEYVIEW(dev)) {
3128                 switch (intel_dig_port->port) {
3129                 case PORT_B:
3130                         bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3131                         break;
3132                 case PORT_C:
3133                         bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3134                         break;
3135                 case PORT_D:
3136                         bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3137                         break;
3138                 default:
3139                         return connector_status_unknown;
3140                 }
3141         } else {
3142                 switch (intel_dig_port->port) {
3143                 case PORT_B:
3144                         bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3145                         break;
3146                 case PORT_C:
3147                         bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3148                         break;
3149                 case PORT_D:
3150                         bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3151                         break;
3152                 default:
3153                         return connector_status_unknown;
3154                 }
3155         }
3156
3157         if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
3158                 return connector_status_disconnected;
3159
3160         return intel_dp_detect_dpcd(intel_dp);
3161 }
3162
3163 static struct edid *
3164 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3165 {
3166         struct intel_connector *intel_connector = to_intel_connector(connector);
3167
3168         /* use cached edid if we have one */
3169         if (intel_connector->edid) {
3170                 /* invalid edid */
3171                 if (IS_ERR(intel_connector->edid))
3172                         return NULL;
3173
3174                 return drm_edid_duplicate(intel_connector->edid);
3175         }
3176
3177         return drm_get_edid(connector, adapter);
3178 }
3179
3180 static int
3181 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3182 {
3183         struct intel_connector *intel_connector = to_intel_connector(connector);
3184
3185         /* use cached edid if we have one */
3186         if (intel_connector->edid) {
3187                 /* invalid edid */
3188                 if (IS_ERR(intel_connector->edid))
3189                         return 0;
3190
3191                 return intel_connector_update_modes(connector,
3192                                                     intel_connector->edid);
3193         }
3194
3195         return intel_ddc_get_modes(connector, adapter);
3196 }
3197
3198 static enum drm_connector_status
3199 intel_dp_detect(struct drm_connector *connector, bool force)
3200 {
3201         struct intel_dp *intel_dp = intel_attached_dp(connector);
3202         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3203         struct intel_encoder *intel_encoder = &intel_dig_port->base;
3204         struct drm_device *dev = connector->dev;
3205         struct drm_i915_private *dev_priv = dev->dev_private;
3206         enum drm_connector_status status;
3207         struct edid *edid = NULL;
3208
3209         intel_runtime_pm_get(dev_priv);
3210
3211         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3212                       connector->base.id, drm_get_connector_name(connector));
3213
3214         intel_dp->has_audio = false;
3215
3216         if (HAS_PCH_SPLIT(dev))
3217                 status = ironlake_dp_detect(intel_dp);
3218         else
3219                 status = g4x_dp_detect(intel_dp);
3220
3221         if (status != connector_status_connected)
3222                 goto out;
3223
3224         intel_dp_probe_oui(intel_dp);
3225
3226         if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3227                 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
3228         } else {
3229                 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
3230                 if (edid) {
3231                         intel_dp->has_audio = drm_detect_monitor_audio(edid);
3232                         kfree(edid);
3233                 }
3234         }
3235
3236         if (intel_encoder->type != INTEL_OUTPUT_EDP)
3237                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3238         status = connector_status_connected;
3239
3240 out:
3241         intel_runtime_pm_put(dev_priv);
3242         return status;
3243 }
3244
3245 static int intel_dp_get_modes(struct drm_connector *connector)
3246 {
3247         struct intel_dp *intel_dp = intel_attached_dp(connector);
3248         struct intel_connector *intel_connector = to_intel_connector(connector);
3249         struct drm_device *dev = connector->dev;
3250         int ret;
3251
3252         /* We should parse the EDID data and find out if it has an audio sink
3253          */
3254
3255         ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
3256         if (ret)
3257                 return ret;
3258
3259         /* if eDP has no EDID, fall back to fixed mode */
3260         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
3261                 struct drm_display_mode *mode;
3262                 mode = drm_mode_duplicate(dev,
3263                                           intel_connector->panel.fixed_mode);
3264                 if (mode) {
3265                         drm_mode_probed_add(connector, mode);
3266                         return 1;
3267                 }
3268         }
3269         return 0;
3270 }
3271
3272 static bool
3273 intel_dp_detect_audio(struct drm_connector *connector)
3274 {
3275         struct intel_dp *intel_dp = intel_attached_dp(connector);
3276         struct edid *edid;
3277         bool has_audio = false;
3278
3279         edid = intel_dp_get_edid(connector, &intel_dp->adapter);
3280         if (edid) {
3281                 has_audio = drm_detect_monitor_audio(edid);
3282                 kfree(edid);
3283         }
3284
3285         return has_audio;
3286 }
3287
3288 static int
3289 intel_dp_set_property(struct drm_connector *connector,
3290                       struct drm_property *property,
3291                       uint64_t val)
3292 {
3293         struct drm_i915_private *dev_priv = connector->dev->dev_private;
3294         struct intel_connector *intel_connector = to_intel_connector(connector);
3295         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3296         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3297         int ret;
3298
3299         ret = drm_object_property_set_value(&connector->base, property, val);
3300         if (ret)
3301                 return ret;
3302
3303         if (property == dev_priv->force_audio_property) {
3304                 int i = val;
3305                 bool has_audio;
3306
3307                 if (i == intel_dp->force_audio)
3308                         return 0;
3309
3310                 intel_dp->force_audio = i;
3311
3312                 if (i == HDMI_AUDIO_AUTO)
3313                         has_audio = intel_dp_detect_audio(connector);
3314                 else
3315                         has_audio = (i == HDMI_AUDIO_ON);
3316
3317                 if (has_audio == intel_dp->has_audio)
3318                         return 0;
3319
3320                 intel_dp->has_audio = has_audio;
3321                 goto done;
3322         }
3323
3324         if (property == dev_priv->broadcast_rgb_property) {
3325                 bool old_auto = intel_dp->color_range_auto;
3326                 uint32_t old_range = intel_dp->color_range;
3327
3328                 switch (val) {
3329                 case INTEL_BROADCAST_RGB_AUTO:
3330                         intel_dp->color_range_auto = true;
3331                         break;
3332                 case INTEL_BROADCAST_RGB_FULL:
3333                         intel_dp->color_range_auto = false;
3334                         intel_dp->color_range = 0;
3335                         break;
3336                 case INTEL_BROADCAST_RGB_LIMITED:
3337                         intel_dp->color_range_auto = false;
3338                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
3339                         break;
3340                 default:
3341                         return -EINVAL;
3342                 }
3343
3344                 if (old_auto == intel_dp->color_range_auto &&
3345                     old_range == intel_dp->color_range)
3346                         return 0;
3347
3348                 goto done;
3349         }
3350
3351         if (is_edp(intel_dp) &&
3352             property == connector->dev->mode_config.scaling_mode_property) {
3353                 if (val == DRM_MODE_SCALE_NONE) {
3354                         DRM_DEBUG_KMS("no scaling not supported\n");
3355                         return -EINVAL;
3356                 }
3357
3358                 if (intel_connector->panel.fitting_mode == val) {
3359                         /* the eDP scaling property is not changed */
3360                         return 0;
3361                 }
3362                 intel_connector->panel.fitting_mode = val;
3363
3364                 goto done;
3365         }
3366
3367         return -EINVAL;
3368
3369 done:
3370         if (intel_encoder->base.crtc)
3371                 intel_crtc_restore_mode(intel_encoder->base.crtc);
3372
3373         return 0;
3374 }
3375
3376 static void
3377 intel_dp_connector_destroy(struct drm_connector *connector)
3378 {
3379         struct intel_connector *intel_connector = to_intel_connector(connector);
3380
3381         if (!IS_ERR_OR_NULL(intel_connector->edid))
3382                 kfree(intel_connector->edid);
3383
3384         /* Can't call is_edp() since the encoder may have been destroyed
3385          * already. */
3386         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3387                 intel_panel_fini(&intel_connector->panel);
3388
3389         drm_connector_cleanup(connector);
3390         kfree(connector);
3391 }
3392
3393 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
3394 {
3395         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3396         struct intel_dp *intel_dp = &intel_dig_port->dp;
3397         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3398
3399         i2c_del_adapter(&intel_dp->adapter);
3400         drm_encoder_cleanup(encoder);
3401         if (is_edp(intel_dp)) {
3402                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3403                 mutex_lock(&dev->mode_config.mutex);
3404                 edp_panel_vdd_off_sync(intel_dp);
3405                 mutex_unlock(&dev->mode_config.mutex);
3406         }
3407         kfree(intel_dig_port);
3408 }
3409
3410 static const struct drm_connector_funcs intel_dp_connector_funcs = {
3411         .dpms = intel_connector_dpms,
3412         .detect = intel_dp_detect,
3413         .fill_modes = drm_helper_probe_single_connector_modes,
3414         .set_property = intel_dp_set_property,
3415         .destroy = intel_dp_connector_destroy,
3416 };
3417
3418 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3419         .get_modes = intel_dp_get_modes,
3420         .mode_valid = intel_dp_mode_valid,
3421         .best_encoder = intel_best_encoder,
3422 };
3423
3424 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
3425         .destroy = intel_dp_encoder_destroy,
3426 };
3427
3428 static void
3429 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
3430 {
3431         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3432
3433         intel_dp_check_link_status(intel_dp);
3434 }
3435
3436 /* Return which DP Port should be selected for Transcoder DP control */
3437 int
3438 intel_trans_dp_port_sel(struct drm_crtc *crtc)
3439 {
3440         struct drm_device *dev = crtc->dev;
3441         struct intel_encoder *intel_encoder;
3442         struct intel_dp *intel_dp;
3443
3444         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3445                 intel_dp = enc_to_intel_dp(&intel_encoder->base);
3446
3447                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3448                     intel_encoder->type == INTEL_OUTPUT_EDP)
3449                         return intel_dp->output_reg;
3450         }
3451
3452         return -1;
3453 }
3454
3455 /* check the VBT to see whether the eDP is on DP-D port */
3456 bool intel_dp_is_edp(struct drm_device *dev, enum port port)
3457 {
3458         struct drm_i915_private *dev_priv = dev->dev_private;
3459         union child_device_config *p_child;
3460         int i;
3461         static const short port_mapping[] = {
3462                 [PORT_B] = PORT_IDPB,
3463                 [PORT_C] = PORT_IDPC,
3464                 [PORT_D] = PORT_IDPD,
3465         };
3466
3467         if (port == PORT_A)
3468                 return true;
3469
3470         if (!dev_priv->vbt.child_dev_num)
3471                 return false;
3472
3473         for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3474                 p_child = dev_priv->vbt.child_dev + i;
3475
3476                 if (p_child->common.dvo_port == port_mapping[port] &&
3477                     (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
3478                     (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
3479                         return true;
3480         }
3481         return false;
3482 }
3483
3484 static void
3485 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3486 {
3487         struct intel_connector *intel_connector = to_intel_connector(connector);
3488
3489         intel_attach_force_audio_property(connector);
3490         intel_attach_broadcast_rgb_property(connector);
3491         intel_dp->color_range_auto = true;
3492
3493         if (is_edp(intel_dp)) {
3494                 drm_mode_create_scaling_mode_property(connector->dev);
3495                 drm_object_attach_property(
3496                         &connector->base,
3497                         connector->dev->mode_config.scaling_mode_property,
3498                         DRM_MODE_SCALE_ASPECT);
3499                 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
3500         }
3501 }
3502
3503 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
3504 {
3505         intel_dp->last_power_cycle = jiffies;
3506         intel_dp->last_power_on = jiffies;
3507         intel_dp->last_backlight_off = jiffies;
3508 }
3509
3510 static void
3511 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
3512                                     struct intel_dp *intel_dp,
3513                                     struct edp_power_seq *out)
3514 {
3515         struct drm_i915_private *dev_priv = dev->dev_private;
3516         struct edp_power_seq cur, vbt, spec, final;
3517         u32 pp_on, pp_off, pp_div, pp;
3518         int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
3519
3520         if (HAS_PCH_SPLIT(dev)) {
3521                 pp_ctrl_reg = PCH_PP_CONTROL;
3522                 pp_on_reg = PCH_PP_ON_DELAYS;
3523                 pp_off_reg = PCH_PP_OFF_DELAYS;
3524                 pp_div_reg = PCH_PP_DIVISOR;
3525         } else {
3526                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3527
3528                 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3529                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3530                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3531                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3532         }
3533
3534         /* Workaround: Need to write PP_CONTROL with the unlock key as
3535          * the very first thing. */
3536         pp = ironlake_get_pp_control(intel_dp);
3537         I915_WRITE(pp_ctrl_reg, pp);
3538
3539         pp_on = I915_READ(pp_on_reg);
3540         pp_off = I915_READ(pp_off_reg);
3541         pp_div = I915_READ(pp_div_reg);
3542
3543         /* Pull timing values out of registers */
3544         cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3545                 PANEL_POWER_UP_DELAY_SHIFT;
3546
3547         cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3548                 PANEL_LIGHT_ON_DELAY_SHIFT;
3549
3550         cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3551                 PANEL_LIGHT_OFF_DELAY_SHIFT;
3552
3553         cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3554                 PANEL_POWER_DOWN_DELAY_SHIFT;
3555
3556         cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3557                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3558
3559         DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3560                       cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3561
3562         vbt = dev_priv->vbt.edp_pps;
3563
3564         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3565          * our hw here, which are all in 100usec. */
3566         spec.t1_t3 = 210 * 10;
3567         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3568         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3569         spec.t10 = 500 * 10;
3570         /* This one is special and actually in units of 100ms, but zero
3571          * based in the hw (so we need to add 100 ms). But the sw vbt
3572          * table multiplies it with 1000 to make it in units of 100usec,
3573          * too. */
3574         spec.t11_t12 = (510 + 100) * 10;
3575
3576         DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3577                       vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3578
3579         /* Use the max of the register settings and vbt. If both are
3580          * unset, fall back to the spec limits. */
3581 #define assign_final(field)     final.field = (max(cur.field, vbt.field) == 0 ? \
3582                                        spec.field : \
3583                                        max(cur.field, vbt.field))
3584         assign_final(t1_t3);
3585         assign_final(t8);
3586         assign_final(t9);
3587         assign_final(t10);
3588         assign_final(t11_t12);
3589 #undef assign_final
3590
3591 #define get_delay(field)        (DIV_ROUND_UP(final.field, 10))
3592         intel_dp->panel_power_up_delay = get_delay(t1_t3);
3593         intel_dp->backlight_on_delay = get_delay(t8);
3594         intel_dp->backlight_off_delay = get_delay(t9);
3595         intel_dp->panel_power_down_delay = get_delay(t10);
3596         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3597 #undef get_delay
3598
3599         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3600                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3601                       intel_dp->panel_power_cycle_delay);
3602
3603         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3604                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3605
3606         if (out)
3607                 *out = final;
3608 }
3609
3610 static void
3611 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3612                                               struct intel_dp *intel_dp,
3613                                               struct edp_power_seq *seq)
3614 {
3615         struct drm_i915_private *dev_priv = dev->dev_private;
3616         u32 pp_on, pp_off, pp_div, port_sel = 0;
3617         int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3618         int pp_on_reg, pp_off_reg, pp_div_reg;
3619
3620         if (HAS_PCH_SPLIT(dev)) {
3621                 pp_on_reg = PCH_PP_ON_DELAYS;
3622                 pp_off_reg = PCH_PP_OFF_DELAYS;
3623                 pp_div_reg = PCH_PP_DIVISOR;
3624         } else {
3625                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3626
3627                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3628                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3629                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3630         }
3631
3632         /*
3633          * And finally store the new values in the power sequencer. The
3634          * backlight delays are set to 1 because we do manual waits on them. For
3635          * T8, even BSpec recommends doing it. For T9, if we don't do this,
3636          * we'll end up waiting for the backlight off delay twice: once when we
3637          * do the manual sleep, and once when we disable the panel and wait for
3638          * the PP_STATUS bit to become zero.
3639          */
3640         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
3641                 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
3642         pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
3643                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
3644         /* Compute the divisor for the pp clock, simply match the Bspec
3645          * formula. */
3646         pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
3647         pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
3648                         << PANEL_POWER_CYCLE_DELAY_SHIFT);
3649
3650         /* Haswell doesn't have any port selection bits for the panel
3651          * power sequencer any more. */
3652         if (IS_VALLEYVIEW(dev)) {
3653                 if (dp_to_dig_port(intel_dp)->port == PORT_B)
3654                         port_sel = PANEL_PORT_SELECT_DPB_VLV;
3655                 else
3656                         port_sel = PANEL_PORT_SELECT_DPC_VLV;
3657         } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3658                 if (dp_to_dig_port(intel_dp)->port == PORT_A)
3659                         port_sel = PANEL_PORT_SELECT_DPA;
3660                 else
3661                         port_sel = PANEL_PORT_SELECT_DPD;
3662         }
3663
3664         pp_on |= port_sel;
3665
3666         I915_WRITE(pp_on_reg, pp_on);
3667         I915_WRITE(pp_off_reg, pp_off);
3668         I915_WRITE(pp_div_reg, pp_div);
3669
3670         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
3671                       I915_READ(pp_on_reg),
3672                       I915_READ(pp_off_reg),
3673                       I915_READ(pp_div_reg));
3674 }
3675
3676 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
3677                                      struct intel_connector *intel_connector,
3678                                      struct edp_power_seq *power_seq)
3679 {
3680         struct drm_connector *connector = &intel_connector->base;
3681         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3682         struct drm_device *dev = intel_dig_port->base.base.dev;
3683         struct drm_i915_private *dev_priv = dev->dev_private;
3684         struct drm_display_mode *fixed_mode = NULL;
3685         bool has_dpcd;
3686         struct drm_display_mode *scan;
3687         struct edid *edid;
3688
3689         if (!is_edp(intel_dp))
3690                 return true;
3691
3692         /* Cache DPCD and EDID for edp. */
3693         edp_panel_vdd_on(intel_dp);
3694         has_dpcd = intel_dp_get_dpcd(intel_dp);
3695         edp_panel_vdd_off(intel_dp, false);
3696
3697         if (has_dpcd) {
3698                 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3699                         dev_priv->no_aux_handshake =
3700                                 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3701                                 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3702         } else {
3703                 /* if this fails, presume the device is a ghost */
3704                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3705                 return false;
3706         }
3707
3708         /* We now know it's not a ghost, init power sequence regs. */
3709         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
3710
3711         edid = drm_get_edid(connector, &intel_dp->adapter);
3712         if (edid) {
3713                 if (drm_add_edid_modes(connector, edid)) {
3714                         drm_mode_connector_update_edid_property(connector,
3715                                                                 edid);
3716                         drm_edid_to_eld(connector, edid);
3717                 } else {
3718                         kfree(edid);
3719                         edid = ERR_PTR(-EINVAL);
3720                 }
3721         } else {
3722                 edid = ERR_PTR(-ENOENT);
3723         }
3724         intel_connector->edid = edid;
3725
3726         /* prefer fixed mode from EDID if available */
3727         list_for_each_entry(scan, &connector->probed_modes, head) {
3728                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3729                         fixed_mode = drm_mode_duplicate(dev, scan);
3730                         break;
3731                 }
3732         }
3733
3734         /* fallback to VBT if available for eDP */
3735         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3736                 fixed_mode = drm_mode_duplicate(dev,
3737                                         dev_priv->vbt.lfp_lvds_vbt_mode);
3738                 if (fixed_mode)
3739                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3740         }
3741
3742         intel_panel_init(&intel_connector->panel, fixed_mode);
3743         intel_panel_setup_backlight(connector);
3744
3745         return true;
3746 }
3747
3748 bool
3749 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3750                         struct intel_connector *intel_connector)
3751 {
3752         struct drm_connector *connector = &intel_connector->base;
3753         struct intel_dp *intel_dp = &intel_dig_port->dp;
3754         struct intel_encoder *intel_encoder = &intel_dig_port->base;
3755         struct drm_device *dev = intel_encoder->base.dev;
3756         struct drm_i915_private *dev_priv = dev->dev_private;
3757         enum port port = intel_dig_port->port;
3758         struct edp_power_seq power_seq = { 0 };
3759         const char *name = NULL;
3760         int type, error;
3761
3762         /* intel_dp vfuncs */
3763         if (IS_VALLEYVIEW(dev))
3764                 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
3765         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3766                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
3767         else if (HAS_PCH_SPLIT(dev))
3768                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
3769         else
3770                 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
3771
3772         intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
3773
3774         /* Preserve the current hw state. */
3775         intel_dp->DP = I915_READ(intel_dp->output_reg);
3776         intel_dp->attached_connector = intel_connector;
3777
3778         if (intel_dp_is_edp(dev, port))
3779                 type = DRM_MODE_CONNECTOR_eDP;
3780         else
3781                 type = DRM_MODE_CONNECTOR_DisplayPort;
3782
3783         /*
3784          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3785          * for DP the encoder type can be set by the caller to
3786          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3787          */
3788         if (type == DRM_MODE_CONNECTOR_eDP)
3789                 intel_encoder->type = INTEL_OUTPUT_EDP;
3790
3791         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3792                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3793                         port_name(port));
3794
3795         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
3796         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3797
3798         connector->interlace_allowed = true;
3799         connector->doublescan_allowed = 0;
3800
3801         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3802                           edp_panel_vdd_work);
3803
3804         intel_connector_attach_encoder(intel_connector, intel_encoder);
3805         drm_sysfs_connector_add(connector);
3806
3807         if (HAS_DDI(dev))
3808                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3809         else
3810                 intel_connector->get_hw_state = intel_connector_get_hw_state;
3811
3812         intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3813         if (HAS_DDI(dev)) {
3814                 switch (intel_dig_port->port) {
3815                 case PORT_A:
3816                         intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3817                         break;
3818                 case PORT_B:
3819                         intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3820                         break;
3821                 case PORT_C:
3822                         intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3823                         break;
3824                 case PORT_D:
3825                         intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3826                         break;
3827                 default:
3828                         BUG();
3829                 }
3830         }
3831
3832         /* Set up the DDC bus. */
3833         switch (port) {
3834         case PORT_A:
3835                 intel_encoder->hpd_pin = HPD_PORT_A;
3836                 name = "DPDDC-A";
3837                 break;
3838         case PORT_B:
3839                 intel_encoder->hpd_pin = HPD_PORT_B;
3840                 name = "DPDDC-B";
3841                 break;
3842         case PORT_C:
3843                 intel_encoder->hpd_pin = HPD_PORT_C;
3844                 name = "DPDDC-C";
3845                 break;
3846         case PORT_D:
3847                 intel_encoder->hpd_pin = HPD_PORT_D;
3848                 name = "DPDDC-D";
3849                 break;
3850         default:
3851                 BUG();
3852         }
3853
3854         if (is_edp(intel_dp)) {
3855                 intel_dp_init_panel_power_timestamps(intel_dp);
3856                 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
3857         }
3858
3859         error = intel_dp_i2c_init(intel_dp, intel_connector, name);
3860         WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n",
3861              error, port_name(port));
3862
3863         intel_dp->psr_setup_done = false;
3864
3865         if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
3866                 i2c_del_adapter(&intel_dp->adapter);
3867                 if (is_edp(intel_dp)) {
3868                         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3869                         mutex_lock(&dev->mode_config.mutex);
3870                         edp_panel_vdd_off_sync(intel_dp);
3871                         mutex_unlock(&dev->mode_config.mutex);
3872                 }
3873                 drm_sysfs_connector_remove(connector);
3874                 drm_connector_cleanup(connector);
3875                 return false;
3876         }
3877
3878         intel_dp_add_properties(intel_dp, connector);
3879
3880         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3881          * 0xd.  Failure to do so will result in spurious interrupts being
3882          * generated on the port when a cable is not attached.
3883          */
3884         if (IS_G4X(dev) && !IS_GM45(dev)) {
3885                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3886                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3887         }
3888
3889         return true;
3890 }
3891
3892 void
3893 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3894 {
3895         struct intel_digital_port *intel_dig_port;
3896         struct intel_encoder *intel_encoder;
3897         struct drm_encoder *encoder;
3898         struct intel_connector *intel_connector;
3899
3900         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
3901         if (!intel_dig_port)
3902                 return;
3903
3904         intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
3905         if (!intel_connector) {
3906                 kfree(intel_dig_port);
3907                 return;
3908         }
3909
3910         intel_encoder = &intel_dig_port->base;
3911         encoder = &intel_encoder->base;
3912
3913         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3914                          DRM_MODE_ENCODER_TMDS);
3915
3916         intel_encoder->compute_config = intel_dp_compute_config;
3917         intel_encoder->mode_set = intel_dp_mode_set;
3918         intel_encoder->disable = intel_disable_dp;
3919         intel_encoder->post_disable = intel_post_disable_dp;
3920         intel_encoder->get_hw_state = intel_dp_get_hw_state;
3921         intel_encoder->get_config = intel_dp_get_config;
3922         if (IS_VALLEYVIEW(dev)) {
3923                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
3924                 intel_encoder->pre_enable = vlv_pre_enable_dp;
3925                 intel_encoder->enable = vlv_enable_dp;
3926         } else {
3927                 intel_encoder->pre_enable = g4x_pre_enable_dp;
3928                 intel_encoder->enable = g4x_enable_dp;
3929         }
3930
3931         intel_dig_port->port = port;
3932         intel_dig_port->dp.output_reg = output_reg;
3933
3934         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3935         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3936         intel_encoder->cloneable = false;
3937         intel_encoder->hot_plug = intel_dp_hot_plug;
3938
3939         if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
3940                 drm_encoder_cleanup(encoder);
3941                 kfree(intel_dig_port);
3942                 kfree(intel_connector);
3943         }
3944 }