2 * Derived from "arch/i386/kernel/process.c"
3 * Copyright (C) 1995 Linus Torvalds
5 * Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
6 * Paul Mackerras (paulus@cs.anu.edu.au)
9 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
17 #include <linux/errno.h>
18 #include <linux/sched.h>
19 #include <linux/sched/debug.h>
20 #include <linux/sched/task.h>
21 #include <linux/sched/task_stack.h>
22 #include <linux/kernel.h>
24 #include <linux/smp.h>
25 #include <linux/stddef.h>
26 #include <linux/unistd.h>
27 #include <linux/ptrace.h>
28 #include <linux/slab.h>
29 #include <linux/user.h>
30 #include <linux/elf.h>
31 #include <linux/prctl.h>
32 #include <linux/init_task.h>
33 #include <linux/export.h>
34 #include <linux/kallsyms.h>
35 #include <linux/mqueue.h>
36 #include <linux/hardirq.h>
37 #include <linux/utsname.h>
38 #include <linux/ftrace.h>
39 #include <linux/kernel_stat.h>
40 #include <linux/personality.h>
41 #include <linux/random.h>
42 #include <linux/hw_breakpoint.h>
43 #include <linux/uaccess.h>
44 #include <linux/elf-randomize.h>
46 #include <asm/pgtable.h>
48 #include <asm/processor.h>
51 #include <asm/machdep.h>
53 #include <asm/runlatch.h>
54 #include <asm/syscalls.h>
55 #include <asm/switch_to.h>
57 #include <asm/debug.h>
59 #include <asm/firmware.h>
61 #include <asm/code-patching.h>
63 #include <asm/livepatch.h>
64 #include <asm/cpu_has_feature.h>
65 #include <asm/asm-prototypes.h>
67 #include <linux/kprobes.h>
68 #include <linux/kdebug.h>
70 /* Transactional Memory debug */
72 #define TM_DEBUG(x...) printk(KERN_INFO x)
74 #define TM_DEBUG(x...) do { } while(0)
77 extern unsigned long _get_SP(void);
79 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
80 static void check_if_tm_restore_required(struct task_struct *tsk)
83 * If we are saving the current thread's registers, and the
84 * thread is in a transactional state, set the TIF_RESTORE_TM
85 * bit so that we know to restore the registers before
86 * returning to userspace.
88 if (tsk == current && tsk->thread.regs &&
89 MSR_TM_ACTIVE(tsk->thread.regs->msr) &&
90 !test_thread_flag(TIF_RESTORE_TM)) {
91 tsk->thread.ckpt_regs.msr = tsk->thread.regs->msr;
92 set_thread_flag(TIF_RESTORE_TM);
96 static inline bool msr_tm_active(unsigned long msr)
98 return MSR_TM_ACTIVE(msr);
101 static inline bool msr_tm_active(unsigned long msr) { return false; }
102 static inline void check_if_tm_restore_required(struct task_struct *tsk) { }
103 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
105 bool strict_msr_control;
106 EXPORT_SYMBOL(strict_msr_control);
108 static int __init enable_strict_msr_control(char *str)
110 strict_msr_control = true;
111 pr_info("Enabling strict facility control\n");
115 early_param("ppc_strict_facility_enable", enable_strict_msr_control);
117 unsigned long msr_check_and_set(unsigned long bits)
119 unsigned long oldmsr = mfmsr();
120 unsigned long newmsr;
122 newmsr = oldmsr | bits;
125 if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP))
129 if (oldmsr != newmsr)
135 void __msr_check_and_clear(unsigned long bits)
137 unsigned long oldmsr = mfmsr();
138 unsigned long newmsr;
140 newmsr = oldmsr & ~bits;
143 if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP))
147 if (oldmsr != newmsr)
150 EXPORT_SYMBOL(__msr_check_and_clear);
152 #ifdef CONFIG_PPC_FPU
153 void __giveup_fpu(struct task_struct *tsk)
158 msr = tsk->thread.regs->msr;
161 if (cpu_has_feature(CPU_FTR_VSX))
164 tsk->thread.regs->msr = msr;
167 void giveup_fpu(struct task_struct *tsk)
169 check_if_tm_restore_required(tsk);
171 msr_check_and_set(MSR_FP);
173 msr_check_and_clear(MSR_FP);
175 EXPORT_SYMBOL(giveup_fpu);
178 * Make sure the floating-point register state in the
179 * the thread_struct is up to date for task tsk.
181 void flush_fp_to_thread(struct task_struct *tsk)
183 if (tsk->thread.regs) {
185 * We need to disable preemption here because if we didn't,
186 * another process could get scheduled after the regs->msr
187 * test but before we have finished saving the FP registers
188 * to the thread_struct. That process could take over the
189 * FPU, and then when we get scheduled again we would store
190 * bogus values for the remaining FP registers.
193 if (tsk->thread.regs->msr & MSR_FP) {
195 * This should only ever be called for current or
196 * for a stopped child process. Since we save away
197 * the FP register state on context switch,
198 * there is something wrong if a stopped child appears
199 * to still have its FP state in the CPU registers.
201 BUG_ON(tsk != current);
207 EXPORT_SYMBOL_GPL(flush_fp_to_thread);
209 void enable_kernel_fp(void)
211 unsigned long cpumsr;
213 WARN_ON(preemptible());
215 cpumsr = msr_check_and_set(MSR_FP);
217 if (current->thread.regs && (current->thread.regs->msr & MSR_FP)) {
218 check_if_tm_restore_required(current);
220 * If a thread has already been reclaimed then the
221 * checkpointed registers are on the CPU but have definitely
222 * been saved by the reclaim code. Don't need to and *cannot*
223 * giveup as this would save to the 'live' structure not the
224 * checkpointed structure.
226 if(!msr_tm_active(cpumsr) && msr_tm_active(current->thread.regs->msr))
228 __giveup_fpu(current);
231 EXPORT_SYMBOL(enable_kernel_fp);
233 static int restore_fp(struct task_struct *tsk) {
234 if (tsk->thread.load_fp || msr_tm_active(tsk->thread.regs->msr)) {
235 load_fp_state(¤t->thread.fp_state);
236 current->thread.load_fp++;
242 static int restore_fp(struct task_struct *tsk) { return 0; }
243 #endif /* CONFIG_PPC_FPU */
245 #ifdef CONFIG_ALTIVEC
246 #define loadvec(thr) ((thr).load_vec)
248 static void __giveup_altivec(struct task_struct *tsk)
253 msr = tsk->thread.regs->msr;
256 if (cpu_has_feature(CPU_FTR_VSX))
259 tsk->thread.regs->msr = msr;
262 void giveup_altivec(struct task_struct *tsk)
264 check_if_tm_restore_required(tsk);
266 msr_check_and_set(MSR_VEC);
267 __giveup_altivec(tsk);
268 msr_check_and_clear(MSR_VEC);
270 EXPORT_SYMBOL(giveup_altivec);
272 void enable_kernel_altivec(void)
274 unsigned long cpumsr;
276 WARN_ON(preemptible());
278 cpumsr = msr_check_and_set(MSR_VEC);
280 if (current->thread.regs && (current->thread.regs->msr & MSR_VEC)) {
281 check_if_tm_restore_required(current);
283 * If a thread has already been reclaimed then the
284 * checkpointed registers are on the CPU but have definitely
285 * been saved by the reclaim code. Don't need to and *cannot*
286 * giveup as this would save to the 'live' structure not the
287 * checkpointed structure.
289 if(!msr_tm_active(cpumsr) && msr_tm_active(current->thread.regs->msr))
291 __giveup_altivec(current);
294 EXPORT_SYMBOL(enable_kernel_altivec);
297 * Make sure the VMX/Altivec register state in the
298 * the thread_struct is up to date for task tsk.
300 void flush_altivec_to_thread(struct task_struct *tsk)
302 if (tsk->thread.regs) {
304 if (tsk->thread.regs->msr & MSR_VEC) {
305 BUG_ON(tsk != current);
311 EXPORT_SYMBOL_GPL(flush_altivec_to_thread);
313 static int restore_altivec(struct task_struct *tsk)
315 if (cpu_has_feature(CPU_FTR_ALTIVEC) &&
316 (tsk->thread.load_vec || msr_tm_active(tsk->thread.regs->msr))) {
317 load_vr_state(&tsk->thread.vr_state);
318 tsk->thread.used_vr = 1;
319 tsk->thread.load_vec++;
326 #define loadvec(thr) 0
327 static inline int restore_altivec(struct task_struct *tsk) { return 0; }
328 #endif /* CONFIG_ALTIVEC */
331 static void __giveup_vsx(struct task_struct *tsk)
333 if (tsk->thread.regs->msr & MSR_FP)
335 if (tsk->thread.regs->msr & MSR_VEC)
336 __giveup_altivec(tsk);
337 tsk->thread.regs->msr &= ~MSR_VSX;
340 static void giveup_vsx(struct task_struct *tsk)
342 check_if_tm_restore_required(tsk);
344 msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX);
346 msr_check_and_clear(MSR_FP|MSR_VEC|MSR_VSX);
349 static void save_vsx(struct task_struct *tsk)
351 if (tsk->thread.regs->msr & MSR_FP)
353 if (tsk->thread.regs->msr & MSR_VEC)
357 void enable_kernel_vsx(void)
359 unsigned long cpumsr;
361 WARN_ON(preemptible());
363 cpumsr = msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX);
365 if (current->thread.regs && (current->thread.regs->msr & MSR_VSX)) {
366 check_if_tm_restore_required(current);
368 * If a thread has already been reclaimed then the
369 * checkpointed registers are on the CPU but have definitely
370 * been saved by the reclaim code. Don't need to and *cannot*
371 * giveup as this would save to the 'live' structure not the
372 * checkpointed structure.
374 if(!msr_tm_active(cpumsr) && msr_tm_active(current->thread.regs->msr))
376 if (current->thread.regs->msr & MSR_FP)
377 __giveup_fpu(current);
378 if (current->thread.regs->msr & MSR_VEC)
379 __giveup_altivec(current);
380 __giveup_vsx(current);
383 EXPORT_SYMBOL(enable_kernel_vsx);
385 void flush_vsx_to_thread(struct task_struct *tsk)
387 if (tsk->thread.regs) {
389 if (tsk->thread.regs->msr & MSR_VSX) {
390 BUG_ON(tsk != current);
396 EXPORT_SYMBOL_GPL(flush_vsx_to_thread);
398 static int restore_vsx(struct task_struct *tsk)
400 if (cpu_has_feature(CPU_FTR_VSX)) {
401 tsk->thread.used_vsr = 1;
408 static inline int restore_vsx(struct task_struct *tsk) { return 0; }
409 static inline void save_vsx(struct task_struct *tsk) { }
410 #endif /* CONFIG_VSX */
413 void giveup_spe(struct task_struct *tsk)
415 check_if_tm_restore_required(tsk);
417 msr_check_and_set(MSR_SPE);
419 msr_check_and_clear(MSR_SPE);
421 EXPORT_SYMBOL(giveup_spe);
423 void enable_kernel_spe(void)
425 WARN_ON(preemptible());
427 msr_check_and_set(MSR_SPE);
429 if (current->thread.regs && (current->thread.regs->msr & MSR_SPE)) {
430 check_if_tm_restore_required(current);
431 __giveup_spe(current);
434 EXPORT_SYMBOL(enable_kernel_spe);
436 void flush_spe_to_thread(struct task_struct *tsk)
438 if (tsk->thread.regs) {
440 if (tsk->thread.regs->msr & MSR_SPE) {
441 BUG_ON(tsk != current);
442 tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
448 #endif /* CONFIG_SPE */
450 static unsigned long msr_all_available;
452 static int __init init_msr_all_available(void)
454 #ifdef CONFIG_PPC_FPU
455 msr_all_available |= MSR_FP;
457 #ifdef CONFIG_ALTIVEC
458 if (cpu_has_feature(CPU_FTR_ALTIVEC))
459 msr_all_available |= MSR_VEC;
462 if (cpu_has_feature(CPU_FTR_VSX))
463 msr_all_available |= MSR_VSX;
466 if (cpu_has_feature(CPU_FTR_SPE))
467 msr_all_available |= MSR_SPE;
472 early_initcall(init_msr_all_available);
474 void giveup_all(struct task_struct *tsk)
476 unsigned long usermsr;
478 if (!tsk->thread.regs)
481 usermsr = tsk->thread.regs->msr;
483 if ((usermsr & msr_all_available) == 0)
486 msr_check_and_set(msr_all_available);
487 check_if_tm_restore_required(tsk);
489 #ifdef CONFIG_PPC_FPU
490 if (usermsr & MSR_FP)
493 #ifdef CONFIG_ALTIVEC
494 if (usermsr & MSR_VEC)
495 __giveup_altivec(tsk);
498 if (usermsr & MSR_VSX)
502 if (usermsr & MSR_SPE)
506 msr_check_and_clear(msr_all_available);
508 EXPORT_SYMBOL(giveup_all);
510 void restore_math(struct pt_regs *regs)
515 * Syscall exit makes a similar initial check before branching
516 * to restore_math. Keep them in synch.
518 if (!msr_tm_active(regs->msr) &&
519 !current->thread.load_fp && !loadvec(current->thread))
523 msr_check_and_set(msr_all_available);
526 * Only reload if the bit is not set in the user MSR, the bit BEING set
527 * indicates that the registers are hot
529 if ((!(msr & MSR_FP)) && restore_fp(current))
530 msr |= MSR_FP | current->thread.fpexc_mode;
532 if ((!(msr & MSR_VEC)) && restore_altivec(current))
535 if ((msr & (MSR_FP | MSR_VEC)) == (MSR_FP | MSR_VEC) &&
536 restore_vsx(current)) {
540 msr_check_and_clear(msr_all_available);
545 void save_all(struct task_struct *tsk)
547 unsigned long usermsr;
549 if (!tsk->thread.regs)
552 usermsr = tsk->thread.regs->msr;
554 if ((usermsr & msr_all_available) == 0)
557 msr_check_and_set(msr_all_available);
560 * Saving the way the register space is in hardware, save_vsx boils
561 * down to a save_fpu() and save_altivec()
563 if (usermsr & MSR_VSX) {
566 if (usermsr & MSR_FP)
569 if (usermsr & MSR_VEC)
573 if (usermsr & MSR_SPE)
576 msr_check_and_clear(msr_all_available);
579 void flush_all_to_thread(struct task_struct *tsk)
581 if (tsk->thread.regs) {
583 BUG_ON(tsk != current);
587 if (tsk->thread.regs->msr & MSR_SPE)
588 tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
594 EXPORT_SYMBOL(flush_all_to_thread);
596 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
597 void do_send_trap(struct pt_regs *regs, unsigned long address,
598 unsigned long error_code, int signal_code, int breakpt)
602 current->thread.trap_nr = signal_code;
603 if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
604 11, SIGSEGV) == NOTIFY_STOP)
607 /* Deliver the signal to userspace */
608 info.si_signo = SIGTRAP;
609 info.si_errno = breakpt; /* breakpoint or watchpoint id */
610 info.si_code = signal_code;
611 info.si_addr = (void __user *)address;
612 force_sig_info(SIGTRAP, &info, current);
614 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
615 void do_break (struct pt_regs *regs, unsigned long address,
616 unsigned long error_code)
620 current->thread.trap_nr = TRAP_HWBKPT;
621 if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
622 11, SIGSEGV) == NOTIFY_STOP)
625 if (debugger_break_match(regs))
628 /* Clear the breakpoint */
629 hw_breakpoint_disable();
631 /* Deliver the signal to userspace */
632 info.si_signo = SIGTRAP;
634 info.si_code = TRAP_HWBKPT;
635 info.si_addr = (void __user *)address;
636 force_sig_info(SIGTRAP, &info, current);
638 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
640 static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk);
642 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
644 * Set the debug registers back to their default "safe" values.
646 static void set_debug_reg_defaults(struct thread_struct *thread)
648 thread->debug.iac1 = thread->debug.iac2 = 0;
649 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
650 thread->debug.iac3 = thread->debug.iac4 = 0;
652 thread->debug.dac1 = thread->debug.dac2 = 0;
653 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
654 thread->debug.dvc1 = thread->debug.dvc2 = 0;
656 thread->debug.dbcr0 = 0;
659 * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
661 thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US |
662 DBCR1_IAC3US | DBCR1_IAC4US;
664 * Force Data Address Compare User/Supervisor bits to be User-only
665 * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
667 thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
669 thread->debug.dbcr1 = 0;
673 static void prime_debug_regs(struct debug_reg *debug)
676 * We could have inherited MSR_DE from userspace, since
677 * it doesn't get cleared on exception entry. Make sure
678 * MSR_DE is clear before we enable any debug events.
680 mtmsr(mfmsr() & ~MSR_DE);
682 mtspr(SPRN_IAC1, debug->iac1);
683 mtspr(SPRN_IAC2, debug->iac2);
684 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
685 mtspr(SPRN_IAC3, debug->iac3);
686 mtspr(SPRN_IAC4, debug->iac4);
688 mtspr(SPRN_DAC1, debug->dac1);
689 mtspr(SPRN_DAC2, debug->dac2);
690 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
691 mtspr(SPRN_DVC1, debug->dvc1);
692 mtspr(SPRN_DVC2, debug->dvc2);
694 mtspr(SPRN_DBCR0, debug->dbcr0);
695 mtspr(SPRN_DBCR1, debug->dbcr1);
697 mtspr(SPRN_DBCR2, debug->dbcr2);
701 * Unless neither the old or new thread are making use of the
702 * debug registers, set the debug registers from the values
703 * stored in the new thread.
705 void switch_booke_debug_regs(struct debug_reg *new_debug)
707 if ((current->thread.debug.dbcr0 & DBCR0_IDM)
708 || (new_debug->dbcr0 & DBCR0_IDM))
709 prime_debug_regs(new_debug);
711 EXPORT_SYMBOL_GPL(switch_booke_debug_regs);
712 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
713 #ifndef CONFIG_HAVE_HW_BREAKPOINT
714 static void set_debug_reg_defaults(struct thread_struct *thread)
716 thread->hw_brk.address = 0;
717 thread->hw_brk.type = 0;
718 set_breakpoint(&thread->hw_brk);
720 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */
721 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
723 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
724 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
726 mtspr(SPRN_DAC1, dabr);
727 #ifdef CONFIG_PPC_47x
732 #elif defined(CONFIG_PPC_BOOK3S)
733 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
735 mtspr(SPRN_DABR, dabr);
736 if (cpu_has_feature(CPU_FTR_DABRX))
737 mtspr(SPRN_DABRX, dabrx);
740 #elif defined(CONFIG_PPC_8xx)
741 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
743 unsigned long addr = dabr & ~HW_BRK_TYPE_DABR;
744 unsigned long lctrl1 = 0x90000000; /* compare type: equal on E & F */
745 unsigned long lctrl2 = 0x8e000002; /* watchpoint 1 on cmp E | F */
747 if ((dabr & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_READ)
749 else if ((dabr & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_WRITE)
751 else if ((dabr & HW_BRK_TYPE_RDWR) == 0)
754 mtspr(SPRN_LCTRL2, 0);
755 mtspr(SPRN_CMPE, addr);
756 mtspr(SPRN_CMPF, addr + 4);
757 mtspr(SPRN_LCTRL1, lctrl1);
758 mtspr(SPRN_LCTRL2, lctrl2);
763 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
769 static inline int set_dabr(struct arch_hw_breakpoint *brk)
771 unsigned long dabr, dabrx;
773 dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR);
774 dabrx = ((brk->type >> 3) & 0x7);
777 return ppc_md.set_dabr(dabr, dabrx);
779 return __set_dabr(dabr, dabrx);
782 static inline int set_dawr(struct arch_hw_breakpoint *brk)
784 unsigned long dawr, dawrx, mrd;
788 dawrx = (brk->type & (HW_BRK_TYPE_READ | HW_BRK_TYPE_WRITE)) \
789 << (63 - 58); //* read/write bits */
790 dawrx |= ((brk->type & (HW_BRK_TYPE_TRANSLATE)) >> 2) \
791 << (63 - 59); //* translate */
792 dawrx |= (brk->type & (HW_BRK_TYPE_PRIV_ALL)) \
793 >> 3; //* PRIM bits */
794 /* dawr length is stored in field MDR bits 48:53. Matches range in
795 doublewords (64 bits) baised by -1 eg. 0b000000=1DW and
797 brk->len is in bytes.
798 This aligns up to double word size, shifts and does the bias.
800 mrd = ((brk->len + 7) >> 3) - 1;
801 dawrx |= (mrd & 0x3f) << (63 - 53);
804 return ppc_md.set_dawr(dawr, dawrx);
805 mtspr(SPRN_DAWR, dawr);
806 mtspr(SPRN_DAWRX, dawrx);
810 void __set_breakpoint(struct arch_hw_breakpoint *brk)
812 memcpy(this_cpu_ptr(¤t_brk), brk, sizeof(*brk));
814 if (cpu_has_feature(CPU_FTR_DAWR))
820 void set_breakpoint(struct arch_hw_breakpoint *brk)
823 __set_breakpoint(brk);
828 DEFINE_PER_CPU(struct cpu_usage, cpu_usage_array);
831 static inline bool hw_brk_match(struct arch_hw_breakpoint *a,
832 struct arch_hw_breakpoint *b)
834 if (a->address != b->address)
836 if (a->type != b->type)
838 if (a->len != b->len)
843 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
845 static inline bool tm_enabled(struct task_struct *tsk)
847 return tsk && tsk->thread.regs && (tsk->thread.regs->msr & MSR_TM);
850 static void tm_reclaim_thread(struct thread_struct *thr,
851 struct thread_info *ti, uint8_t cause)
854 * Use the current MSR TM suspended bit to track if we have
855 * checkpointed state outstanding.
856 * On signal delivery, we'd normally reclaim the checkpointed
857 * state to obtain stack pointer (see:get_tm_stackpointer()).
858 * This will then directly return to userspace without going
859 * through __switch_to(). However, if the stack frame is bad,
860 * we need to exit this thread which calls __switch_to() which
861 * will again attempt to reclaim the already saved tm state.
862 * Hence we need to check that we've not already reclaimed
864 * We do this using the current MSR, rather tracking it in
865 * some specific thread_struct bit, as it has the additional
866 * benefit of checking for a potential TM bad thing exception.
868 if (!MSR_TM_SUSPENDED(mfmsr()))
872 * If we are in a transaction and FP is off then we can't have
873 * used FP inside that transaction. Hence the checkpointed
874 * state is the same as the live state. We need to copy the
875 * live state to the checkpointed state so that when the
876 * transaction is restored, the checkpointed state is correct
877 * and the aborted transaction sees the correct state. We use
878 * ckpt_regs.msr here as that's what tm_reclaim will use to
879 * determine if it's going to write the checkpointed state or
880 * not. So either this will write the checkpointed registers,
881 * or reclaim will. Similarly for VMX.
883 if ((thr->ckpt_regs.msr & MSR_FP) == 0)
884 memcpy(&thr->ckfp_state, &thr->fp_state,
885 sizeof(struct thread_fp_state));
886 if ((thr->ckpt_regs.msr & MSR_VEC) == 0)
887 memcpy(&thr->ckvr_state, &thr->vr_state,
888 sizeof(struct thread_vr_state));
890 giveup_all(container_of(thr, struct task_struct, thread));
892 tm_reclaim(thr, thr->ckpt_regs.msr, cause);
895 void tm_reclaim_current(uint8_t cause)
898 tm_reclaim_thread(¤t->thread, current_thread_info(), cause);
901 static inline void tm_reclaim_task(struct task_struct *tsk)
903 /* We have to work out if we're switching from/to a task that's in the
904 * middle of a transaction.
906 * In switching we need to maintain a 2nd register state as
907 * oldtask->thread.ckpt_regs. We tm_reclaim(oldproc); this saves the
908 * checkpointed (tbegin) state in ckpt_regs, ckfp_state and
911 * We also context switch (save) TFHAR/TEXASR/TFIAR in here.
913 struct thread_struct *thr = &tsk->thread;
918 if (!MSR_TM_ACTIVE(thr->regs->msr))
919 goto out_and_saveregs;
921 TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, "
922 "ccr=%lx, msr=%lx, trap=%lx)\n",
923 tsk->pid, thr->regs->nip,
924 thr->regs->ccr, thr->regs->msr,
927 tm_reclaim_thread(thr, task_thread_info(tsk), TM_CAUSE_RESCHED);
929 TM_DEBUG("--- tm_reclaim on pid %d complete\n",
933 /* Always save the regs here, even if a transaction's not active.
934 * This context-switches a thread's TM info SPRs. We do it here to
935 * be consistent with the restore path (in recheckpoint) which
936 * cannot happen later in _switch().
941 extern void __tm_recheckpoint(struct thread_struct *thread,
942 unsigned long orig_msr);
944 void tm_recheckpoint(struct thread_struct *thread,
945 unsigned long orig_msr)
949 if (!(thread->regs->msr & MSR_TM))
952 /* We really can't be interrupted here as the TEXASR registers can't
953 * change and later in the trecheckpoint code, we have a userspace R1.
954 * So let's hard disable over this region.
956 local_irq_save(flags);
959 /* The TM SPRs are restored here, so that TEXASR.FS can be set
960 * before the trecheckpoint and no explosion occurs.
962 tm_restore_sprs(thread);
964 __tm_recheckpoint(thread, orig_msr);
966 local_irq_restore(flags);
969 static inline void tm_recheckpoint_new_task(struct task_struct *new)
973 if (!cpu_has_feature(CPU_FTR_TM))
976 /* Recheckpoint the registers of the thread we're about to switch to.
978 * If the task was using FP, we non-lazily reload both the original and
979 * the speculative FP register states. This is because the kernel
980 * doesn't see if/when a TM rollback occurs, so if we take an FP
981 * unavailable later, we are unable to determine which set of FP regs
982 * need to be restored.
984 if (!tm_enabled(new))
987 if (!MSR_TM_ACTIVE(new->thread.regs->msr)){
988 tm_restore_sprs(&new->thread);
991 msr = new->thread.ckpt_regs.msr;
992 /* Recheckpoint to restore original checkpointed register state. */
993 TM_DEBUG("*** tm_recheckpoint of pid %d "
994 "(new->msr 0x%lx, new->origmsr 0x%lx)\n",
995 new->pid, new->thread.regs->msr, msr);
997 tm_recheckpoint(&new->thread, msr);
1000 * The checkpointed state has been restored but the live state has
1001 * not, ensure all the math functionality is turned off to trigger
1002 * restore_math() to reload.
1004 new->thread.regs->msr &= ~(MSR_FP | MSR_VEC | MSR_VSX);
1006 TM_DEBUG("*** tm_recheckpoint of pid %d complete "
1007 "(kernel msr 0x%lx)\n",
1011 static inline void __switch_to_tm(struct task_struct *prev,
1012 struct task_struct *new)
1014 if (cpu_has_feature(CPU_FTR_TM)) {
1015 if (tm_enabled(prev) || tm_enabled(new))
1018 if (tm_enabled(prev)) {
1019 prev->thread.load_tm++;
1020 tm_reclaim_task(prev);
1021 if (!MSR_TM_ACTIVE(prev->thread.regs->msr) && prev->thread.load_tm == 0)
1022 prev->thread.regs->msr &= ~MSR_TM;
1025 tm_recheckpoint_new_task(new);
1030 * This is called if we are on the way out to userspace and the
1031 * TIF_RESTORE_TM flag is set. It checks if we need to reload
1032 * FP and/or vector state and does so if necessary.
1033 * If userspace is inside a transaction (whether active or
1034 * suspended) and FP/VMX/VSX instructions have ever been enabled
1035 * inside that transaction, then we have to keep them enabled
1036 * and keep the FP/VMX/VSX state loaded while ever the transaction
1037 * continues. The reason is that if we didn't, and subsequently
1038 * got a FP/VMX/VSX unavailable interrupt inside a transaction,
1039 * we don't know whether it's the same transaction, and thus we
1040 * don't know which of the checkpointed state and the transactional
1043 void restore_tm_state(struct pt_regs *regs)
1045 unsigned long msr_diff;
1048 * This is the only moment we should clear TIF_RESTORE_TM as
1049 * it is here that ckpt_regs.msr and pt_regs.msr become the same
1050 * again, anything else could lead to an incorrect ckpt_msr being
1051 * saved and therefore incorrect signal contexts.
1053 clear_thread_flag(TIF_RESTORE_TM);
1054 if (!MSR_TM_ACTIVE(regs->msr))
1057 msr_diff = current->thread.ckpt_regs.msr & ~regs->msr;
1058 msr_diff &= MSR_FP | MSR_VEC | MSR_VSX;
1060 /* Ensure that restore_math() will restore */
1061 if (msr_diff & MSR_FP)
1062 current->thread.load_fp = 1;
1063 #ifdef CONFIG_ALTIVEC
1064 if (cpu_has_feature(CPU_FTR_ALTIVEC) && msr_diff & MSR_VEC)
1065 current->thread.load_vec = 1;
1069 regs->msr |= msr_diff;
1073 #define tm_recheckpoint_new_task(new)
1074 #define __switch_to_tm(prev, new)
1075 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1077 static inline void save_sprs(struct thread_struct *t)
1079 #ifdef CONFIG_ALTIVEC
1080 if (cpu_has_feature(CPU_FTR_ALTIVEC))
1081 t->vrsave = mfspr(SPRN_VRSAVE);
1083 #ifdef CONFIG_PPC_BOOK3S_64
1084 if (cpu_has_feature(CPU_FTR_DSCR))
1085 t->dscr = mfspr(SPRN_DSCR);
1087 if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
1088 t->bescr = mfspr(SPRN_BESCR);
1089 t->ebbhr = mfspr(SPRN_EBBHR);
1090 t->ebbrr = mfspr(SPRN_EBBRR);
1092 t->fscr = mfspr(SPRN_FSCR);
1095 * Note that the TAR is not available for use in the kernel.
1096 * (To provide this, the TAR should be backed up/restored on
1097 * exception entry/exit instead, and be in pt_regs. FIXME,
1098 * this should be in pt_regs anyway (for debug).)
1100 t->tar = mfspr(SPRN_TAR);
1105 static inline void restore_sprs(struct thread_struct *old_thread,
1106 struct thread_struct *new_thread)
1108 #ifdef CONFIG_ALTIVEC
1109 if (cpu_has_feature(CPU_FTR_ALTIVEC) &&
1110 old_thread->vrsave != new_thread->vrsave)
1111 mtspr(SPRN_VRSAVE, new_thread->vrsave);
1113 #ifdef CONFIG_PPC_BOOK3S_64
1114 if (cpu_has_feature(CPU_FTR_DSCR)) {
1115 u64 dscr = get_paca()->dscr_default;
1116 if (new_thread->dscr_inherit)
1117 dscr = new_thread->dscr;
1119 if (old_thread->dscr != dscr)
1120 mtspr(SPRN_DSCR, dscr);
1123 if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
1124 if (old_thread->bescr != new_thread->bescr)
1125 mtspr(SPRN_BESCR, new_thread->bescr);
1126 if (old_thread->ebbhr != new_thread->ebbhr)
1127 mtspr(SPRN_EBBHR, new_thread->ebbhr);
1128 if (old_thread->ebbrr != new_thread->ebbrr)
1129 mtspr(SPRN_EBBRR, new_thread->ebbrr);
1131 if (old_thread->fscr != new_thread->fscr)
1132 mtspr(SPRN_FSCR, new_thread->fscr);
1134 if (old_thread->tar != new_thread->tar)
1135 mtspr(SPRN_TAR, new_thread->tar);
1140 struct task_struct *__switch_to(struct task_struct *prev,
1141 struct task_struct *new)
1143 struct thread_struct *new_thread, *old_thread;
1144 struct task_struct *last;
1145 #ifdef CONFIG_PPC_BOOK3S_64
1146 struct ppc64_tlb_batch *batch;
1149 new_thread = &new->thread;
1150 old_thread = ¤t->thread;
1152 WARN_ON(!irqs_disabled());
1156 * Collect processor utilization data per process
1158 if (firmware_has_feature(FW_FEATURE_SPLPAR)) {
1159 struct cpu_usage *cu = this_cpu_ptr(&cpu_usage_array);
1160 long unsigned start_tb, current_tb;
1161 start_tb = old_thread->start_tb;
1162 cu->current_tb = current_tb = mfspr(SPRN_PURR);
1163 old_thread->accum_tb += (current_tb - start_tb);
1164 new_thread->start_tb = current_tb;
1166 #endif /* CONFIG_PPC64 */
1168 #ifdef CONFIG_PPC_STD_MMU_64
1169 batch = this_cpu_ptr(&ppc64_tlb_batch);
1170 if (batch->active) {
1171 current_thread_info()->local_flags |= _TLF_LAZY_MMU;
1173 __flush_tlb_pending(batch);
1176 #endif /* CONFIG_PPC_STD_MMU_64 */
1178 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1179 switch_booke_debug_regs(&new->thread.debug);
1182 * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
1185 #ifndef CONFIG_HAVE_HW_BREAKPOINT
1186 if (unlikely(!hw_brk_match(this_cpu_ptr(¤t_brk), &new->thread.hw_brk)))
1187 __set_breakpoint(&new->thread.hw_brk);
1188 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1192 * We need to save SPRs before treclaim/trecheckpoint as these will
1193 * change a number of them.
1195 save_sprs(&prev->thread);
1197 /* Save FPU, Altivec, VSX and SPE state */
1200 __switch_to_tm(prev, new);
1202 if (!radix_enabled()) {
1204 * We can't take a PMU exception inside _switch() since there
1205 * is a window where the kernel stack SLB and the kernel stack
1206 * are out of sync. Hard disable here.
1212 * Call restore_sprs() before calling _switch(). If we move it after
1213 * _switch() then we miss out on calling it for new tasks. The reason
1214 * for this is we manually create a stack frame for new tasks that
1215 * directly returns through ret_from_fork() or
1216 * ret_from_kernel_thread(). See copy_thread() for details.
1218 restore_sprs(old_thread, new_thread);
1220 last = _switch(old_thread, new_thread);
1222 #ifdef CONFIG_PPC_STD_MMU_64
1223 if (current_thread_info()->local_flags & _TLF_LAZY_MMU) {
1224 current_thread_info()->local_flags &= ~_TLF_LAZY_MMU;
1225 batch = this_cpu_ptr(&ppc64_tlb_batch);
1229 if (current_thread_info()->task->thread.regs)
1230 restore_math(current_thread_info()->task->thread.regs);
1231 #endif /* CONFIG_PPC_STD_MMU_64 */
1236 static int instructions_to_print = 16;
1238 static void show_instructions(struct pt_regs *regs)
1241 unsigned long pc = regs->nip - (instructions_to_print * 3 / 4 *
1244 printk("Instruction dump:");
1246 for (i = 0; i < instructions_to_print; i++) {
1252 #if !defined(CONFIG_BOOKE)
1253 /* If executing with the IMMU off, adjust pc rather
1254 * than print XXXXXXXX.
1256 if (!(regs->msr & MSR_IR))
1257 pc = (unsigned long)phys_to_virt(pc);
1260 if (!__kernel_text_address(pc) ||
1261 probe_kernel_address((unsigned int __user *)pc, instr)) {
1262 pr_cont("XXXXXXXX ");
1264 if (regs->nip == pc)
1265 pr_cont("<%08x> ", instr);
1267 pr_cont("%08x ", instr);
1281 static struct regbit msr_bits[] = {
1282 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
1304 #ifndef CONFIG_BOOKE
1311 static void print_bits(unsigned long val, struct regbit *bits, const char *sep)
1315 for (; bits->bit; ++bits)
1316 if (val & bits->bit) {
1317 pr_cont("%s%s", s, bits->name);
1322 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1323 static struct regbit msr_tm_bits[] = {
1330 static void print_tm_bits(unsigned long val)
1333 * This only prints something if at least one of the TM bit is set.
1334 * Inside the TM[], the output means:
1335 * E: Enabled (bit 32)
1336 * S: Suspended (bit 33)
1337 * T: Transactional (bit 34)
1339 if (val & (MSR_TM | MSR_TS_S | MSR_TS_T)) {
1341 print_bits(val, msr_tm_bits, "");
1346 static void print_tm_bits(unsigned long val) {}
1349 static void print_msr_bits(unsigned long val)
1352 print_bits(val, msr_bits, ",");
1358 #define REG "%016lx"
1359 #define REGS_PER_LINE 4
1360 #define LAST_VOLATILE 13
1363 #define REGS_PER_LINE 8
1364 #define LAST_VOLATILE 12
1367 void show_regs(struct pt_regs * regs)
1371 show_regs_print_info(KERN_DEFAULT);
1373 printk("NIP: "REG" LR: "REG" CTR: "REG"\n",
1374 regs->nip, regs->link, regs->ctr);
1375 printk("REGS: %p TRAP: %04lx %s (%s)\n",
1376 regs, regs->trap, print_tainted(), init_utsname()->release);
1377 printk("MSR: "REG" ", regs->msr);
1378 print_msr_bits(regs->msr);
1379 printk(" CR: %08lx XER: %08lx\n", regs->ccr, regs->xer);
1381 if ((regs->trap != 0xc00) && cpu_has_feature(CPU_FTR_CFAR))
1382 pr_cont("CFAR: "REG" ", regs->orig_gpr3);
1383 if (trap == 0x200 || trap == 0x300 || trap == 0x600)
1384 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
1385 pr_cont("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr);
1387 pr_cont("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr);
1390 pr_cont("SOFTE: %ld ", regs->softe);
1392 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1393 if (MSR_TM_ACTIVE(regs->msr))
1394 pr_cont("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch);
1397 for (i = 0; i < 32; i++) {
1398 if ((i % REGS_PER_LINE) == 0)
1399 pr_cont("\nGPR%02d: ", i);
1400 pr_cont(REG " ", regs->gpr[i]);
1401 if (i == LAST_VOLATILE && !FULL_REGS(regs))
1405 #ifdef CONFIG_KALLSYMS
1407 * Lookup NIP late so we have the best change of getting the
1408 * above info out without failing
1410 printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip);
1411 printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link);
1413 show_stack(current, (unsigned long *) regs->gpr[1]);
1414 if (!user_mode(regs))
1415 show_instructions(regs);
1418 void flush_thread(void)
1420 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1421 flush_ptrace_hw_breakpoint(current);
1422 #else /* CONFIG_HAVE_HW_BREAKPOINT */
1423 set_debug_reg_defaults(¤t->thread);
1424 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1428 release_thread(struct task_struct *t)
1433 * this gets called so that we can store coprocessor state into memory and
1434 * copy the current task into the new thread.
1436 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
1438 flush_all_to_thread(src);
1440 * Flush TM state out so we can copy it. __switch_to_tm() does this
1441 * flush but it removes the checkpointed state from the current CPU and
1442 * transitions the CPU out of TM mode. Hence we need to call
1443 * tm_recheckpoint_new_task() (on the same task) to restore the
1444 * checkpointed state back and the TM mode.
1446 * Can't pass dst because it isn't ready. Doesn't matter, passing
1447 * dst is only important for __switch_to()
1449 __switch_to_tm(src, src);
1453 clear_task_ebb(dst);
1458 static void setup_ksp_vsid(struct task_struct *p, unsigned long sp)
1460 #ifdef CONFIG_PPC_STD_MMU_64
1461 unsigned long sp_vsid;
1462 unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp;
1464 if (radix_enabled())
1467 if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
1468 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T)
1469 << SLB_VSID_SHIFT_1T;
1471 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M)
1473 sp_vsid |= SLB_VSID_KERNEL | llp;
1474 p->thread.ksp_vsid = sp_vsid;
1483 * Copy architecture-specific thread state
1485 int copy_thread(unsigned long clone_flags, unsigned long usp,
1486 unsigned long kthread_arg, struct task_struct *p)
1488 struct pt_regs *childregs, *kregs;
1489 extern void ret_from_fork(void);
1490 extern void ret_from_kernel_thread(void);
1492 unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE;
1493 struct thread_info *ti = task_thread_info(p);
1495 klp_init_thread_info(ti);
1497 /* Copy registers */
1498 sp -= sizeof(struct pt_regs);
1499 childregs = (struct pt_regs *) sp;
1500 if (unlikely(p->flags & PF_KTHREAD)) {
1502 memset(childregs, 0, sizeof(struct pt_regs));
1503 childregs->gpr[1] = sp + sizeof(struct pt_regs);
1506 childregs->gpr[14] = ppc_function_entry((void *)usp);
1508 clear_tsk_thread_flag(p, TIF_32BIT);
1509 childregs->softe = 1;
1511 childregs->gpr[15] = kthread_arg;
1512 p->thread.regs = NULL; /* no user register state */
1513 ti->flags |= _TIF_RESTOREALL;
1514 f = ret_from_kernel_thread;
1517 struct pt_regs *regs = current_pt_regs();
1518 CHECK_FULL_REGS(regs);
1521 childregs->gpr[1] = usp;
1522 p->thread.regs = childregs;
1523 childregs->gpr[3] = 0; /* Result from fork() */
1524 if (clone_flags & CLONE_SETTLS) {
1526 if (!is_32bit_task())
1527 childregs->gpr[13] = childregs->gpr[6];
1530 childregs->gpr[2] = childregs->gpr[6];
1535 childregs->msr &= ~(MSR_FP|MSR_VEC|MSR_VSX);
1536 sp -= STACK_FRAME_OVERHEAD;
1539 * The way this works is that at some point in the future
1540 * some task will call _switch to switch to the new task.
1541 * That will pop off the stack frame created below and start
1542 * the new task running at ret_from_fork. The new task will
1543 * do some house keeping and then return from the fork or clone
1544 * system call, using the stack frame created above.
1546 ((unsigned long *)sp)[0] = 0;
1547 sp -= sizeof(struct pt_regs);
1548 kregs = (struct pt_regs *) sp;
1549 sp -= STACK_FRAME_OVERHEAD;
1552 p->thread.ksp_limit = (unsigned long)task_stack_page(p) +
1553 _ALIGN_UP(sizeof(struct thread_info), 16);
1555 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1556 p->thread.ptrace_bps[0] = NULL;
1559 p->thread.fp_save_area = NULL;
1560 #ifdef CONFIG_ALTIVEC
1561 p->thread.vr_save_area = NULL;
1564 setup_ksp_vsid(p, sp);
1567 if (cpu_has_feature(CPU_FTR_DSCR)) {
1568 p->thread.dscr_inherit = current->thread.dscr_inherit;
1569 p->thread.dscr = mfspr(SPRN_DSCR);
1571 if (cpu_has_feature(CPU_FTR_HAS_PPR))
1572 p->thread.ppr = INIT_PPR;
1574 kregs->nip = ppc_function_entry(f);
1579 * Set up a thread for executing a new program
1581 void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp)
1584 unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */
1588 * If we exec out of a kernel thread then thread.regs will not be
1591 if (!current->thread.regs) {
1592 struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE;
1593 current->thread.regs = regs - 1;
1596 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1598 * Clear any transactional state, we're exec()ing. The cause is
1599 * not important as there will never be a recheckpoint so it's not
1602 if (MSR_TM_SUSPENDED(mfmsr()))
1603 tm_reclaim_current(0);
1606 memset(regs->gpr, 0, sizeof(regs->gpr));
1614 * We have just cleared all the nonvolatile GPRs, so make
1615 * FULL_REGS(regs) return true. This is necessary to allow
1616 * ptrace to examine the thread immediately after exec.
1623 regs->msr = MSR_USER;
1625 if (!is_32bit_task()) {
1626 unsigned long entry;
1628 if (is_elf2_task()) {
1629 /* Look ma, no function descriptors! */
1634 * The latest iteration of the ABI requires that when
1635 * calling a function (at its global entry point),
1636 * the caller must ensure r12 holds the entry point
1637 * address (so that the function can quickly
1638 * establish addressability).
1640 regs->gpr[12] = start;
1641 /* Make sure that's restored on entry to userspace. */
1642 set_thread_flag(TIF_RESTOREALL);
1646 /* start is a relocated pointer to the function
1647 * descriptor for the elf _start routine. The first
1648 * entry in the function descriptor is the entry
1649 * address of _start and the second entry is the TOC
1650 * value we need to use.
1652 __get_user(entry, (unsigned long __user *)start);
1653 __get_user(toc, (unsigned long __user *)start+1);
1655 /* Check whether the e_entry function descriptor entries
1656 * need to be relocated before we can use them.
1658 if (load_addr != 0) {
1665 regs->msr = MSR_USER64;
1669 regs->msr = MSR_USER32;
1673 current->thread.used_vsr = 0;
1675 memset(¤t->thread.fp_state, 0, sizeof(current->thread.fp_state));
1676 current->thread.fp_save_area = NULL;
1677 #ifdef CONFIG_ALTIVEC
1678 memset(¤t->thread.vr_state, 0, sizeof(current->thread.vr_state));
1679 current->thread.vr_state.vscr.u[3] = 0x00010000; /* Java mode disabled */
1680 current->thread.vr_save_area = NULL;
1681 current->thread.vrsave = 0;
1682 current->thread.used_vr = 0;
1683 #endif /* CONFIG_ALTIVEC */
1685 memset(current->thread.evr, 0, sizeof(current->thread.evr));
1686 current->thread.acc = 0;
1687 current->thread.spefscr = 0;
1688 current->thread.used_spe = 0;
1689 #endif /* CONFIG_SPE */
1690 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1691 current->thread.tm_tfhar = 0;
1692 current->thread.tm_texasr = 0;
1693 current->thread.tm_tfiar = 0;
1694 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1696 EXPORT_SYMBOL(start_thread);
1698 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \
1699 | PR_FP_EXC_RES | PR_FP_EXC_INV)
1701 int set_fpexc_mode(struct task_struct *tsk, unsigned int val)
1703 struct pt_regs *regs = tsk->thread.regs;
1705 /* This is a bit hairy. If we are an SPE enabled processor
1706 * (have embedded fp) we store the IEEE exception enable flags in
1707 * fpexc_mode. fpexc_mode is also used for setting FP exception
1708 * mode (asyn, precise, disabled) for 'Classic' FP. */
1709 if (val & PR_FP_EXC_SW_ENABLE) {
1711 if (cpu_has_feature(CPU_FTR_SPE)) {
1713 * When the sticky exception bits are set
1714 * directly by userspace, it must call prctl
1715 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1716 * in the existing prctl settings) or
1717 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1718 * the bits being set). <fenv.h> functions
1719 * saving and restoring the whole
1720 * floating-point environment need to do so
1721 * anyway to restore the prctl settings from
1722 * the saved environment.
1724 tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1725 tsk->thread.fpexc_mode = val &
1726 (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT);
1736 /* on a CONFIG_SPE this does not hurt us. The bits that
1737 * __pack_fe01 use do not overlap with bits used for
1738 * PR_FP_EXC_SW_ENABLE. Additionally, the MSR[FE0,FE1] bits
1739 * on CONFIG_SPE implementations are reserved so writing to
1740 * them does not change anything */
1741 if (val > PR_FP_EXC_PRECISE)
1743 tsk->thread.fpexc_mode = __pack_fe01(val);
1744 if (regs != NULL && (regs->msr & MSR_FP) != 0)
1745 regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1))
1746 | tsk->thread.fpexc_mode;
1750 int get_fpexc_mode(struct task_struct *tsk, unsigned long adr)
1754 if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE)
1756 if (cpu_has_feature(CPU_FTR_SPE)) {
1758 * When the sticky exception bits are set
1759 * directly by userspace, it must call prctl
1760 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1761 * in the existing prctl settings) or
1762 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1763 * the bits being set). <fenv.h> functions
1764 * saving and restoring the whole
1765 * floating-point environment need to do so
1766 * anyway to restore the prctl settings from
1767 * the saved environment.
1769 tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1770 val = tsk->thread.fpexc_mode;
1777 val = __unpack_fe01(tsk->thread.fpexc_mode);
1778 return put_user(val, (unsigned int __user *) adr);
1781 int set_endian(struct task_struct *tsk, unsigned int val)
1783 struct pt_regs *regs = tsk->thread.regs;
1785 if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) ||
1786 (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE)))
1792 if (val == PR_ENDIAN_BIG)
1793 regs->msr &= ~MSR_LE;
1794 else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE)
1795 regs->msr |= MSR_LE;
1802 int get_endian(struct task_struct *tsk, unsigned long adr)
1804 struct pt_regs *regs = tsk->thread.regs;
1807 if (!cpu_has_feature(CPU_FTR_PPC_LE) &&
1808 !cpu_has_feature(CPU_FTR_REAL_LE))
1814 if (regs->msr & MSR_LE) {
1815 if (cpu_has_feature(CPU_FTR_REAL_LE))
1816 val = PR_ENDIAN_LITTLE;
1818 val = PR_ENDIAN_PPC_LITTLE;
1820 val = PR_ENDIAN_BIG;
1822 return put_user(val, (unsigned int __user *)adr);
1825 int set_unalign_ctl(struct task_struct *tsk, unsigned int val)
1827 tsk->thread.align_ctl = val;
1831 int get_unalign_ctl(struct task_struct *tsk, unsigned long adr)
1833 return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr);
1836 static inline int valid_irq_stack(unsigned long sp, struct task_struct *p,
1837 unsigned long nbytes)
1839 unsigned long stack_page;
1840 unsigned long cpu = task_cpu(p);
1843 * Avoid crashing if the stack has overflowed and corrupted
1844 * task_cpu(p), which is in the thread_info struct.
1846 if (cpu < NR_CPUS && cpu_possible(cpu)) {
1847 stack_page = (unsigned long) hardirq_ctx[cpu];
1848 if (sp >= stack_page + sizeof(struct thread_struct)
1849 && sp <= stack_page + THREAD_SIZE - nbytes)
1852 stack_page = (unsigned long) softirq_ctx[cpu];
1853 if (sp >= stack_page + sizeof(struct thread_struct)
1854 && sp <= stack_page + THREAD_SIZE - nbytes)
1860 int validate_sp(unsigned long sp, struct task_struct *p,
1861 unsigned long nbytes)
1863 unsigned long stack_page = (unsigned long)task_stack_page(p);
1865 if (sp >= stack_page + sizeof(struct thread_struct)
1866 && sp <= stack_page + THREAD_SIZE - nbytes)
1869 return valid_irq_stack(sp, p, nbytes);
1872 EXPORT_SYMBOL(validate_sp);
1874 unsigned long get_wchan(struct task_struct *p)
1876 unsigned long ip, sp;
1879 if (!p || p == current || p->state == TASK_RUNNING)
1883 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
1887 sp = *(unsigned long *)sp;
1888 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
1891 ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE];
1892 if (!in_sched_functions(ip))
1895 } while (count++ < 16);
1899 static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH;
1901 void show_stack(struct task_struct *tsk, unsigned long *stack)
1903 unsigned long sp, ip, lr, newsp;
1906 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1907 int curr_frame = current->curr_ret_stack;
1908 extern void return_to_handler(void);
1909 unsigned long rth = (unsigned long)return_to_handler;
1912 sp = (unsigned long) stack;
1917 sp = current_stack_pointer();
1919 sp = tsk->thread.ksp;
1923 printk("Call Trace:\n");
1925 if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD))
1928 stack = (unsigned long *) sp;
1930 ip = stack[STACK_FRAME_LR_SAVE];
1931 if (!firstframe || ip != lr) {
1932 printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip);
1933 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1934 if ((ip == rth) && curr_frame >= 0) {
1936 (void *)current->ret_stack[curr_frame].ret);
1941 pr_cont(" (unreliable)");
1947 * See if this is an exception frame.
1948 * We look for the "regshere" marker in the current frame.
1950 if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE)
1951 && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) {
1952 struct pt_regs *regs = (struct pt_regs *)
1953 (sp + STACK_FRAME_OVERHEAD);
1955 printk("--- interrupt: %lx at %pS\n LR = %pS\n",
1956 regs->trap, (void *)regs->nip, (void *)lr);
1961 } while (count++ < kstack_depth_to_print);
1965 /* Called with hard IRQs off */
1966 void notrace __ppc64_runlatch_on(void)
1968 struct thread_info *ti = current_thread_info();
1971 ctrl = mfspr(SPRN_CTRLF);
1972 ctrl |= CTRL_RUNLATCH;
1973 mtspr(SPRN_CTRLT, ctrl);
1975 ti->local_flags |= _TLF_RUNLATCH;
1978 /* Called with hard IRQs off */
1979 void notrace __ppc64_runlatch_off(void)
1981 struct thread_info *ti = current_thread_info();
1984 ti->local_flags &= ~_TLF_RUNLATCH;
1986 ctrl = mfspr(SPRN_CTRLF);
1987 ctrl &= ~CTRL_RUNLATCH;
1988 mtspr(SPRN_CTRLT, ctrl);
1990 #endif /* CONFIG_PPC64 */
1992 unsigned long arch_align_stack(unsigned long sp)
1994 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
1995 sp -= get_random_int() & ~PAGE_MASK;
1999 static inline unsigned long brk_rnd(void)
2001 unsigned long rnd = 0;
2003 /* 8MB for 32bit, 1GB for 64bit */
2004 if (is_32bit_task())
2005 rnd = (get_random_long() % (1UL<<(23-PAGE_SHIFT)));
2007 rnd = (get_random_long() % (1UL<<(30-PAGE_SHIFT)));
2009 return rnd << PAGE_SHIFT;
2012 unsigned long arch_randomize_brk(struct mm_struct *mm)
2014 unsigned long base = mm->brk;
2017 #ifdef CONFIG_PPC_STD_MMU_64
2019 * If we are using 1TB segments and we are allowed to randomise
2020 * the heap, we can put it above 1TB so it is backed by a 1TB
2021 * segment. Otherwise the heap will be in the bottom 1TB
2022 * which always uses 256MB segments and this may result in a
2023 * performance penalty. We don't need to worry about radix. For
2024 * radix, mmu_highuser_ssize remains unchanged from 256MB.
2026 if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T))
2027 base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T);
2030 ret = PAGE_ALIGN(base + brk_rnd());