arch/blackfin/mach-bf609/boards/ezkit.c

   1 /*
   2  * Copyright 2004-2009 Analog Devices Inc.
   3  *                2005 National ICT Australia (NICTA)
   4  *                      Aidan Williams <aidan@nicta.com.au>
   5  *
   6  * Licensed under the GPL-2 or later.
   7  */
   8
   9 #include <linux/device.h>
  10 #include <linux/platform_device.h>
  11 #include <linux/mtd/mtd.h>
  12 #include <linux/mtd/partitions.h>
  13 #include <linux/mtd/physmap.h>
  14 #include <linux/spi/spi.h>
  15 #include <linux/spi/flash.h>
  16 #include <linux/irq.h>
  17 #include <linux/i2c.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/usb/musb.h>
  20 #include <asm/bfin_spi3.h>
  21 #include <asm/dma.h>
  22 #include <asm/gpio.h>
  23 #include <asm/nand.h>
  24 #include <asm/dpmc.h>
  25 #include <asm/portmux.h>
  26 #include <asm/bfin_sdh.h>
  27 #include <linux/input.h>
  28 #include <linux/spi/ad7877.h>
  29
  30 /*
  31  * Name the Board for the /proc/cpuinfo
  32  */
  33 const char bfin_board_name[] = "ADI BF609-EZKIT";
  34
  35 /*
  36  *  Driver needs to know address, irq and flag pin.
  37  */
  38
  39 #if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
  40 #include <linux/usb/isp1760.h>
  41 static struct resource bfin_isp1760_resources[] = {
  42         [0] = {
  43                 .start  = 0x2C0C0000,
  44                 .end    = 0x2C0C0000 + 0xfffff,
  45                 .flags  = IORESOURCE_MEM,
  46         },
  47         [1] = {
  48                 .start  = IRQ_PG7,
  49                 .end    = IRQ_PG7,
  50                 .flags  = IORESOURCE_IRQ,
  51         },
  52 };
  53
  54 static struct isp1760_platform_data isp1760_priv = {
  55         .is_isp1761 = 0,
  56         .bus_width_16 = 1,
  57         .port1_otg = 0,
  58         .analog_oc = 0,
  59         .dack_polarity_high = 0,
  60         .dreq_polarity_high = 0,
  61 };
  62
  63 static struct platform_device bfin_isp1760_device = {
  64         .name           = "isp1760",
  65         .id             = 0,
  66         .dev = {
  67                 .platform_data = &isp1760_priv,
  68         },
  69         .num_resources  = ARRAY_SIZE(bfin_isp1760_resources),
  70         .resource       = bfin_isp1760_resources,
  71 };
  72 #endif
  73
  74 #if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE)
  75 #include <asm/bfin_rotary.h>
  76
  77 static struct bfin_rotary_platform_data bfin_rotary_data = {
  78         /*.rotary_up_key     = KEY_UP,*/
  79         /*.rotary_down_key   = KEY_DOWN,*/
  80         .rotary_rel_code   = REL_WHEEL,
  81         .rotary_button_key = KEY_ENTER,
  82         .debounce          = 10,        /* 0..17 */
  83         .mode              = ROT_QUAD_ENC | ROT_DEBE,
  84 };
  85
  86 static struct resource bfin_rotary_resources[] = {
  87         {
  88                 .start = IRQ_CNT,
  89                 .end = IRQ_CNT,
  90                 .flags = IORESOURCE_IRQ,
  91         },
  92 };
  93
  94 static struct platform_device bfin_rotary_device = {
  95         .name           = "bfin-rotary",
  96         .id             = -1,
  97         .num_resources  = ARRAY_SIZE(bfin_rotary_resources),
  98         .resource       = bfin_rotary_resources,
  99         .dev            = {
 100                 .platform_data = &bfin_rotary_data,
 101         },
 102 };
 103 #endif
 104
 105 #if defined(CONFIG_STMMAC_ETH) || defined(CONFIG_STMMAC_ETH_MODULE)
 106 #include <linux/stmmac.h>
 107
 108 static unsigned short pins[] = P_RMII0;
 109
 110 static struct stmmac_mdio_bus_data phy_private_data = {
 111         .phy_mask = 1,
 112 };
 113
 114 static struct plat_stmmacenet_data eth_private_data = {
 115         .bus_id   = 0,
 116         .enh_desc = 1,
 117         .phy_addr = 1,
 118         .mdio_bus_data = &phy_private_data,
 119 };
 120
 121 static struct platform_device bfin_eth_device = {
 122         .name           = "stmmaceth",
 123         .id             = 0,
 124         .num_resources  = 2,
 125         .resource       = (struct resource[]) {
 126                 {
 127                         .start  = EMAC0_MACCFG,
 128                         .end    = EMAC0_MACCFG + 0x1274,
 129                         .flags  = IORESOURCE_MEM,
 130                 },
 131                 {
 132                         .name   = "macirq",
 133                         .start  = IRQ_EMAC0_STAT,
 134                         .end    = IRQ_EMAC0_STAT,
 135                         .flags  = IORESOURCE_IRQ,
 136                 },
 137         },
 138         .dev = {
 139                 .power.can_wakeup = 1,
 140                 .platform_data = &eth_private_data,
 141         }
 142 };
 143 #endif
 144
 145 #if defined(CONFIG_INPUT_ADXL34X) || defined(CONFIG_INPUT_ADXL34X_MODULE)
 146 #include <linux/input/adxl34x.h>
 147 static const struct adxl34x_platform_data adxl34x_info = {
 148         .x_axis_offset = 0,
 149         .y_axis_offset = 0,
 150         .z_axis_offset = 0,
 151         .tap_threshold = 0x31,
 152         .tap_duration = 0x10,
 153         .tap_latency = 0x60,
 154         .tap_window = 0xF0,
 155         .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN,
 156         .act_axis_control = 0xFF,
 157         .activity_threshold = 5,
 158         .inactivity_threshold = 3,
 159         .inactivity_time = 4,
 160         .free_fall_threshold = 0x7,
 161         .free_fall_time = 0x20,
 162         .data_rate = 0x8,
 163         .data_range = ADXL_FULL_RES,
 164
 165         .ev_type = EV_ABS,
 166         .ev_code_x = ABS_X,             /* EV_REL */
 167         .ev_code_y = ABS_Y,             /* EV_REL */
 168         .ev_code_z = ABS_Z,             /* EV_REL */
 169
 170         .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */
 171
 172 /*      .ev_code_ff = KEY_F,*/          /* EV_KEY */
 173 /*      .ev_code_act_inactivity = KEY_A,*/      /* EV_KEY */
 174         .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK,
 175         .fifo_mode = ADXL_FIFO_STREAM,
 176         .orientation_enable = ADXL_EN_ORIENTATION_3D,
 177         .deadzone_angle = ADXL_DEADZONE_ANGLE_10p8,
 178         .divisor_length = ADXL_LP_FILTER_DIVISOR_16,
 179         /* EV_KEY {+Z, +Y, +X, -X, -Y, -Z} */
 180         .ev_codes_orient_3d = {BTN_Z, BTN_Y, BTN_X, BTN_A, BTN_B, BTN_C},
 181 };
 182 #endif
 183
 184 #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
 185 static struct platform_device rtc_device = {
 186         .name = "rtc-bfin",
 187         .id   = -1,
 188 };
 189 #endif
 190
 191 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
 192 #ifdef CONFIG_SERIAL_BFIN_UART0
 193 static struct resource bfin_uart0_resources[] = {
 194         {
 195                 .start = UART0_REVID,
 196                 .end = UART0_RXDIV+4,
 197                 .flags = IORESOURCE_MEM,
 198         },
 199         {
 200                 .start = IRQ_UART0_TX,
 201                 .end = IRQ_UART0_TX,
 202                 .flags = IORESOURCE_IRQ,
 203         },
 204         {
 205                 .start = IRQ_UART0_RX,
 206                 .end = IRQ_UART0_RX,
 207                 .flags = IORESOURCE_IRQ,
 208         },
 209         {
 210                 .start = IRQ_UART0_STAT,
 211                 .end = IRQ_UART0_STAT,
 212                 .flags = IORESOURCE_IRQ,
 213         },
 214         {
 215                 .start = CH_UART0_TX,
 216                 .end = CH_UART0_TX,
 217                 .flags = IORESOURCE_DMA,
 218         },
 219         {
 220                 .start = CH_UART0_RX,
 221                 .end = CH_UART0_RX,
 222                 .flags = IORESOURCE_DMA,
 223         },
 224 #ifdef CONFIG_BFIN_UART0_CTSRTS
 225         {       /* CTS pin -- 0 means not supported */
 226                 .start = GPIO_PD10,
 227                 .end = GPIO_PD10,
 228                 .flags = IORESOURCE_IO,
 229         },
 230         {       /* RTS pin -- 0 means not supported */
 231                 .start = GPIO_PD9,
 232                 .end = GPIO_PD9,
 233                 .flags = IORESOURCE_IO,
 234         },
 235 #endif
 236 };
 237
 238 static unsigned short bfin_uart0_peripherals[] = {
 239         P_UART0_TX, P_UART0_RX,
 240 #ifdef CONFIG_BFIN_UART0_CTSRTS
 241         P_UART0_RTS, P_UART0_CTS,
 242 #endif
 243         0
 244 };
 245
 246 static struct platform_device bfin_uart0_device = {
 247         .name = "bfin-uart",
 248         .id = 0,
 249         .num_resources = ARRAY_SIZE(bfin_uart0_resources),
 250         .resource = bfin_uart0_resources,
 251         .dev = {
 252                 .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
 253         },
 254 };
 255 #endif
 256 #ifdef CONFIG_SERIAL_BFIN_UART1
 257 static struct resource bfin_uart1_resources[] = {
 258         {
 259                 .start = UART1_REVID,
 260                 .end = UART1_RXDIV+4,
 261                 .flags = IORESOURCE_MEM,
 262         },
 263         {
 264                 .start = IRQ_UART1_TX,
 265                 .end = IRQ_UART1_TX,
 266                 .flags = IORESOURCE_IRQ,
 267         },
 268         {
 269                 .start = IRQ_UART1_RX,
 270                 .end = IRQ_UART1_RX,
 271                 .flags = IORESOURCE_IRQ,
 272         },
 273         {
 274                 .start = IRQ_UART1_STAT,
 275                 .end = IRQ_UART1_STAT,
 276                 .flags = IORESOURCE_IRQ,
 277         },
 278         {
 279                 .start = CH_UART1_TX,
 280                 .end = CH_UART1_TX,
 281                 .flags = IORESOURCE_DMA,
 282         },
 283         {
 284                 .start = CH_UART1_RX,
 285                 .end = CH_UART1_RX,
 286                 .flags = IORESOURCE_DMA,
 287         },
 288 #ifdef CONFIG_BFIN_UART1_CTSRTS
 289         {       /* CTS pin -- 0 means not supported */
 290                 .start = GPIO_PG13,
 291                 .end = GPIO_PG13,
 292                 .flags = IORESOURCE_IO,
 293         },
 294         {       /* RTS pin -- 0 means not supported */
 295                 .start = GPIO_PG10,
 296                 .end = GPIO_PG10,
 297                 .flags = IORESOURCE_IO,
 298         },
 299 #endif
 300 };
 301
 302 static unsigned short bfin_uart1_peripherals[] = {
 303         P_UART1_TX, P_UART1_RX,
 304 #ifdef CONFIG_BFIN_UART1_CTSRTS
 305         P_UART1_RTS, P_UART1_CTS,
 306 #endif
 307         0
 308 };
 309
 310 static struct platform_device bfin_uart1_device = {
 311         .name = "bfin-uart",
 312         .id = 1,
 313         .num_resources = ARRAY_SIZE(bfin_uart1_resources),
 314         .resource = bfin_uart1_resources,
 315         .dev = {
 316                 .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
 317         },
 318 };
 319 #endif
 320 #endif
 321
 322 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
 323 #ifdef CONFIG_BFIN_SIR0
 324 static struct resource bfin_sir0_resources[] = {
 325         {
 326                 .start = 0xFFC00400,
 327                 .end = 0xFFC004FF,
 328                 .flags = IORESOURCE_MEM,
 329         },
 330         {
 331                 .start = IRQ_UART0_TX,
 332                 .end = IRQ_UART0_TX+1,
 333                 .flags = IORESOURCE_IRQ,
 334         },
 335         {
 336                 .start = CH_UART0_TX,
 337                 .end = CH_UART0_TX+1,
 338                 .flags = IORESOURCE_DMA,
 339         },
 340 };
 341 static struct platform_device bfin_sir0_device = {
 342         .name = "bfin_sir",
 343         .id = 0,
 344         .num_resources = ARRAY_SIZE(bfin_sir0_resources),
 345         .resource = bfin_sir0_resources,
 346 };
 347 #endif
 348 #ifdef CONFIG_BFIN_SIR1
 349 static struct resource bfin_sir1_resources[] = {
 350         {
 351                 .start = 0xFFC02000,
 352                 .end = 0xFFC020FF,
 353                 .flags = IORESOURCE_MEM,
 354         },
 355         {
 356                 .start = IRQ_UART1_TX,
 357                 .end = IRQ_UART1_TX+1,
 358                 .flags = IORESOURCE_IRQ,
 359         },
 360         {
 361                 .start = CH_UART1_TX,
 362                 .end = CH_UART1_TX+1,
 363                 .flags = IORESOURCE_DMA,
 364         },
 365 };
 366 static struct platform_device bfin_sir1_device = {
 367         .name = "bfin_sir",
 368         .id = 1,
 369         .num_resources = ARRAY_SIZE(bfin_sir1_resources),
 370         .resource = bfin_sir1_resources,
 371 };
 372 #endif
 373 #endif
 374
 375 #if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
 376 static struct resource musb_resources[] = {
 377         [0] = {
 378                 .start  = 0xFFCC1000,
 379                 .end    = 0xFFCC1398,
 380                 .flags  = IORESOURCE_MEM,
 381         },
 382         [1] = { /* general IRQ */
 383                 .start  = IRQ_USB_STAT,
 384                 .end    = IRQ_USB_STAT,
 385                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
 386                 .name   = "mc"
 387         },
 388         [2] = { /* DMA IRQ */
 389                 .start  = IRQ_USB_DMA,
 390                 .end    = IRQ_USB_DMA,
 391                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
 392                 .name   = "dma"
 393         },
 394 };
 395
 396 static struct musb_hdrc_config musb_config = {
 397         .multipoint     = 1,
 398         .dyn_fifo       = 0,
 399         .dma            = 1,
 400         .num_eps        = 16,
 401         .dma_channels   = 8,
 402         .clkin          = 48,           /* musb CLKIN in MHZ */
 403 };
 404
 405 static struct musb_hdrc_platform_data musb_plat = {
 406 #if defined(CONFIG_USB_MUSB_HDRC) && defined(CONFIG_USB_GADGET_MUSB_HDRC)
 407         .mode           = MUSB_OTG,
 408 #elif defined(CONFIG_USB_MUSB_HDRC)
 409         .mode           = MUSB_HOST,
 410 #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
 411         .mode           = MUSB_PERIPHERAL,
 412 #endif
 413         .config         = &musb_config,
 414 };
 415
 416 static u64 musb_dmamask = ~(u32)0;
 417
 418 static struct platform_device musb_device = {
 419         .name           = "musb-blackfin",
 420         .id             = 0,
 421         .dev = {
 422                 .dma_mask               = &musb_dmamask,
 423                 .coherent_dma_mask      = 0xffffffff,
 424                 .platform_data          = &musb_plat,
 425         },
 426         .num_resources  = ARRAY_SIZE(musb_resources),
 427         .resource       = musb_resources,
 428 };
 429 #endif
 430
 431 #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
 432 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
 433 static struct resource bfin_sport0_uart_resources[] = {
 434         {
 435                 .start = SPORT0_TCR1,
 436                 .end = SPORT0_MRCS3+4,
 437                 .flags = IORESOURCE_MEM,
 438         },
 439         {
 440                 .start = IRQ_SPORT0_RX,
 441                 .end = IRQ_SPORT0_RX+1,
 442                 .flags = IORESOURCE_IRQ,
 443         },
 444         {
 445                 .start = IRQ_SPORT0_ERROR,
 446                 .end = IRQ_SPORT0_ERROR,
 447                 .flags = IORESOURCE_IRQ,
 448         },
 449 };
 450
 451 static unsigned short bfin_sport0_peripherals[] = {
 452         P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
 453         P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
 454 };
 455
 456 static struct platform_device bfin_sport0_uart_device = {
 457         .name = "bfin-sport-uart",
 458         .id = 0,
 459         .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
 460         .resource = bfin_sport0_uart_resources,
 461         .dev = {
 462                 .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
 463         },
 464 };
 465 #endif
 466 #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
 467 static struct resource bfin_sport1_uart_resources[] = {
 468         {
 469                 .start = SPORT1_TCR1,
 470                 .end = SPORT1_MRCS3+4,
 471                 .flags = IORESOURCE_MEM,
 472         },
 473         {
 474                 .start = IRQ_SPORT1_RX,
 475                 .end = IRQ_SPORT1_RX+1,
 476                 .flags = IORESOURCE_IRQ,
 477         },
 478         {
 479                 .start = IRQ_SPORT1_ERROR,
 480                 .end = IRQ_SPORT1_ERROR,
 481                 .flags = IORESOURCE_IRQ,
 482         },
 483 };
 484
 485 static unsigned short bfin_sport1_peripherals[] = {
 486         P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
 487         P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
 488 };
 489
 490 static struct platform_device bfin_sport1_uart_device = {
 491         .name = "bfin-sport-uart",
 492         .id = 1,
 493         .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
 494         .resource = bfin_sport1_uart_resources,
 495         .dev = {
 496                 .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
 497         },
 498 };
 499 #endif
 500 #ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
 501 static struct resource bfin_sport2_uart_resources[] = {
 502         {
 503                 .start = SPORT2_TCR1,
 504                 .end = SPORT2_MRCS3+4,
 505                 .flags = IORESOURCE_MEM,
 506         },
 507         {
 508                 .start = IRQ_SPORT2_RX,
 509                 .end = IRQ_SPORT2_RX+1,
 510                 .flags = IORESOURCE_IRQ,
 511         },
 512         {
 513                 .start = IRQ_SPORT2_ERROR,
 514                 .end = IRQ_SPORT2_ERROR,
 515                 .flags = IORESOURCE_IRQ,
 516         },
 517 };
 518
 519 static unsigned short bfin_sport2_peripherals[] = {
 520         P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS,
 521         P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0
 522 };
 523
 524 static struct platform_device bfin_sport2_uart_device = {
 525         .name = "bfin-sport-uart",
 526         .id = 2,
 527         .num_resources = ARRAY_SIZE(bfin_sport2_uart_resources),
 528         .resource = bfin_sport2_uart_resources,
 529         .dev = {
 530                 .platform_data = &bfin_sport2_peripherals, /* Passed to driver */
 531         },
 532 };
 533 #endif
 534 #endif
 535
 536 #if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
 537
 538 static unsigned short bfin_can0_peripherals[] = {
 539         P_CAN0_RX, P_CAN0_TX, 0
 540 };
 541
 542 static struct resource bfin_can0_resources[] = {
 543         {
 544                 .start = 0xFFC00A00,
 545                 .end = 0xFFC00FFF,
 546                 .flags = IORESOURCE_MEM,
 547         },
 548         {
 549                 .start = IRQ_CAN0_RX,
 550                 .end = IRQ_CAN0_RX,
 551                 .flags = IORESOURCE_IRQ,
 552         },
 553         {
 554                 .start = IRQ_CAN0_TX,
 555                 .end = IRQ_CAN0_TX,
 556                 .flags = IORESOURCE_IRQ,
 557         },
 558         {
 559                 .start = IRQ_CAN0_STAT,
 560                 .end = IRQ_CAN0_STAT,
 561                 .flags = IORESOURCE_IRQ,
 562         },
 563 };
 564
 565 static struct platform_device bfin_can0_device = {
 566         .name = "bfin_can",
 567         .id = 0,
 568         .num_resources = ARRAY_SIZE(bfin_can0_resources),
 569         .resource = bfin_can0_resources,
 570         .dev = {
 571                 .platform_data = &bfin_can0_peripherals, /* Passed to driver */
 572         },
 573 };
 574
 575 #endif
 576
 577 #if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
 578 static struct mtd_partition partition_info[] = {
 579         {
 580                 .name = "bootloader(nand)",
 581                 .offset = 0,
 582                 .size = 0x80000,
 583         }, {
 584                 .name = "linux kernel(nand)",
 585                 .offset = MTDPART_OFS_APPEND,
 586                 .size = 4 * 1024 * 1024,
 587         },
 588         {
 589                 .name = "file system(nand)",
 590                 .offset = MTDPART_OFS_APPEND,
 591                 .size = MTDPART_SIZ_FULL,
 592         },
 593 };
 594
 595 static struct bf5xx_nand_platform bfin_nand_platform = {
 596         .data_width = NFC_NWIDTH_8,
 597         .partitions = partition_info,
 598         .nr_partitions = ARRAY_SIZE(partition_info),
 599         .rd_dly = 3,
 600         .wr_dly = 3,
 601 };
 602
 603 static struct resource bfin_nand_resources[] = {
 604         {
 605                 .start = 0xFFC03B00,
 606                 .end = 0xFFC03B4F,
 607                 .flags = IORESOURCE_MEM,
 608         },
 609         {
 610                 .start = CH_NFC,
 611                 .end = CH_NFC,
 612                 .flags = IORESOURCE_IRQ,
 613         },
 614 };
 615
 616 static struct platform_device bfin_nand_device = {
 617         .name = "bfin-nand",
 618         .id = 0,
 619         .num_resources = ARRAY_SIZE(bfin_nand_resources),
 620         .resource = bfin_nand_resources,
 621         .dev = {
 622                 .platform_data = &bfin_nand_platform,
 623         },
 624 };
 625 #endif
 626
 627 #if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
 628
 629 static struct bfin_sd_host bfin_sdh_data = {
 630         .dma_chan = CH_RSI,
 631         .irq_int0 = IRQ_RSI_INT0,
 632         .pin_req = {P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0},
 633 };
 634
 635 static struct platform_device bfin_sdh_device = {
 636         .name = "bfin-sdh",
 637         .id = 0,
 638         .dev = {
 639                 .platform_data = &bfin_sdh_data,
 640         },
 641 };
 642 #endif
 643
 644 #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
 645 static struct mtd_partition ezkit_partitions[] = {
 646         {
 647                 .name       = "bootloader(nor)",
 648                 .size       = 0x80000,
 649                 .offset     = 0,
 650         }, {
 651                 .name       = "linux kernel(nor)",
 652                 .size       = 0x400000,
 653                 .offset     = MTDPART_OFS_APPEND,
 654         }, {
 655                 .name       = "file system(nor)",
 656                 .size       = 0x1000000 - 0x80000 - 0x400000,
 657                 .offset     = MTDPART_OFS_APPEND,
 658         },
 659 };
 660
 661 int bf609_nor_flash_init(struct platform_device *dev)
 662 {
 663 #define CONFIG_SMC_GCTL_VAL     0x00000010
 664         const unsigned short pins[] = {
 665                 P_A3, P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12,
 666                 P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20, P_A21,
 667                 P_A22, P_A23, P_A24, P_A25, P_NORCK, 0,
 668         };
 669
 670         peripheral_request_list(pins, "smc0");
 671
 672         bfin_write32(SMC_GCTL, CONFIG_SMC_GCTL_VAL);
 673         bfin_write32(SMC_B0CTL, 0x01002011);
 674         bfin_write32(SMC_B0TIM, 0x08170977);
 675         bfin_write32(SMC_B0ETIM, 0x00092231);
 676         return 0;
 677 }
 678
 679 void bf609_nor_flash_exit(struct platform_device *dev)
 680 {
 681         const unsigned short pins[] = {
 682                 P_A3, P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12,
 683                 P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20, P_A21,
 684                 P_A22, P_A23, P_A24, P_A25, P_NORCK, 0,
 685         };
 686
 687         peripheral_free_list(pins);
 688
 689         bfin_write32(SMC_GCTL, 0);
 690 }
 691
 692 static struct physmap_flash_data ezkit_flash_data = {
 693         .width      = 2,
 694         .parts      = ezkit_partitions,
 695         .init       = bf609_nor_flash_init,
 696         .exit       = bf609_nor_flash_exit,
 697         .nr_parts   = ARRAY_SIZE(ezkit_partitions),
 698 #ifdef CONFIG_ROMKERNEL
 699         .probe_type = "map_rom",
 700 #endif
 701 };
 702
 703 static struct resource ezkit_flash_resource = {
 704         .start = 0xb0000000,
 705         .end   = 0xb0ffffff,
 706         .flags = IORESOURCE_MEM,
 707 };
 708
 709 static struct platform_device ezkit_flash_device = {
 710         .name          = "physmap-flash",
 711         .id            = 0,
 712         .dev = {
 713                 .platform_data = &ezkit_flash_data,
 714         },
 715         .num_resources = 1,
 716         .resource      = &ezkit_flash_resource,
 717 };
 718 #endif
 719
 720 #if defined(CONFIG_MTD_M25P80) \
 721         || defined(CONFIG_MTD_M25P80_MODULE)
 722 /* SPI flash chip (w25q32) */
 723 static struct mtd_partition bfin_spi_flash_partitions[] = {
 724         {
 725                 .name = "bootloader(spi)",
 726                 .size = 0x00080000,
 727                 .offset = 0,
 728                 .mask_flags = MTD_CAP_ROM
 729         }, {
 730                 .name = "linux kernel(spi)",
 731                 .size = 0x00180000,
 732                 .offset = MTDPART_OFS_APPEND,
 733         }, {
 734                 .name = "file system(spi)",
 735                 .size = MTDPART_SIZ_FULL,
 736                 .offset = MTDPART_OFS_APPEND,
 737         }
 738 };
 739
 740 static struct flash_platform_data bfin_spi_flash_data = {
 741         .name = "m25p80",
 742         .parts = bfin_spi_flash_partitions,
 743         .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
 744         .type = "w25q32",
 745 };
 746
 747 static struct bfin_spi3_chip spi_flash_chip_info = {
 748         .enable_dma = true,         /* use dma transfer with this chip*/
 749 };
 750 #endif
 751
 752 #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
 753 static struct bfin_spi3_chip spidev_chip_info = {
 754         .enable_dma = true,
 755 };
 756 #endif
 757
 758 #if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
 759 static struct platform_device bfin_i2s_pcm = {
 760         .name = "bfin-i2s-pcm-audio",
 761         .id = -1,
 762 };
 763 #endif
 764
 765 #if defined(CONFIG_SND_BF6XX_SOC_I2S) || \
 766         defined(CONFIG_SND_BF6XX_SOC_I2S_MODULE)
 767 #include <asm/bfin_sport3.h>
 768 static struct resource bfin_snd_resources[] = {
 769         {
 770                 .start = SPORT0_CTL_A,
 771                 .end = SPORT0_CTL_A,
 772                 .flags = IORESOURCE_MEM,
 773         },
 774         {
 775                 .start = SPORT0_CTL_B,
 776                 .end = SPORT0_CTL_B,
 777                 .flags = IORESOURCE_MEM,
 778         },
 779         {
 780                 .start = CH_SPORT0_TX,
 781                 .end = CH_SPORT0_TX,
 782                 .flags = IORESOURCE_DMA,
 783         },
 784         {
 785                 .start = CH_SPORT0_RX,
 786                 .end = CH_SPORT0_RX,
 787                 .flags = IORESOURCE_DMA,
 788         },
 789         {
 790                 .start = IRQ_SPORT0_TX_STAT,
 791                 .end = IRQ_SPORT0_TX_STAT,
 792                 .flags = IORESOURCE_IRQ,
 793         },
 794         {
 795                 .start = IRQ_SPORT0_RX_STAT,
 796                 .end = IRQ_SPORT0_RX_STAT,
 797                 .flags = IORESOURCE_IRQ,
 798         },
 799 };
 800
 801 static const unsigned short bfin_snd_pin[] = {
 802         P_SPORT0_ACLK, P_SPORT0_AFS, P_SPORT0_AD0, P_SPORT0_BCLK,
 803         P_SPORT0_BFS, P_SPORT0_BD0, 0,
 804 };
 805
 806 static struct bfin_snd_platform_data bfin_snd_data = {
 807         .pin_req = bfin_snd_pin,
 808 };
 809
 810 static struct platform_device bfin_i2s = {
 811         .name = "bfin-i2s",
 812         .num_resources = ARRAY_SIZE(bfin_snd_resources),
 813         .resource = bfin_snd_resources,
 814         .dev = {
 815                 .platform_data = &bfin_snd_data,
 816         },
 817 };
 818 #endif
 819
 820 #if defined(CONFIG_SND_BF5XX_SOC_AD1836) \
 821                 || defined(CONFIG_SND_BF5XX_SOC_AD1836_MODULE)
 822 static const char * const ad1836_link[] = {
 823         "bfin-i2s.0",
 824         "spi0.76",
 825 };
 826 static struct platform_device bfin_ad1836_machine = {
 827         .name = "bfin-snd-ad1836",
 828         .id = -1,
 829         .dev = {
 830                 .platform_data = (void *)ad1836_link,
 831         },
 832 };
 833 #endif
 834
 835 #if defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61) || \
 836         defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61_MODULE)
 837 static struct platform_device adau1761_device = {
 838         .name = "bfin-eval-adau1x61",
 839 };
 840 #endif
 841
 842 #if defined(CONFIG_SND_SOC_ADAU1761) || defined(CONFIG_SND_SOC_ADAU1761_MODULE)
 843 #include <sound/adau17x1.h>
 844 static struct adau1761_platform_data adau1761_info = {
 845         .lineout_mode = ADAU1761_OUTPUT_MODE_LINE,
 846         .headphone_mode = ADAU1761_OUTPUT_MODE_HEADPHONE_CAPLESS,
 847 };
 848 #endif
 849
 850 #if defined(CONFIG_VIDEO_BLACKFIN_CAPTURE) \
 851         || defined(CONFIG_VIDEO_BLACKFIN_CAPTURE_MODULE)
 852 #include <linux/videodev2.h>
 853 #include <media/blackfin/bfin_capture.h>
 854 #include <media/blackfin/ppi.h>
 855
 856 static const unsigned short ppi_req[] = {
 857         P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
 858         P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
 859         P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
 860         P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15,
 861 #if !defined(CONFIG_VIDEO_VS6624) && !defined(CONFIG_VIDEO_VS6624_MODULE)
 862         P_PPI0_D16, P_PPI0_D17, P_PPI0_D18, P_PPI0_D19,
 863         P_PPI0_D20, P_PPI0_D21, P_PPI0_D22, P_PPI0_D23,
 864 #endif
 865         P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
 866         0,
 867 };
 868
 869 static const struct ppi_info ppi_info = {
 870         .type = PPI_TYPE_EPPI3,
 871         .dma_ch = CH_EPPI0_CH0,
 872         .irq_err = IRQ_EPPI0_STAT,
 873         .base = (void __iomem *)EPPI0_STAT,
 874         .pin_req = ppi_req,
 875 };
 876
 877 #if defined(CONFIG_VIDEO_VS6624) \
 878         || defined(CONFIG_VIDEO_VS6624_MODULE)
 879 static struct v4l2_input vs6624_inputs[] = {
 880         {
 881                 .index = 0,
 882                 .name = "Camera",
 883                 .type = V4L2_INPUT_TYPE_CAMERA,
 884                 .std = V4L2_STD_UNKNOWN,
 885         },
 886 };
 887
 888 static struct bcap_route vs6624_routes[] = {
 889         {
 890                 .input = 0,
 891                 .output = 0,
 892         },
 893 };
 894
 895 static const unsigned vs6624_ce_pin = GPIO_PE4;
 896
 897 static struct bfin_capture_config bfin_capture_data = {
 898         .card_name = "BF609",
 899         .inputs = vs6624_inputs,
 900         .num_inputs = ARRAY_SIZE(vs6624_inputs),
 901         .routes = vs6624_routes,
 902         .i2c_adapter_id = 0,
 903         .board_info = {
 904                 .type = "vs6624",
 905                 .addr = 0x10,
 906                 .platform_data = (void *)&vs6624_ce_pin,
 907         },
 908         .ppi_info = &ppi_info,
 909         .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FS1HI_FS2HI
 910                         | EPPI_CTL_POLC3 | EPPI_CTL_SYNC2 | EPPI_CTL_NON656),
 911         .blank_pixels = 4,
 912 };
 913 #endif
 914
 915 #if defined(CONFIG_VIDEO_ADV7842) \
 916         || defined(CONFIG_VIDEO_ADV7842_MODULE)
 917 #include <media/adv7842.h>
 918
 919 static struct v4l2_input adv7842_inputs[] = {
 920         {
 921                 .index = 0,
 922                 .name = "Composite",
 923                 .type = V4L2_INPUT_TYPE_CAMERA,
 924                 .std = V4L2_STD_ALL,
 925                 .capabilities = V4L2_IN_CAP_STD,
 926         },
 927         {
 928                 .index = 1,
 929                 .name = "S-Video",
 930                 .type = V4L2_INPUT_TYPE_CAMERA,
 931                 .std = V4L2_STD_ALL,
 932                 .capabilities = V4L2_IN_CAP_STD,
 933         },
 934         {
 935                 .index = 2,
 936                 .name = "Component",
 937                 .type = V4L2_INPUT_TYPE_CAMERA,
 938                 .capabilities = V4L2_IN_CAP_DV_TIMINGS,
 939         },
 940         {
 941                 .index = 3,
 942                 .name = "VGA",
 943                 .type = V4L2_INPUT_TYPE_CAMERA,
 944                 .capabilities = V4L2_IN_CAP_DV_TIMINGS,
 945         },
 946         {
 947                 .index = 4,
 948                 .name = "HDMI",
 949                 .type = V4L2_INPUT_TYPE_CAMERA,
 950                 .capabilities = V4L2_IN_CAP_DV_TIMINGS,
 951         },
 952 };
 953
 954 static struct bcap_route adv7842_routes[] = {
 955         {
 956                 .input = 3,
 957                 .output = 0,
 958                 .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FLDSEL
 959                                 | EPPI_CTL_ACTIVE656),
 960         },
 961         {
 962                 .input = 4,
 963                 .output = 0,
 964         },
 965         {
 966                 .input = 2,
 967                 .output = 0,
 968         },
 969         {
 970                 .input = 1,
 971                 .output = 0,
 972         },
 973         {
 974                 .input = 0,
 975                 .output = 1,
 976                 .ppi_control = (EPPI_CTL_SPLTWRD | PACK_EN | DLEN_16
 977                                 | EPPI_CTL_FS1LO_FS2LO | EPPI_CTL_POLC2
 978                                 | EPPI_CTL_SYNC2 | EPPI_CTL_NON656),
 979         },
 980 };
 981
 982 static struct adv7842_output_format adv7842_opf[] = {
 983         {
 984                 .op_ch_sel = ADV7842_OP_CH_SEL_BRG,
 985                 .op_format_sel = ADV7842_OP_FORMAT_SEL_SDR_ITU656_8,
 986                 .op_656_range = 1,
 987                 .blank_data = 1,
 988                 .insert_av_codes = 1,
 989         },
 990         {
 991                 .op_ch_sel = ADV7842_OP_CH_SEL_RGB,
 992                 .op_format_sel = ADV7842_OP_FORMAT_SEL_SDR_ITU656_16,
 993                 .op_656_range = 1,
 994                 .blank_data = 1,
 995         },
 996 };
 997
 998 static struct adv7842_platform_data adv7842_data = {
 999         .opf = adv7842_opf,
1000         .num_opf = ARRAY_SIZE(adv7842_opf),
1001         .ain_sel = ADV7842_AIN10_11_12_NC_SYNC_4_1,
1002         .prim_mode = ADV7842_PRIM_MODE_SDP,
1003         .vid_std_select = ADV7842_SDP_VID_STD_CVBS_SD_4x1,
1004         .inp_color_space = ADV7842_INP_COLOR_SPACE_AUTO,
1005         .i2c_sdp_io = 0x40,
1006         .i2c_sdp = 0x41,
1007         .i2c_cp = 0x42,
1008         .i2c_vdp = 0x43,
1009         .i2c_afe = 0x44,
1010         .i2c_hdmi = 0x45,
1011         .i2c_repeater = 0x46,
1012         .i2c_edid = 0x47,
1013         .i2c_infoframe = 0x48,
1014         .i2c_cec = 0x49,
1015         .i2c_avlink = 0x4a,
1016         .i2c_ex = 0x26,
1017 };
1018
1019 static struct bfin_capture_config bfin_capture_data = {
1020         .card_name = "BF609",
1021         .inputs = adv7842_inputs,
1022         .num_inputs = ARRAY_SIZE(adv7842_inputs),
1023         .routes = adv7842_routes,
1024         .i2c_adapter_id = 0,
1025         .board_info = {
1026                 .type = "adv7842",
1027                 .addr = 0x20,
1028                 .platform_data = (void *)&adv7842_data,
1029         },
1030         .ppi_info = &ppi_info,
1031         .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FLDSEL
1032                         | EPPI_CTL_ACTIVE656),
1033 };
1034 #endif
1035
1036 static struct platform_device bfin_capture_device = {
1037         .name = "bfin_capture",
1038         .dev = {
1039                 .platform_data = &bfin_capture_data,
1040         },
1041 };
1042 #endif
1043
1044 #if defined(CONFIG_VIDEO_BLACKFIN_DISPLAY) \
1045         || defined(CONFIG_VIDEO_BLACKFIN_DISPLAY_MODULE)
1046 #include <linux/videodev2.h>
1047 #include <media/blackfin/bfin_display.h>
1048 #include <media/blackfin/ppi.h>
1049
1050 static const unsigned short ppi_req_disp[] = {
1051         P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
1052         P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
1053         P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
1054         P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15,
1055         P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
1056         0,
1057 };
1058
1059 static const struct ppi_info ppi_info = {
1060         .type = PPI_TYPE_EPPI3,
1061         .dma_ch = CH_EPPI0_CH0,
1062         .irq_err = IRQ_EPPI0_STAT,
1063         .base = (void __iomem *)EPPI0_STAT,
1064         .pin_req = ppi_req_disp,
1065 };
1066
1067 #if defined(CONFIG_VIDEO_ADV7511) \
1068         || defined(CONFIG_VIDEO_ADV7511_MODULE)
1069 #include <media/adv7511.h>
1070
1071 static struct v4l2_output adv7511_outputs[] = {
1072         {
1073                 .index = 0,
1074                 .name = "HDMI",
1075                 .type = V4L2_INPUT_TYPE_CAMERA,
1076                 .capabilities = V4L2_OUT_CAP_DV_TIMINGS,
1077         },
1078 };
1079
1080 static struct disp_route adv7511_routes[] = {
1081         {
1082                 .output = 0,
1083         },
1084 };
1085
1086 static struct adv7511_platform_data adv7511_data = {
1087         .edid_addr = 0x7e,
1088         .i2c_ex = 0x25,
1089 };
1090
1091 static struct bfin_display_config bfin_display_data = {
1092         .card_name = "BF609",
1093         .outputs = adv7511_outputs,
1094         .num_outputs = ARRAY_SIZE(adv7511_outputs),
1095         .routes = adv7511_routes,
1096         .i2c_adapter_id = 0,
1097         .board_info = {
1098                 .type = "adv7511",
1099                 .addr = 0x39,
1100                 .platform_data = (void *)&adv7511_data,
1101         },
1102         .ppi_info = &ppi_info,
1103         .ppi_control = (EPPI_CTL_SPLTWRD | PACK_EN | DLEN_16
1104                         | EPPI_CTL_FS1LO_FS2LO | EPPI_CTL_POLC3
1105                         | EPPI_CTL_IFSGEN | EPPI_CTL_SYNC2
1106                         | EPPI_CTL_NON656 | EPPI_CTL_DIR),
1107 };
1108 #endif
1109
1110 #if IS_ENABLED(CONFIG_VIDEO_ADV7343)
1111 #include <media/adv7343.h>
1112
1113 static struct v4l2_output adv7343_outputs[] = {
1114         {
1115                 .index = 0,
1116                 .name = "Composite",
1117                 .type = V4L2_OUTPUT_TYPE_ANALOG,
1118                 .std = V4L2_STD_ALL,
1119                 .capabilities = V4L2_OUT_CAP_STD,
1120         },
1121         {
1122                 .index = 1,
1123                 .name = "S-Video",
1124                 .type = V4L2_OUTPUT_TYPE_ANALOG,
1125                 .std = V4L2_STD_ALL,
1126                 .capabilities = V4L2_OUT_CAP_STD,
1127         },
1128         {
1129                 .index = 2,
1130                 .name = "Component",
1131                 .type = V4L2_OUTPUT_TYPE_ANALOG,
1132                 .std = V4L2_STD_ALL,
1133                 .capabilities = V4L2_OUT_CAP_STD,
1134         },
1135
1136 };
1137
1138 static struct disp_route adv7343_routes[] = {
1139         {
1140                 .output = ADV7343_COMPOSITE_ID,
1141         },
1142         {
1143                 .output = ADV7343_SVIDEO_ID,
1144         },
1145         {
1146                 .output = ADV7343_COMPONENT_ID,
1147         },
1148 };
1149
1150 static struct adv7343_platform_data adv7343_data = {
1151         .mode_config = {
1152                 .sleep_mode = false,
1153                 .pll_control = false,
1154                 .dac_1 = true,
1155                 .dac_2 = true,
1156                 .dac_3 = true,
1157                 .dac_4 = true,
1158                 .dac_5 = true,
1159                 .dac_6 = true,
1160         },
1161         .sd_config = {
1162                 .sd_dac_out1 = false,
1163                 .sd_dac_out2 = false,
1164         },
1165 };
1166
1167 static struct bfin_display_config bfin_display_data = {
1168         .card_name = "BF609",
1169         .outputs = adv7343_outputs,
1170         .num_outputs = ARRAY_SIZE(adv7343_outputs),
1171         .routes = adv7343_routes,
1172         .i2c_adapter_id = 0,
1173         .board_info = {
1174                 .type = "adv7343",
1175                 .addr = 0x2b,
1176                 .platform_data = (void *)&adv7343_data,
1177         },
1178         .ppi_info = &ppi_info_disp,
1179         .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FS1LO_FS2LO
1180                         | EPPI_CTL_POLC3 | EPPI_CTL_BLANKGEN | EPPI_CTL_SYNC2
1181                         | EPPI_CTL_NON656 | EPPI_CTL_DIR),
1182 };
1183 #endif
1184
1185 static struct platform_device bfin_display_device = {
1186         .name = "bfin_display",
1187         .dev = {
1188                 .platform_data = &bfin_display_data,
1189         },
1190 };
1191 #endif
1192
1193 #if defined(CONFIG_BFIN_CRC)
1194 #define BFIN_CRC_NAME "bfin-crc"
1195
1196 static struct resource bfin_crc0_resources[] = {
1197         {
1198                 .start = REG_CRC0_CTL,
1199                 .end = REG_CRC0_REVID+4,
1200                 .flags = IORESOURCE_MEM,
1201         },
1202         {
1203                 .start = IRQ_CRC0_DCNTEXP,
1204                 .end = IRQ_CRC0_DCNTEXP,
1205                 .flags = IORESOURCE_IRQ,
1206         },
1207         {
1208                 .start = CH_MEM_STREAM0_SRC_CRC0,
1209                 .end = CH_MEM_STREAM0_SRC_CRC0,
1210                 .flags = IORESOURCE_DMA,
1211         },
1212         {
1213                 .start = CH_MEM_STREAM0_DEST_CRC0,
1214                 .end = CH_MEM_STREAM0_DEST_CRC0,
1215                 .flags = IORESOURCE_DMA,
1216         },
1217 };
1218
1219 static struct platform_device bfin_crc0_device = {
1220         .name = BFIN_CRC_NAME,
1221         .id = 0,
1222         .num_resources = ARRAY_SIZE(bfin_crc0_resources),
1223         .resource = bfin_crc0_resources,
1224 };
1225
1226 static struct resource bfin_crc1_resources[] = {
1227         {
1228                 .start = REG_CRC1_CTL,
1229                 .end = REG_CRC1_REVID+4,
1230                 .flags = IORESOURCE_MEM,
1231         },
1232         {
1233                 .start = IRQ_CRC1_DCNTEXP,
1234                 .end = IRQ_CRC1_DCNTEXP,
1235                 .flags = IORESOURCE_IRQ,
1236         },
1237         {
1238                 .start = CH_MEM_STREAM1_SRC_CRC1,
1239                 .end = CH_MEM_STREAM1_SRC_CRC1,
1240                 .flags = IORESOURCE_DMA,
1241         },
1242         {
1243                 .start = CH_MEM_STREAM1_DEST_CRC1,
1244                 .end = CH_MEM_STREAM1_DEST_CRC1,
1245                 .flags = IORESOURCE_DMA,
1246         },
1247 };
1248
1249 static struct platform_device bfin_crc1_device = {
1250         .name = BFIN_CRC_NAME,
1251         .id = 1,
1252         .num_resources = ARRAY_SIZE(bfin_crc1_resources),
1253         .resource = bfin_crc1_resources,
1254 };
1255 #endif
1256
1257 #if defined(CONFIG_CRYPTO_DEV_BFIN_CRC)
1258 #define BFIN_CRYPTO_CRC_NAME            "bfin-hmac-crc"
1259 #define BFIN_CRYPTO_CRC_POLY_DATA       0x5c5c5c5c
1260
1261 static struct resource bfin_crypto_crc_resources[] = {
1262         {
1263                 .start = REG_CRC0_CTL,
1264                 .end = REG_CRC0_REVID+4,
1265                 .flags = IORESOURCE_MEM,
1266         },
1267         {
1268                 .start = IRQ_CRC0_DCNTEXP,
1269                 .end = IRQ_CRC0_DCNTEXP,
1270                 .flags = IORESOURCE_IRQ,
1271         },
1272         {
1273                 .start = CH_MEM_STREAM0_SRC_CRC0,
1274                 .end = CH_MEM_STREAM0_SRC_CRC0,
1275                 .flags = IORESOURCE_DMA,
1276         },
1277 };
1278
1279 static struct platform_device bfin_crypto_crc_device = {
1280         .name = BFIN_CRYPTO_CRC_NAME,
1281         .id = 0,
1282         .num_resources = ARRAY_SIZE(bfin_crypto_crc_resources),
1283         .resource = bfin_crypto_crc_resources,
1284         .dev = {
1285                 .platform_data = (void *)BFIN_CRYPTO_CRC_POLY_DATA,
1286         },
1287 };
1288 #endif
1289
1290 #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
1291 static const struct ad7877_platform_data bfin_ad7877_ts_info = {
1292         .model                  = 7877,
1293         .vref_delay_usecs       = 50,   /* internal, no capacitor */
1294         .x_plate_ohms           = 419,
1295         .y_plate_ohms           = 486,
1296         .pressure_max           = 1000,
1297         .pressure_min           = 0,
1298         .stopacq_polarity       = 1,
1299         .first_conversion_delay = 3,
1300         .acquisition_time       = 1,
1301         .averaging              = 1,
1302         .pen_down_acc_interval  = 1,
1303 };
1304 #endif
1305
1306 #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
1307 #include <linux/input.h>
1308 #include <linux/gpio_keys.h>
1309
1310 static struct gpio_keys_button bfin_gpio_keys_table[] = {
1311         {BTN_0, GPIO_PB10, 1, "gpio-keys: BTN0"},
1312         {BTN_1, GPIO_PE1, 1, "gpio-keys: BTN1"},
1313 };
1314
1315 static struct gpio_keys_platform_data bfin_gpio_keys_data = {
1316         .buttons        = bfin_gpio_keys_table,
1317         .nbuttons       = ARRAY_SIZE(bfin_gpio_keys_table),
1318 };
1319
1320 static struct platform_device bfin_device_gpiokeys = {
1321         .name      = "gpio-keys",
1322         .dev = {
1323                 .platform_data = &bfin_gpio_keys_data,
1324         },
1325 };
1326 #endif
1327
1328 static struct spi_board_info bfin_spi_board_info[] __initdata = {
1329 #if defined(CONFIG_MTD_M25P80) \
1330         || defined(CONFIG_MTD_M25P80_MODULE)
1331         {
1332                 /* the modalias must be the same as spi device driver name */
1333                 .modalias = "m25p80", /* Name of spi_driver for this device */
1334                 .max_speed_hz = 25000000,     /* max spi clock (SCK) speed in HZ */
1335                 .bus_num = 0, /* Framework bus number */
1336                 .chip_select = 1, /* SPI_SSEL1*/
1337                 .platform_data = &bfin_spi_flash_data,
1338                 .controller_data = &spi_flash_chip_info,
1339                 .mode = SPI_MODE_3,
1340         },
1341 #endif
1342 #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
1343         {
1344                 .modalias               = "ad7877",
1345                 .platform_data          = &bfin_ad7877_ts_info,
1346                 .irq                    = IRQ_PD9,
1347                 .max_speed_hz           = 12500000,     /* max spi clock (SCK) speed in HZ */
1348                 .bus_num                = 0,
1349                 .chip_select            = 4,
1350         },
1351 #endif
1352 #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
1353         {
1354                 .modalias = "spidev",
1355                 .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
1356                 .bus_num = 0,
1357                 .chip_select = 1,
1358                 .controller_data = &spidev_chip_info,
1359         },
1360 #endif
1361 #if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE)
1362         {
1363                 .modalias               = "adxl34x",
1364                 .platform_data          = &adxl34x_info,
1365                 .irq                    = IRQ_PC5,
1366                 .max_speed_hz           = 5000000,     /* max spi clock (SCK) speed in HZ */
1367                 .bus_num                = 1,
1368                 .chip_select            = 2,
1369                 .mode = SPI_MODE_3,
1370         },
1371 #endif
1372 };
1373 #if IS_ENABLED(CONFIG_SPI_BFIN_V3)
1374 /* SPI (0) */
1375 static struct resource bfin_spi0_resource[] = {
1376         {
1377                 .start = SPI0_REGBASE,
1378                 .end   = SPI0_REGBASE + 0xFF,
1379                 .flags = IORESOURCE_MEM,
1380         },
1381         {
1382                 .start = CH_SPI0_TX,
1383                 .end   = CH_SPI0_TX,
1384                 .flags = IORESOURCE_DMA,
1385         },
1386         {
1387                 .start = CH_SPI0_RX,
1388                 .end   = CH_SPI0_RX,
1389                 .flags = IORESOURCE_DMA,
1390         },
1391 };
1392
1393 /* SPI (1) */
1394 static struct resource bfin_spi1_resource[] = {
1395         {
1396                 .start = SPI1_REGBASE,
1397                 .end   = SPI1_REGBASE + 0xFF,
1398                 .flags = IORESOURCE_MEM,
1399         },
1400         {
1401                 .start = CH_SPI1_TX,
1402                 .end   = CH_SPI1_TX,
1403                 .flags = IORESOURCE_DMA,
1404         },
1405         {
1406                 .start = CH_SPI1_RX,
1407                 .end   = CH_SPI1_RX,
1408                 .flags = IORESOURCE_DMA,
1409         },
1410
1411 };
1412
1413 /* SPI controller data */
1414 static struct bfin_spi3_master bf60x_spi_master_info0 = {
1415         .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
1416         .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
1417 };
1418
1419 static struct platform_device bf60x_spi_master0 = {
1420         .name = "bfin-spi3",
1421         .id = 0, /* Bus number */
1422         .num_resources = ARRAY_SIZE(bfin_spi0_resource),
1423         .resource = bfin_spi0_resource,
1424         .dev = {
1425                 .platform_data = &bf60x_spi_master_info0, /* Passed to driver */
1426         },
1427 };
1428
1429 static struct bfin_spi3_master bf60x_spi_master_info1 = {
1430         .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
1431         .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
1432 };
1433
1434 static struct platform_device bf60x_spi_master1 = {
1435         .name = "bfin-spi3",
1436         .id = 1, /* Bus number */
1437         .num_resources = ARRAY_SIZE(bfin_spi1_resource),
1438         .resource = bfin_spi1_resource,
1439         .dev = {
1440                 .platform_data = &bf60x_spi_master_info1, /* Passed to driver */
1441         },
1442 };
1443 #endif  /* spi master and devices */
1444
1445 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
1446 static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
1447
1448 static struct resource bfin_twi0_resource[] = {
1449         [0] = {
1450                 .start = TWI0_CLKDIV,
1451                 .end   = TWI0_CLKDIV + 0xFF,
1452                 .flags = IORESOURCE_MEM,
1453         },
1454         [1] = {
1455                 .start = IRQ_TWI0,
1456                 .end   = IRQ_TWI0,
1457                 .flags = IORESOURCE_IRQ,
1458         },
1459 };
1460
1461 static struct platform_device i2c_bfin_twi0_device = {
1462         .name = "i2c-bfin-twi",
1463         .id = 0,
1464         .num_resources = ARRAY_SIZE(bfin_twi0_resource),
1465         .resource = bfin_twi0_resource,
1466         .dev = {
1467                 .platform_data = &bfin_twi0_pins,
1468         },
1469 };
1470
1471 static const u16 bfin_twi1_pins[] = {P_TWI1_SCL, P_TWI1_SDA, 0};
1472
1473 static struct resource bfin_twi1_resource[] = {
1474         [0] = {
1475                 .start = TWI1_CLKDIV,
1476                 .end   = TWI1_CLKDIV + 0xFF,
1477                 .flags = IORESOURCE_MEM,
1478         },
1479         [1] = {
1480                 .start = IRQ_TWI1,
1481                 .end   = IRQ_TWI1,
1482                 .flags = IORESOURCE_IRQ,
1483         },
1484 };
1485
1486 static struct platform_device i2c_bfin_twi1_device = {
1487         .name = "i2c-bfin-twi",
1488         .id = 1,
1489         .num_resources = ARRAY_SIZE(bfin_twi1_resource),
1490         .resource = bfin_twi1_resource,
1491         .dev = {
1492                 .platform_data = &bfin_twi1_pins,
1493         },
1494 };
1495 #endif
1496
1497 static struct i2c_board_info __initdata bfin_i2c_board_info0[] = {
1498 #if defined(CONFIG_INPUT_ADXL34X_I2C) || defined(CONFIG_INPUT_ADXL34X_I2C_MODULE)
1499         {
1500                 I2C_BOARD_INFO("adxl34x", 0x53),
1501                 .irq = IRQ_PC5,
1502                 .platform_data = (void *)&adxl34x_info,
1503         },
1504 #endif
1505 #if defined(CONFIG_SND_SOC_ADAU1761) || defined(CONFIG_SND_SOC_ADAU1761_MODULE)
1506         {
1507                 I2C_BOARD_INFO("adau1761", 0x38),
1508                 .platform_data = (void *)&adau1761_info
1509         },
1510 #endif
1511 #if defined(CONFIG_SND_SOC_SSM2602) || defined(CONFIG_SND_SOC_SSM2602_MODULE)
1512         {
1513                 I2C_BOARD_INFO("ssm2602", 0x1b),
1514         },
1515 #endif
1516 };
1517
1518 static struct i2c_board_info __initdata bfin_i2c_board_info1[] = {
1519 };
1520
1521 static const unsigned int cclk_vlev_datasheet[] =
1522 {
1523 /*
1524  * Internal VLEV BF54XSBBC1533
1525  ****temporarily using these values until data sheet is updated
1526  */
1527         VRPAIR(VLEV_085, 150000000),
1528         VRPAIR(VLEV_090, 250000000),
1529         VRPAIR(VLEV_110, 276000000),
1530         VRPAIR(VLEV_115, 301000000),
1531         VRPAIR(VLEV_120, 525000000),
1532         VRPAIR(VLEV_125, 550000000),
1533         VRPAIR(VLEV_130, 600000000),
1534 };
1535
1536 static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
1537         .tuple_tab = cclk_vlev_datasheet,
1538         .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
1539         .vr_settling_time = 25 /* us */,
1540 };
1541
1542 static struct platform_device bfin_dpmc = {
1543         .name = "bfin dpmc",
1544         .dev = {
1545                 .platform_data = &bfin_dmpc_vreg_data,
1546         },
1547 };
1548
1549 static struct platform_device *ezkit_devices[] __initdata = {
1550
1551         &bfin_dpmc,
1552
1553 #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
1554         &rtc_device,
1555 #endif
1556
1557 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
1558 #ifdef CONFIG_SERIAL_BFIN_UART0
1559         &bfin_uart0_device,
1560 #endif
1561 #ifdef CONFIG_SERIAL_BFIN_UART1
1562         &bfin_uart1_device,
1563 #endif
1564 #endif
1565
1566 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
1567 #ifdef CONFIG_BFIN_SIR0
1568         &bfin_sir0_device,
1569 #endif
1570 #ifdef CONFIG_BFIN_SIR1
1571         &bfin_sir1_device,
1572 #endif
1573 #endif
1574
1575 #if defined(CONFIG_STMMAC_ETH) || defined(CONFIG_STMMAC_ETH_MODULE)
1576         &bfin_eth_device,
1577 #endif
1578
1579 #if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
1580         &musb_device,
1581 #endif
1582
1583 #if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
1584         &bfin_isp1760_device,
1585 #endif
1586
1587 #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
1588 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
1589         &bfin_sport0_uart_device,
1590 #endif
1591 #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
1592         &bfin_sport1_uart_device,
1593 #endif
1594 #ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
1595         &bfin_sport2_uart_device,
1596 #endif
1597 #endif
1598
1599 #if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
1600         &bfin_can0_device,
1601 #endif
1602
1603 #if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
1604         &bfin_nand_device,
1605 #endif
1606
1607 #if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
1608         &bfin_sdh_device,
1609 #endif
1610
1611 #if IS_ENABLED(CONFIG_SPI_BFIN_V3)
1612         &bf60x_spi_master0,
1613         &bf60x_spi_master1,
1614 #endif
1615
1616 #if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE)
1617         &bfin_rotary_device,
1618 #endif
1619
1620 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
1621         &i2c_bfin_twi0_device,
1622 #if !defined(CONFIG_BF542)
1623         &i2c_bfin_twi1_device,
1624 #endif
1625 #endif
1626
1627 #if defined(CONFIG_BFIN_CRC)
1628         &bfin_crc0_device,
1629         &bfin_crc1_device,
1630 #endif
1631 #if defined(CONFIG_CRYPTO_DEV_BFIN_CRC)
1632         &bfin_crypto_crc_device,
1633 #endif
1634
1635 #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
1636         &bfin_device_gpiokeys,
1637 #endif
1638
1639 #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
1640         &ezkit_flash_device,
1641 #endif
1642 #if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
1643         &bfin_i2s_pcm,
1644 #endif
1645 #if defined(CONFIG_SND_BF6XX_SOC_I2S) || \
1646         defined(CONFIG_SND_BF6XX_SOC_I2S_MODULE)
1647         &bfin_i2s,
1648 #endif
1649 #if defined(CONFIG_SND_BF5XX_SOC_AD1836) || \
1650         defined(CONFIG_SND_BF5XX_SOC_AD1836_MODULE)
1651         &bfin_ad1836_machine,
1652 #endif
1653 #if defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61) || \
1654         defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61_MODULE)
1655         &adau1761_device,
1656 #endif
1657 #if defined(CONFIG_VIDEO_BLACKFIN_CAPTURE) \
1658         || defined(CONFIG_VIDEO_BLACKFIN_CAPTURE_MODULE)
1659         &bfin_capture_device,
1660 #endif
1661 #if defined(CONFIG_VIDEO_BLACKFIN_DISPLAY) \
1662         || defined(CONFIG_VIDEO_BLACKFIN_DISPLAY_MODULE)
1663         &bfin_display_device,
1664 #endif
1665
1666 };
1667
1668 static int __init ezkit_init(void)
1669 {
1670         printk(KERN_INFO "%s(): registering device resources\n", __func__);
1671
1672         i2c_register_board_info(0, bfin_i2c_board_info0,
1673                                 ARRAY_SIZE(bfin_i2c_board_info0));
1674         i2c_register_board_info(1, bfin_i2c_board_info1,
1675                                 ARRAY_SIZE(bfin_i2c_board_info1));
1676
1677 #if defined(CONFIG_STMMAC_ETH) || defined(CONFIG_STMMAC_ETH_MODULE)
1678         if (!peripheral_request_list(pins, "emac0"))
1679                 printk(KERN_ERR "%s(): request emac pins failed\n", __func__);
1680 #endif
1681
1682         platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices));
1683
1684         spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
1685
1686         return 0;
1687 }
1688
1689 arch_initcall(ezkit_init);
1690
1691 static struct platform_device *ezkit_early_devices[] __initdata = {
1692 #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
1693 #ifdef CONFIG_SERIAL_BFIN_UART0
1694         &bfin_uart0_device,
1695 #endif
1696 #ifdef CONFIG_SERIAL_BFIN_UART1
1697         &bfin_uart1_device,
1698 #endif
1699 #endif
1700
1701 #if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
1702 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
1703         &bfin_sport0_uart_device,
1704 #endif
1705 #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
1706         &bfin_sport1_uart_device,
1707 #endif
1708 #ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
1709         &bfin_sport2_uart_device,
1710 #endif
1711 #endif
1712 };
1713
1714 void __init native_machine_early_platform_add_devices(void)
1715 {
1716         printk(KERN_INFO "register early platform devices\n");
1717         early_platform_add_devices(ezkit_early_devices,
1718                 ARRAY_SIZE(ezkit_early_devices));
1719 }