arch/arm/mach-shmobile/setup-r8a7790.c

   1 /*
   2  * r8a7790 processor support
   3  *
   4  * Copyright (C) 2013  Renesas Solutions Corp.
   5  * Copyright (C) 2013  Magnus Damm
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  */
  20
  21 #include <linux/irq.h>
  22 #include <linux/kernel.h>
  23 #include <linux/of_platform.h>
  24 #include <linux/platform_data/gpio-rcar.h>
  25 #include <linux/platform_data/irq-renesas-irqc.h>
  26 #include <linux/serial_sci.h>
  27 #include <linux/sh_dma.h>
  28 #include <linux/sh_timer.h>
  29 #include <mach/common.h>
  30 #include <mach/dma-register.h>
  31 #include <mach/irqs.h>
  32 #include <mach/r8a7790.h>
  33 #include <asm/mach/arch.h>
  34
  35 /* Audio-DMAC */
  36 #define AUDIO_DMAC_SLAVE(_id, _addr, t, r)                      \
  37 {                                                               \
  38         .slave_id       = AUDIO_DMAC_SLAVE_## _id ##_TX,        \
  39         .addr           = _addr + 0x8,                          \
  40         .chcr           = CHCR_TX(XMIT_SZ_32BIT),               \
  41         .mid_rid        = t,                                    \
  42 }, {                                                            \
  43         .slave_id       = AUDIO_DMAC_SLAVE_## _id ##_RX,        \
  44         .addr           = _addr + 0xc,                          \
  45         .chcr           = CHCR_RX(XMIT_SZ_32BIT),               \
  46         .mid_rid        = r,                                    \
  47 }
  48
  49 static const struct sh_dmae_slave_config r8a7790_audio_dmac_slaves[] = {
  50         AUDIO_DMAC_SLAVE(SSI0, 0xec241000, 0x01, 0x02),
  51         AUDIO_DMAC_SLAVE(SSI1, 0xec241040, 0x03, 0x04),
  52         AUDIO_DMAC_SLAVE(SSI2, 0xec241080, 0x05, 0x06),
  53         AUDIO_DMAC_SLAVE(SSI3, 0xec2410c0, 0x07, 0x08),
  54         AUDIO_DMAC_SLAVE(SSI4, 0xec241100, 0x09, 0x0a),
  55         AUDIO_DMAC_SLAVE(SSI5, 0xec241140, 0x0b, 0x0c),
  56         AUDIO_DMAC_SLAVE(SSI6, 0xec241180, 0x0d, 0x0e),
  57         AUDIO_DMAC_SLAVE(SSI7, 0xec2411c0, 0x0f, 0x10),
  58         AUDIO_DMAC_SLAVE(SSI8, 0xec241200, 0x11, 0x12),
  59         AUDIO_DMAC_SLAVE(SSI9, 0xec241240, 0x13, 0x14),
  60 };
  61
  62 #define DMAE_CHANNEL(a, b)                      \
  63 {                                               \
  64         .offset         = (a) - 0x20,           \
  65         .dmars          = (a) - 0x20 + 0x40,    \
  66         .chclr_bit      = (b),                  \
  67         .chclr_offset   = 0x80 - 0x20,          \
  68 }
  69
  70 static const struct sh_dmae_channel r8a7790_audio_dmac_channels[] = {
  71         DMAE_CHANNEL(0x8000, 0),
  72         DMAE_CHANNEL(0x8080, 1),
  73         DMAE_CHANNEL(0x8100, 2),
  74         DMAE_CHANNEL(0x8180, 3),
  75         DMAE_CHANNEL(0x8200, 4),
  76         DMAE_CHANNEL(0x8280, 5),
  77         DMAE_CHANNEL(0x8300, 6),
  78         DMAE_CHANNEL(0x8380, 7),
  79         DMAE_CHANNEL(0x8400, 8),
  80         DMAE_CHANNEL(0x8480, 9),
  81         DMAE_CHANNEL(0x8500, 10),
  82         DMAE_CHANNEL(0x8580, 11),
  83         DMAE_CHANNEL(0x8600, 12),
  84 };
  85
  86 static struct sh_dmae_pdata r8a7790_audio_dmac_platform_data = {
  87         .slave          = r8a7790_audio_dmac_slaves,
  88         .slave_num      = ARRAY_SIZE(r8a7790_audio_dmac_slaves),
  89         .channel        = r8a7790_audio_dmac_channels,
  90         .channel_num    = ARRAY_SIZE(r8a7790_audio_dmac_channels),
  91         .ts_low_shift   = TS_LOW_SHIFT,
  92         .ts_low_mask    = TS_LOW_BIT << TS_LOW_SHIFT,
  93         .ts_high_shift  = TS_HI_SHIFT,
  94         .ts_high_mask   = TS_HI_BIT << TS_HI_SHIFT,
  95         .ts_shift       = dma_ts_shift,
  96         .ts_shift_num   = ARRAY_SIZE(dma_ts_shift),
  97         .dmaor_init     = DMAOR_DME,
  98         .chclr_present  = 1,
  99         .chclr_bitwise  = 1,
 100 };
 101
 102 static struct resource r8a7790_audio_dmac_resources[] = {
 103         /* Channel registers and DMAOR for low */
 104         DEFINE_RES_MEM(0xec700020, 0x8663 - 0x20),
 105         DEFINE_RES_IRQ(gic_spi(346)),
 106         DEFINE_RES_NAMED(gic_spi(320), 13, NULL, IORESOURCE_IRQ),
 107
 108         /* Channel registers and DMAOR for hi */
 109         DEFINE_RES_MEM(0xec720020, 0x8663 - 0x20), /* hi */
 110         DEFINE_RES_IRQ(gic_spi(347)),
 111         DEFINE_RES_NAMED(gic_spi(333), 13, NULL, IORESOURCE_IRQ),
 112 };
 113
 114 #define r8a7790_register_audio_dmac(id)                         \
 115         platform_device_register_resndata(                      \
 116                 &platform_bus, "sh-dma-engine", id,             \
 117                 &r8a7790_audio_dmac_resources[id * 3],  3,      \
 118                 &r8a7790_audio_dmac_platform_data,              \
 119                 sizeof(r8a7790_audio_dmac_platform_data))
 120
 121 static const struct resource pfc_resources[] __initconst = {
 122         DEFINE_RES_MEM(0xe6060000, 0x250),
 123 };
 124
 125 #define r8a7790_register_pfc()                                          \
 126         platform_device_register_simple("pfc-r8a7790", -1, pfc_resources, \
 127                                         ARRAY_SIZE(pfc_resources))
 128
 129 #define R8A7790_GPIO(idx)                                               \
 130 static const struct resource r8a7790_gpio##idx##_resources[] __initconst = { \
 131         DEFINE_RES_MEM(0xe6050000 + 0x1000 * (idx), 0x50),              \
 132         DEFINE_RES_IRQ(gic_spi(4 + (idx))),                             \
 133 };                                                                      \
 134                                                                         \
 135 static const struct gpio_rcar_config                                    \
 136 r8a7790_gpio##idx##_platform_data __initconst = {                       \
 137         .gpio_base      = 32 * (idx),                                   \
 138         .irq_base       = 0,                                            \
 139         .number_of_pins = 32,                                           \
 140         .pctl_name      = "pfc-r8a7790",                                \
 141         .has_both_edge_trigger = 1,                                     \
 142 };                                                                      \
 143
 144 R8A7790_GPIO(0);
 145 R8A7790_GPIO(1);
 146 R8A7790_GPIO(2);
 147 R8A7790_GPIO(3);
 148 R8A7790_GPIO(4);
 149 R8A7790_GPIO(5);
 150
 151 #define r8a7790_register_gpio(idx)                                      \
 152         platform_device_register_resndata(&platform_bus, "gpio_rcar", idx, \
 153                 r8a7790_gpio##idx##_resources,                          \
 154                 ARRAY_SIZE(r8a7790_gpio##idx##_resources),              \
 155                 &r8a7790_gpio##idx##_platform_data,                     \
 156                 sizeof(r8a7790_gpio##idx##_platform_data))
 157
 158 static struct resource i2c_resources[] __initdata = {
 159         /* I2C0 */
 160         DEFINE_RES_MEM(0xE6508000, 0x40),
 161         DEFINE_RES_IRQ(gic_spi(287)),
 162         /* I2C1 */
 163         DEFINE_RES_MEM(0xE6518000, 0x40),
 164         DEFINE_RES_IRQ(gic_spi(288)),
 165         /* I2C2 */
 166         DEFINE_RES_MEM(0xE6530000, 0x40),
 167         DEFINE_RES_IRQ(gic_spi(286)),
 168         /* I2C3 */
 169         DEFINE_RES_MEM(0xE6540000, 0x40),
 170         DEFINE_RES_IRQ(gic_spi(290)),
 171
 172 };
 173
 174 #define r8a7790_register_i2c(idx)               \
 175         platform_device_register_simple(        \
 176                 "i2c-rcar_gen2", idx,           \
 177                 i2c_resources + (2 * idx), 2);  \
 178
 179 void __init r8a7790_pinmux_init(void)
 180 {
 181         r8a7790_register_pfc();
 182         r8a7790_register_gpio(0);
 183         r8a7790_register_gpio(1);
 184         r8a7790_register_gpio(2);
 185         r8a7790_register_gpio(3);
 186         r8a7790_register_gpio(4);
 187         r8a7790_register_gpio(5);
 188         r8a7790_register_i2c(0);
 189         r8a7790_register_i2c(1);
 190         r8a7790_register_i2c(2);
 191         r8a7790_register_i2c(3);
 192         r8a7790_register_audio_dmac(0);
 193         r8a7790_register_audio_dmac(1);
 194 }
 195
 196 #define __R8A7790_SCIF(scif_type, _scscr, index, baseaddr, irq)         \
 197 static struct plat_sci_port scif##index##_platform_data = {             \
 198         .type           = scif_type,                                    \
 199         .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,              \
 200         .scscr          = _scscr,                                       \
 201 };                                                                      \
 202                                                                         \
 203 static struct resource scif##index##_resources[] = {                    \
 204         DEFINE_RES_MEM(baseaddr, 0x100),                                \
 205         DEFINE_RES_IRQ(irq),                                            \
 206 }
 207
 208 #define R8A7790_SCIF(index, baseaddr, irq)                              \
 209         __R8A7790_SCIF(PORT_SCIF, SCSCR_RE | SCSCR_TE,                  \
 210                        index, baseaddr, irq)
 211
 212 #define R8A7790_SCIFA(index, baseaddr, irq)                             \
 213         __R8A7790_SCIF(PORT_SCIFA, SCSCR_RE | SCSCR_TE | SCSCR_CKE0,    \
 214                        index, baseaddr, irq)
 215
 216 #define R8A7790_SCIFB(index, baseaddr, irq)                             \
 217         __R8A7790_SCIF(PORT_SCIFB, SCSCR_RE | SCSCR_TE,                 \
 218                        index, baseaddr, irq)
 219
 220 #define R8A7790_HSCIF(index, baseaddr, irq)                             \
 221         __R8A7790_SCIF(PORT_HSCIF, SCSCR_RE | SCSCR_TE,                 \
 222                        index, baseaddr, irq)
 223
 224 R8A7790_SCIFA(0, 0xe6c40000, gic_spi(144)); /* SCIFA0 */
 225 R8A7790_SCIFA(1, 0xe6c50000, gic_spi(145)); /* SCIFA1 */
 226 R8A7790_SCIFB(2, 0xe6c20000, gic_spi(148)); /* SCIFB0 */
 227 R8A7790_SCIFB(3, 0xe6c30000, gic_spi(149)); /* SCIFB1 */
 228 R8A7790_SCIFB(4, 0xe6ce0000, gic_spi(150)); /* SCIFB2 */
 229 R8A7790_SCIFA(5, 0xe6c60000, gic_spi(151)); /* SCIFA2 */
 230 R8A7790_SCIF(6,  0xe6e60000, gic_spi(152)); /* SCIF0 */
 231 R8A7790_SCIF(7,  0xe6e68000, gic_spi(153)); /* SCIF1 */
 232 R8A7790_HSCIF(8, 0xe62c0000, gic_spi(154)); /* HSCIF0 */
 233 R8A7790_HSCIF(9, 0xe62c8000, gic_spi(155)); /* HSCIF1 */
 234
 235 #define r8a7790_register_scif(index)                                           \
 236         platform_device_register_resndata(&platform_bus, "sh-sci", index,      \
 237                                           scif##index##_resources,             \
 238                                           ARRAY_SIZE(scif##index##_resources), \
 239                                           &scif##index##_platform_data,        \
 240                                           sizeof(scif##index##_platform_data))
 241
 242 static const struct renesas_irqc_config irqc0_data __initconst = {
 243         .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
 244 };
 245
 246 static const struct resource irqc0_resources[] __initconst = {
 247         DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
 248         DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
 249         DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
 250         DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
 251         DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
 252 };
 253
 254 #define r8a7790_register_irqc(idx)                                      \
 255         platform_device_register_resndata(&platform_bus, "renesas_irqc", \
 256                                           idx, irqc##idx##_resources,   \
 257                                           ARRAY_SIZE(irqc##idx##_resources), \
 258                                           &irqc##idx##_data,            \
 259                                           sizeof(struct renesas_irqc_config))
 260
 261 static const struct resource thermal_resources[] __initconst = {
 262         DEFINE_RES_MEM(0xe61f0000, 0x14),
 263         DEFINE_RES_MEM(0xe61f0100, 0x38),
 264         DEFINE_RES_IRQ(gic_spi(69)),
 265 };
 266
 267 #define r8a7790_register_thermal()                                      \
 268         platform_device_register_simple("rcar_thermal", -1,             \
 269                                         thermal_resources,              \
 270                                         ARRAY_SIZE(thermal_resources))
 271
 272 static const struct sh_timer_config cmt00_platform_data __initconst = {
 273         .name = "CMT00",
 274         .timer_bit = 0,
 275         .clockevent_rating = 80,
 276 };
 277
 278 static const struct resource cmt00_resources[] __initconst = {
 279         DEFINE_RES_MEM(0xffca0510, 0x0c),
 280         DEFINE_RES_MEM(0xffca0500, 0x04),
 281         DEFINE_RES_IRQ(gic_spi(142)), /* CMT0_0 */
 282 };
 283
 284 #define r8a7790_register_cmt(idx)                                       \
 285         platform_device_register_resndata(&platform_bus, "sh_cmt",      \
 286                                           idx, cmt##idx##_resources,    \
 287                                           ARRAY_SIZE(cmt##idx##_resources), \
 288                                           &cmt##idx##_platform_data,    \
 289                                           sizeof(struct sh_timer_config))
 290
 291 void __init r8a7790_add_dt_devices(void)
 292 {
 293         r8a7790_register_scif(0);
 294         r8a7790_register_scif(1);
 295         r8a7790_register_scif(2);
 296         r8a7790_register_scif(3);
 297         r8a7790_register_scif(4);
 298         r8a7790_register_scif(5);
 299         r8a7790_register_scif(6);
 300         r8a7790_register_scif(7);
 301         r8a7790_register_scif(8);
 302         r8a7790_register_scif(9);
 303         r8a7790_register_cmt(00);
 304 }
 305
 306 void __init r8a7790_add_standard_devices(void)
 307 {
 308         r8a7790_add_dt_devices();
 309         r8a7790_register_irqc(0);
 310         r8a7790_register_thermal();
 311 }
 312
 313 void __init r8a7790_init_early(void)
 314 {
 315 #ifndef CONFIG_ARM_ARCH_TIMER
 316         shmobile_setup_delay(1300, 2, 4); /* Cortex-A15 @ 1300MHz */
 317 #endif
 318 }
 319
 320 #ifdef CONFIG_USE_OF
 321
 322 static const char * const r8a7790_boards_compat_dt[] __initconst = {
 323         "renesas,r8a7790",
 324         NULL,
 325 };
 326
 327 DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)")
 328         .smp            = smp_ops(r8a7790_smp_ops),
 329         .init_early     = r8a7790_init_early,
 330         .init_time      = rcar_gen2_timer_init,
 331         .dt_compat      = r8a7790_boards_compat_dt,
 332 MACHINE_END
 333 #endif /* CONFIG_USE_OF */