arch/arm/mach-omap2/cpuidle44xx.c

   1 /*
   2  * OMAP4 CPU idle Routines
   3  *
   4  * Copyright (C) 2011 Texas Instruments, Inc.
   5  * Santosh Shilimkar <santosh.shilimkar@ti.com>
   6  * Rajendra Nayak <rnayak@ti.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/sched.h>
  14 #include <linux/cpuidle.h>
  15 #include <linux/cpu_pm.h>
  16 #include <linux/export.h>
  17 #include <linux/clockchips.h>
  18
  19 #include <asm/proc-fns.h>
  20
  21 #include "common.h"
  22 #include "pm.h"
  23 #include "prm.h"
  24
  25 #ifdef CONFIG_CPU_IDLE
  26
  27 /* Machine specific information */
  28 struct omap4_idle_statedata {
  29         u32 cpu_state;
  30         u32 mpu_logic_state;
  31         u32 mpu_state;
  32 };
  33
  34 static struct omap4_idle_statedata omap4_idle_data[] = {
  35         {
  36                 .cpu_state = PWRDM_POWER_ON,
  37                 .mpu_state = PWRDM_POWER_ON,
  38                 .mpu_logic_state = PWRDM_POWER_RET,
  39         },
  40         {
  41                 .cpu_state = PWRDM_POWER_OFF,
  42                 .mpu_state = PWRDM_POWER_RET,
  43                 .mpu_logic_state = PWRDM_POWER_RET,
  44         },
  45         {
  46                 .cpu_state = PWRDM_POWER_OFF,
  47                 .mpu_state = PWRDM_POWER_RET,
  48                 .mpu_logic_state = PWRDM_POWER_OFF,
  49         },
  50 };
  51
  52 static struct powerdomain *mpu_pd, *cpu0_pd, *cpu1_pd;
  53
  54 /**
  55  * omap4_enter_idle - Programs OMAP4 to enter the specified state
  56  * @dev: cpuidle device
  57  * @drv: cpuidle driver
  58  * @index: the index of state to be entered
  59  *
  60  * Called from the CPUidle framework to program the device to the
  61  * specified low power state selected by the governor.
  62  * Returns the amount of time spent in the low power state.
  63  */
  64 static int omap4_enter_idle(struct cpuidle_device *dev,
  65                         struct cpuidle_driver *drv,
  66                         int index)
  67 {
  68         struct omap4_idle_statedata *cx = &omap4_idle_data[index];
  69         u32 cpu1_state;
  70         int cpu_id = smp_processor_id();
  71
  72         local_fiq_disable();
  73
  74         /*
  75          * CPU0 has to stay ON (i.e in C1) until CPU1 is OFF state.
  76          * This is necessary to honour hardware recommondation
  77          * of triggeing all the possible low power modes once CPU1 is
  78          * out of coherency and in OFF mode.
  79          * Update dev->last_state so that governor stats reflects right
  80          * data.
  81          */
  82         cpu1_state = pwrdm_read_pwrst(cpu1_pd);
  83         if (cpu1_state != PWRDM_POWER_OFF) {
  84                 index = drv->safe_state_index;
  85                 cx = &omap4_idle_data[index];
  86         }
  87
  88         if (index > 0)
  89                 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu_id);
  90
  91         /*
  92          * Call idle CPU PM enter notifier chain so that
  93          * VFP and per CPU interrupt context is saved.
  94          */
  95         if (cx->cpu_state == PWRDM_POWER_OFF)
  96                 cpu_pm_enter();
  97
  98         pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state);
  99         omap_set_pwrdm_state(mpu_pd, cx->mpu_state);
 100
 101         /*
 102          * Call idle CPU cluster PM enter notifier chain
 103          * to save GIC and wakeupgen context.
 104          */
 105         if ((cx->mpu_state == PWRDM_POWER_RET) &&
 106                 (cx->mpu_logic_state == PWRDM_POWER_OFF))
 107                         cpu_cluster_pm_enter();
 108
 109         omap4_enter_lowpower(dev->cpu, cx->cpu_state);
 110
 111         /*
 112          * Call idle CPU PM exit notifier chain to restore
 113          * VFP and per CPU IRQ context. Only CPU0 state is
 114          * considered since CPU1 is managed by CPU hotplug.
 115          */
 116         if (pwrdm_read_prev_pwrst(cpu0_pd) == PWRDM_POWER_OFF)
 117                 cpu_pm_exit();
 118
 119         /*
 120          * Call idle CPU cluster PM exit notifier chain
 121          * to restore GIC and wakeupgen context.
 122          */
 123         if (omap4_mpuss_read_prev_context_state())
 124                 cpu_cluster_pm_exit();
 125
 126         if (index > 0)
 127                 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu_id);
 128
 129         local_fiq_enable();
 130
 131         return index;
 132 }
 133
 134 DEFINE_PER_CPU(struct cpuidle_device, omap4_idle_dev);
 135
 136 struct cpuidle_driver omap4_idle_driver = {
 137         .name                           = "omap4_idle",
 138         .owner                          = THIS_MODULE,
 139         .en_core_tk_irqen               = 1,
 140         .states = {
 141                 {
 142                         /* C1 - CPU0 ON + CPU1 ON + MPU ON */
 143                         .exit_latency = 2 + 2,
 144                         .target_residency = 5,
 145                         .flags = CPUIDLE_FLAG_TIME_VALID,
 146                         .enter = omap4_enter_idle,
 147                         .name = "C1",
 148                         .desc = "MPUSS ON"
 149                 },
 150                 {
 151                         /* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
 152                         .exit_latency = 328 + 440,
 153                         .target_residency = 960,
 154                         .flags = CPUIDLE_FLAG_TIME_VALID,
 155                         .enter = omap4_enter_idle,
 156                         .name = "C2",
 157                         .desc = "MPUSS CSWR",
 158                 },
 159                 {
 160                         /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
 161                         .exit_latency = 460 + 518,
 162                         .target_residency = 1100,
 163                         .flags = CPUIDLE_FLAG_TIME_VALID,
 164                         .enter = omap4_enter_idle,
 165                         .name = "C3",
 166                         .desc = "MPUSS OSWR",
 167                 },
 168         },
 169         .state_count = ARRAY_SIZE(omap4_idle_data),
 170         .safe_state_index = 0,
 171 };
 172
 173 /**
 174  * omap4_idle_init - Init routine for OMAP4 idle
 175  *
 176  * Registers the OMAP4 specific cpuidle driver to the cpuidle
 177  * framework with the valid set of states.
 178  */
 179 int __init omap4_idle_init(void)
 180 {
 181         struct cpuidle_device *dev;
 182         unsigned int cpu_id = 0;
 183
 184         mpu_pd = pwrdm_lookup("mpu_pwrdm");
 185         cpu0_pd = pwrdm_lookup("cpu0_pwrdm");
 186         cpu1_pd = pwrdm_lookup("cpu1_pwrdm");
 187         if ((!mpu_pd) || (!cpu0_pd) || (!cpu1_pd))
 188                 return -ENODEV;
 189
 190         dev = &per_cpu(omap4_idle_dev, cpu_id);
 191         dev->cpu = cpu_id;
 192
 193         cpuidle_register_driver(&omap4_idle_driver);
 194
 195         if (cpuidle_register_device(dev)) {
 196                 pr_err("%s: CPUidle register device failed\n", __func__);
 197                 return -EIO;
 198         }
 199
 200         return 0;
 201 }
 202 #else
 203 int __init omap4_idle_init(void)
 204 {
 205         return 0;
 206 }
 207 #endif /* CONFIG_CPU_IDLE */