arch/arm/mach-omap2/cclock3xxx_data.c

   1 /*
   2  * OMAP3 clock data
   3  *
   4  * Copyright (C) 2007-2012 Texas Instruments, Inc.
   5  * Copyright (C) 2007-2011 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  * Updated to COMMON clk data format by Rajendra Nayak <rnayak@ti.com>
   9  * With many device clock fixes by Kevin Hilman and Jouni Högander
  10  * DPLL bypass clock support added by Roman Tereshonkov
  11  *
  12  */
  13
  14 /*
  15  * Virtual clocks are introduced as convenient tools.
  16  * They are sources for other clocks and not supposed
  17  * to be requested from drivers directly.
  18  */
  19
  20 #include <linux/kernel.h>
  21 #include <linux/clk.h>
  22 #include <linux/clk-private.h>
  23 #include <linux/list.h>
  24 #include <linux/io.h>
  25
  26 #include "soc.h"
  27 #include "iomap.h"
  28 #include "clock.h"
  29 #include "clock3xxx.h"
  30 #include "clock34xx.h"
  31 #include "clock36xx.h"
  32 #include "clock3517.h"
  33 #include "cm3xxx.h"
  34 #include "cm-regbits-34xx.h"
  35 #include "prm3xxx.h"
  36 #include "prm-regbits-34xx.h"
  37 #include "control.h"
  38
  39 /*
  40  * clocks
  41  */
  42
  43 #define OMAP_CM_REGADDR         OMAP34XX_CM_REGADDR
  44
  45 /* Maximum DPLL multiplier, divider values for OMAP3 */
  46 #define OMAP3_MAX_DPLL_MULT             2047
  47 #define OMAP3630_MAX_JTYPE_DPLL_MULT    4095
  48 #define OMAP3_MAX_DPLL_DIV              128
  49
  50 DEFINE_CLK_FIXED_RATE(dummy_apb_pclk, CLK_IS_ROOT, 0x0, 0x0);
  51
  52 DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0);
  53
  54 DEFINE_CLK_FIXED_RATE(omap_32k_fck, CLK_IS_ROOT, 32768, 0x0);
  55
  56 DEFINE_CLK_FIXED_RATE(pclk_ck, CLK_IS_ROOT, 27000000, 0x0);
  57
  58 DEFINE_CLK_FIXED_RATE(rmii_ck, CLK_IS_ROOT, 50000000, 0x0);
  59
  60 DEFINE_CLK_FIXED_RATE(secure_32k_fck, CLK_IS_ROOT, 32768, 0x0);
  61
  62 DEFINE_CLK_FIXED_RATE(sys_altclk, CLK_IS_ROOT, 0x0, 0x0);
  63
  64 DEFINE_CLK_FIXED_RATE(virt_12m_ck, CLK_IS_ROOT, 12000000, 0x0);
  65
  66 DEFINE_CLK_FIXED_RATE(virt_13m_ck, CLK_IS_ROOT, 13000000, 0x0);
  67
  68 DEFINE_CLK_FIXED_RATE(virt_16_8m_ck, CLK_IS_ROOT, 16800000, 0x0);
  69
  70 DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
  71
  72 DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
  73
  74 DEFINE_CLK_FIXED_RATE(virt_38_4m_ck, CLK_IS_ROOT, 38400000, 0x0);
  75
  76 static const char *osc_sys_ck_parent_names[] = {
  77         "virt_12m_ck", "virt_13m_ck", "virt_19200000_ck", "virt_26000000_ck",
  78         "virt_38_4m_ck", "virt_16_8m_ck",
  79 };
  80
  81 DEFINE_CLK_MUX(osc_sys_ck, osc_sys_ck_parent_names, NULL, 0x0,
  82                OMAP3430_PRM_CLKSEL, OMAP3430_SYS_CLKIN_SEL_SHIFT,
  83                OMAP3430_SYS_CLKIN_SEL_WIDTH, 0x0, NULL);
  84
  85 DEFINE_CLK_DIVIDER(sys_ck, "osc_sys_ck", &osc_sys_ck, 0x0,
  86                    OMAP3430_PRM_CLKSRC_CTRL, OMAP_SYSCLKDIV_SHIFT,
  87                    OMAP_SYSCLKDIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
  88
  89 static struct dpll_data dpll3_dd = {
  90         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
  91         .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
  92         .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
  93         .clk_bypass     = &sys_ck,
  94         .clk_ref        = &sys_ck,
  95         .freqsel_mask   = OMAP3430_CORE_DPLL_FREQSEL_MASK,
  96         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
  97         .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
  98         .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
  99         .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
 100         .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
 101         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 102         .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
 103         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 104         .idlest_mask    = OMAP3430_ST_CORE_CLK_MASK,
 105         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 106         .min_divider    = 1,
 107         .max_divider    = OMAP3_MAX_DPLL_DIV,
 108 };
 109
 110 static struct clk dpll3_ck;
 111
 112 static const char *dpll3_ck_parent_names[] = {
 113         "sys_ck",
 114 };
 115
 116 static const struct clk_ops dpll3_ck_ops = {
 117         .init           = &omap2_init_clk_clkdm,
 118         .get_parent     = &omap2_init_dpll_parent,
 119         .recalc_rate    = &omap3_dpll_recalc,
 120         .round_rate     = &omap2_dpll_round_rate,
 121 };
 122
 123 static struct clk_hw_omap dpll3_ck_hw = {
 124         .hw = {
 125                 .clk = &dpll3_ck,
 126         },
 127         .ops            = &clkhwops_omap3_dpll,
 128         .dpll_data      = &dpll3_dd,
 129         .clkdm_name     = "dpll3_clkdm",
 130 };
 131
 132 DEFINE_STRUCT_CLK(dpll3_ck, dpll3_ck_parent_names, dpll3_ck_ops);
 133
 134 DEFINE_CLK_DIVIDER(dpll3_m2_ck, "dpll3_ck", &dpll3_ck, 0x0,
 135                    OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 136                    OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT,
 137                    OMAP3430_CORE_DPLL_CLKOUT_DIV_WIDTH,
 138                    CLK_DIVIDER_ONE_BASED, NULL);
 139
 140 static struct clk core_ck;
 141
 142 static const char *core_ck_parent_names[] = {
 143         "dpll3_m2_ck",
 144 };
 145
 146 static const struct clk_ops core_ck_ops = {};
 147
 148 DEFINE_STRUCT_CLK_HW_OMAP(core_ck, NULL);
 149 DEFINE_STRUCT_CLK(core_ck, core_ck_parent_names, core_ck_ops);
 150
 151 DEFINE_CLK_DIVIDER(l3_ick, "core_ck", &core_ck, 0x0,
 152                    OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
 153                    OMAP3430_CLKSEL_L3_SHIFT, OMAP3430_CLKSEL_L3_WIDTH,
 154                    CLK_DIVIDER_ONE_BASED, NULL);
 155
 156 DEFINE_CLK_DIVIDER(l4_ick, "l3_ick", &l3_ick, 0x0,
 157                    OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
 158                    OMAP3430_CLKSEL_L4_SHIFT, OMAP3430_CLKSEL_L4_WIDTH,
 159                    CLK_DIVIDER_ONE_BASED, NULL);
 160
 161 static struct clk security_l4_ick2;
 162
 163 static const char *security_l4_ick2_parent_names[] = {
 164         "l4_ick",
 165 };
 166
 167 DEFINE_STRUCT_CLK_HW_OMAP(security_l4_ick2, NULL);
 168 DEFINE_STRUCT_CLK(security_l4_ick2, security_l4_ick2_parent_names, core_ck_ops);
 169
 170 static struct clk aes1_ick;
 171
 172 static const char *aes1_ick_parent_names[] = {
 173         "security_l4_ick2",
 174 };
 175
 176 static const struct clk_ops aes1_ick_ops = {
 177         .enable         = &omap2_dflt_clk_enable,
 178         .disable        = &omap2_dflt_clk_disable,
 179         .is_enabled     = &omap2_dflt_clk_is_enabled,
 180 };
 181
 182 static struct clk_hw_omap aes1_ick_hw = {
 183         .hw = {
 184                 .clk = &aes1_ick,
 185         },
 186         .ops            = &clkhwops_iclk_wait,
 187         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
 188         .enable_bit     = OMAP3430_EN_AES1_SHIFT,
 189 };
 190
 191 DEFINE_STRUCT_CLK(aes1_ick, aes1_ick_parent_names, aes1_ick_ops);
 192
 193 static struct clk core_l4_ick;
 194
 195 static const struct clk_ops core_l4_ick_ops = {
 196         .init           = &omap2_init_clk_clkdm,
 197 };
 198
 199 DEFINE_STRUCT_CLK_HW_OMAP(core_l4_ick, "core_l4_clkdm");
 200 DEFINE_STRUCT_CLK(core_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops);
 201
 202 static struct clk aes2_ick;
 203
 204 static const char *aes2_ick_parent_names[] = {
 205         "core_l4_ick",
 206 };
 207
 208 static const struct clk_ops aes2_ick_ops = {
 209         .init           = &omap2_init_clk_clkdm,
 210         .enable         = &omap2_dflt_clk_enable,
 211         .disable        = &omap2_dflt_clk_disable,
 212         .is_enabled     = &omap2_dflt_clk_is_enabled,
 213 };
 214
 215 static struct clk_hw_omap aes2_ick_hw = {
 216         .hw = {
 217                 .clk = &aes2_ick,
 218         },
 219         .ops            = &clkhwops_iclk_wait,
 220         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 221         .enable_bit     = OMAP3430_EN_AES2_SHIFT,
 222         .clkdm_name     = "core_l4_clkdm",
 223 };
 224
 225 DEFINE_STRUCT_CLK(aes2_ick, aes2_ick_parent_names, aes2_ick_ops);
 226
 227 static struct clk dpll1_fck;
 228
 229 static struct dpll_data dpll1_dd = {
 230         .mult_div1_reg  = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 231         .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
 232         .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
 233         .clk_bypass     = &dpll1_fck,
 234         .clk_ref        = &sys_ck,
 235         .freqsel_mask   = OMAP3430_MPU_DPLL_FREQSEL_MASK,
 236         .control_reg    = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
 237         .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
 238         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 239         .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
 240         .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
 241         .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
 242         .autoidle_reg   = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 243         .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
 244         .idlest_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
 245         .idlest_mask    = OMAP3430_ST_MPU_CLK_MASK,
 246         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 247         .min_divider    = 1,
 248         .max_divider    = OMAP3_MAX_DPLL_DIV,
 249 };
 250
 251 static struct clk dpll1_ck;
 252
 253 static const struct clk_ops dpll1_ck_ops = {
 254         .init           = &omap2_init_clk_clkdm,
 255         .enable         = &omap3_noncore_dpll_enable,
 256         .disable        = &omap3_noncore_dpll_disable,
 257         .get_parent     = &omap2_init_dpll_parent,
 258         .recalc_rate    = &omap3_dpll_recalc,
 259         .set_rate       = &omap3_noncore_dpll_set_rate,
 260         .round_rate     = &omap2_dpll_round_rate,
 261 };
 262
 263 static struct clk_hw_omap dpll1_ck_hw = {
 264         .hw = {
 265                 .clk = &dpll1_ck,
 266         },
 267         .ops            = &clkhwops_omap3_dpll,
 268         .dpll_data      = &dpll1_dd,
 269         .clkdm_name     = "dpll1_clkdm",
 270 };
 271
 272 DEFINE_STRUCT_CLK(dpll1_ck, dpll3_ck_parent_names, dpll1_ck_ops);
 273
 274 DEFINE_CLK_FIXED_FACTOR(dpll1_x2_ck, "dpll1_ck", &dpll1_ck, 0x0, 2, 1);
 275
 276 DEFINE_CLK_DIVIDER(dpll1_x2m2_ck, "dpll1_x2_ck", &dpll1_x2_ck, 0x0,
 277                    OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
 278                    OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT,
 279                    OMAP3430_MPU_DPLL_CLKOUT_DIV_WIDTH,
 280                    CLK_DIVIDER_ONE_BASED, NULL);
 281
 282 static struct clk mpu_ck;
 283
 284 static const char *mpu_ck_parent_names[] = {
 285         "dpll1_x2m2_ck",
 286 };
 287
 288 DEFINE_STRUCT_CLK_HW_OMAP(mpu_ck, "mpu_clkdm");
 289 DEFINE_STRUCT_CLK(mpu_ck, mpu_ck_parent_names, core_l4_ick_ops);
 290
 291 DEFINE_CLK_DIVIDER(arm_fck, "mpu_ck", &mpu_ck, 0x0,
 292                    OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
 293                    OMAP3430_ST_MPU_CLK_SHIFT, OMAP3430_ST_MPU_CLK_WIDTH,
 294                    0x0, NULL);
 295
 296 static struct clk cam_ick;
 297
 298 static struct clk_hw_omap cam_ick_hw = {
 299         .hw = {
 300                 .clk = &cam_ick,
 301         },
 302         .ops            = &clkhwops_iclk,
 303         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
 304         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
 305         .clkdm_name     = "cam_clkdm",
 306 };
 307
 308 DEFINE_STRUCT_CLK(cam_ick, security_l4_ick2_parent_names, aes2_ick_ops);
 309
 310 /* DPLL4 */
 311 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
 312 /* Type: DPLL */
 313 static struct dpll_data dpll4_dd;
 314
 315 static struct dpll_data dpll4_dd_34xx __initdata = {
 316         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 317         .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
 318         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
 319         .clk_bypass     = &sys_ck,
 320         .clk_ref        = &sys_ck,
 321         .freqsel_mask   = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
 322         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 323         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
 324         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 325         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 326         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 327         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
 328         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 329         .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
 330         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 331         .idlest_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 332         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 333         .min_divider    = 1,
 334         .max_divider    = OMAP3_MAX_DPLL_DIV,
 335 };
 336
 337 static struct dpll_data dpll4_dd_3630 __initdata = {
 338         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 339         .mult_mask      = OMAP3630_PERIPH_DPLL_MULT_MASK,
 340         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
 341         .clk_bypass     = &sys_ck,
 342         .clk_ref        = &sys_ck,
 343         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 344         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
 345         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 346         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 347         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 348         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
 349         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 350         .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
 351         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 352         .idlest_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 353         .dco_mask       = OMAP3630_PERIPH_DPLL_DCO_SEL_MASK,
 354         .sddiv_mask     = OMAP3630_PERIPH_DPLL_SD_DIV_MASK,
 355         .max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT,
 356         .min_divider    = 1,
 357         .max_divider    = OMAP3_MAX_DPLL_DIV,
 358         .flags          = DPLL_J_TYPE
 359 };
 360
 361 static struct clk dpll4_ck;
 362
 363 static const struct clk_ops dpll4_ck_ops = {
 364         .init           = &omap2_init_clk_clkdm,
 365         .enable         = &omap3_noncore_dpll_enable,
 366         .disable        = &omap3_noncore_dpll_disable,
 367         .get_parent     = &omap2_init_dpll_parent,
 368         .recalc_rate    = &omap3_dpll_recalc,
 369         .set_rate       = &omap3_dpll4_set_rate,
 370         .round_rate     = &omap2_dpll_round_rate,
 371 };
 372
 373 static struct clk_hw_omap dpll4_ck_hw = {
 374         .hw = {
 375                 .clk = &dpll4_ck,
 376         },
 377         .dpll_data      = &dpll4_dd,
 378         .ops            = &clkhwops_omap3_dpll,
 379         .clkdm_name     = "dpll4_clkdm",
 380 };
 381
 382 DEFINE_STRUCT_CLK(dpll4_ck, dpll3_ck_parent_names, dpll4_ck_ops);
 383
 384 static const struct clk_div_table dpll4_mx_ck_div_table[] = {
 385         { .div = 1, .val = 1 },
 386         { .div = 2, .val = 2 },
 387         { .div = 3, .val = 3 },
 388         { .div = 4, .val = 4 },
 389         { .div = 5, .val = 5 },
 390         { .div = 6, .val = 6 },
 391         { .div = 7, .val = 7 },
 392         { .div = 8, .val = 8 },
 393         { .div = 9, .val = 9 },
 394         { .div = 10, .val = 10 },
 395         { .div = 11, .val = 11 },
 396         { .div = 12, .val = 12 },
 397         { .div = 13, .val = 13 },
 398         { .div = 14, .val = 14 },
 399         { .div = 15, .val = 15 },
 400         { .div = 16, .val = 16 },
 401         { .div = 17, .val = 17 },
 402         { .div = 18, .val = 18 },
 403         { .div = 19, .val = 19 },
 404         { .div = 20, .val = 20 },
 405         { .div = 21, .val = 21 },
 406         { .div = 22, .val = 22 },
 407         { .div = 23, .val = 23 },
 408         { .div = 24, .val = 24 },
 409         { .div = 25, .val = 25 },
 410         { .div = 26, .val = 26 },
 411         { .div = 27, .val = 27 },
 412         { .div = 28, .val = 28 },
 413         { .div = 29, .val = 29 },
 414         { .div = 30, .val = 30 },
 415         { .div = 31, .val = 31 },
 416         { .div = 32, .val = 32 },
 417         { .div = 0 },
 418 };
 419
 420 DEFINE_CLK_DIVIDER(dpll4_m5_ck, "dpll4_ck", &dpll4_ck, 0x0,
 421                    OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
 422                    OMAP3430_CLKSEL_CAM_SHIFT, OMAP3630_CLKSEL_CAM_WIDTH,
 423                    CLK_DIVIDER_ONE_BASED, NULL);
 424
 425 static struct clk dpll4_m5x2_ck;
 426
 427 static const char *dpll4_m5x2_ck_parent_names[] = {
 428         "dpll4_m5_ck",
 429 };
 430
 431 static const struct clk_ops dpll4_m5x2_ck_ops = {
 432         .init           = &omap2_init_clk_clkdm,
 433         .enable         = &omap2_dflt_clk_enable,
 434         .disable        = &omap2_dflt_clk_disable,
 435         .is_enabled     = &omap2_dflt_clk_is_enabled,
 436         .set_rate       = &omap3_clkoutx2_set_rate,
 437         .recalc_rate    = &omap3_clkoutx2_recalc,
 438         .round_rate     = &omap3_clkoutx2_round_rate,
 439 };
 440
 441 static const struct clk_ops dpll4_m5x2_ck_3630_ops = {
 442         .init           = &omap2_init_clk_clkdm,
 443         .enable         = &omap36xx_pwrdn_clk_enable_with_hsdiv_restore,
 444         .disable        = &omap2_dflt_clk_disable,
 445         .recalc_rate    = &omap3_clkoutx2_recalc,
 446 };
 447
 448 static struct clk_hw_omap dpll4_m5x2_ck_hw = {
 449         .hw = {
 450                 .clk = &dpll4_m5x2_ck,
 451         },
 452         .ops            = &clkhwops_wait,
 453         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 454         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 455         .flags          = INVERT_ENABLE,
 456         .clkdm_name     = "dpll4_clkdm",
 457 };
 458
 459 DEFINE_STRUCT_CLK(dpll4_m5x2_ck, dpll4_m5x2_ck_parent_names, dpll4_m5x2_ck_ops);
 460
 461 static struct clk dpll4_m5x2_ck_3630 = {
 462         .name           = "dpll4_m5x2_ck",
 463         .hw             = &dpll4_m5x2_ck_hw.hw,
 464         .parent_names   = dpll4_m5x2_ck_parent_names,
 465         .num_parents    = ARRAY_SIZE(dpll4_m5x2_ck_parent_names),
 466         .ops            = &dpll4_m5x2_ck_3630_ops,
 467         .flags          = CLK_SET_RATE_PARENT,
 468 };
 469
 470 static struct clk cam_mclk;
 471
 472 static const char *cam_mclk_parent_names[] = {
 473         "dpll4_m5x2_ck",
 474 };
 475
 476 static struct clk_hw_omap cam_mclk_hw = {
 477         .hw = {
 478                 .clk = &cam_mclk,
 479         },
 480         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
 481         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
 482         .clkdm_name     = "cam_clkdm",
 483 };
 484
 485 static struct clk cam_mclk = {
 486         .name           = "cam_mclk",
 487         .hw             = &cam_mclk_hw.hw,
 488         .parent_names   = cam_mclk_parent_names,
 489         .num_parents    = ARRAY_SIZE(cam_mclk_parent_names),
 490         .ops            = &aes2_ick_ops,
 491         .flags          = CLK_SET_RATE_PARENT,
 492 };
 493
 494 static const struct clksel_rate clkout2_src_core_rates[] = {
 495         { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
 496         { .div = 0 }
 497 };
 498
 499 static const struct clksel_rate clkout2_src_sys_rates[] = {
 500         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 501         { .div = 0 }
 502 };
 503
 504 static const struct clksel_rate clkout2_src_96m_rates[] = {
 505         { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
 506         { .div = 0 }
 507 };
 508
 509 DEFINE_CLK_DIVIDER(dpll4_m2_ck, "dpll4_ck", &dpll4_ck, 0x0,
 510                    OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
 511                    OMAP3430_DIV_96M_SHIFT, OMAP3630_DIV_96M_WIDTH,
 512                    CLK_DIVIDER_ONE_BASED, NULL);
 513
 514 static struct clk dpll4_m2x2_ck;
 515
 516 static const char *dpll4_m2x2_ck_parent_names[] = {
 517         "dpll4_m2_ck",
 518 };
 519
 520 static struct clk_hw_omap dpll4_m2x2_ck_hw = {
 521         .hw = {
 522                 .clk = &dpll4_m2x2_ck,
 523         },
 524         .ops            = &clkhwops_wait,
 525         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 526         .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
 527         .flags          = INVERT_ENABLE,
 528         .clkdm_name     = "dpll4_clkdm",
 529 };
 530
 531 DEFINE_STRUCT_CLK(dpll4_m2x2_ck, dpll4_m2x2_ck_parent_names, dpll4_m5x2_ck_ops);
 532
 533 static struct clk dpll4_m2x2_ck_3630 = {
 534         .name           = "dpll4_m2x2_ck",
 535         .hw             = &dpll4_m2x2_ck_hw.hw,
 536         .parent_names   = dpll4_m2x2_ck_parent_names,
 537         .num_parents    = ARRAY_SIZE(dpll4_m2x2_ck_parent_names),
 538         .ops            = &dpll4_m5x2_ck_3630_ops,
 539 };
 540
 541 static struct clk omap_96m_alwon_fck;
 542
 543 static const char *omap_96m_alwon_fck_parent_names[] = {
 544         "dpll4_m2x2_ck",
 545 };
 546
 547 DEFINE_STRUCT_CLK_HW_OMAP(omap_96m_alwon_fck, NULL);
 548 DEFINE_STRUCT_CLK(omap_96m_alwon_fck, omap_96m_alwon_fck_parent_names,
 549                   core_ck_ops);
 550
 551 static struct clk cm_96m_fck;
 552
 553 static const char *cm_96m_fck_parent_names[] = {
 554         "omap_96m_alwon_fck",
 555 };
 556
 557 DEFINE_STRUCT_CLK_HW_OMAP(cm_96m_fck, NULL);
 558 DEFINE_STRUCT_CLK(cm_96m_fck, cm_96m_fck_parent_names, core_ck_ops);
 559
 560 static const struct clksel_rate clkout2_src_54m_rates[] = {
 561         { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
 562         { .div = 0 }
 563 };
 564
 565 DEFINE_CLK_DIVIDER_TABLE(dpll4_m3_ck, "dpll4_ck", &dpll4_ck, 0x0,
 566                    OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 567                    OMAP3430_CLKSEL_TV_SHIFT, OMAP3630_CLKSEL_TV_WIDTH,
 568                    0, dpll4_mx_ck_div_table, NULL);
 569
 570 static struct clk dpll4_m3x2_ck;
 571
 572 static const char *dpll4_m3x2_ck_parent_names[] = {
 573         "dpll4_m3_ck",
 574 };
 575
 576 static struct clk_hw_omap dpll4_m3x2_ck_hw = {
 577         .hw = {
 578                 .clk = &dpll4_m3x2_ck,
 579         },
 580         .ops            = &clkhwops_wait,
 581         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 582         .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
 583         .flags          = INVERT_ENABLE,
 584         .clkdm_name     = "dpll4_clkdm",
 585 };
 586
 587 DEFINE_STRUCT_CLK(dpll4_m3x2_ck, dpll4_m3x2_ck_parent_names, dpll4_m5x2_ck_ops);
 588
 589 static struct clk dpll4_m3x2_ck_3630 = {
 590         .name           = "dpll4_m3x2_ck",
 591         .hw             = &dpll4_m3x2_ck_hw.hw,
 592         .parent_names   = dpll4_m3x2_ck_parent_names,
 593         .num_parents    = ARRAY_SIZE(dpll4_m3x2_ck_parent_names),
 594         .ops            = &dpll4_m5x2_ck_3630_ops,
 595 };
 596
 597 static const char *omap_54m_fck_parent_names[] = {
 598         "dpll4_m3x2_ck", "sys_altclk",
 599 };
 600
 601 DEFINE_CLK_MUX(omap_54m_fck, omap_54m_fck_parent_names, NULL, 0x0,
 602                OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), OMAP3430_SOURCE_54M_SHIFT,
 603                OMAP3430_SOURCE_54M_WIDTH, 0x0, NULL);
 604
 605 static const struct clksel clkout2_src_clksel[] = {
 606         { .parent = &core_ck, .rates = clkout2_src_core_rates },
 607         { .parent = &sys_ck, .rates = clkout2_src_sys_rates },
 608         { .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates },
 609         { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates },
 610         { .parent = NULL },
 611 };
 612
 613 static const char *clkout2_src_ck_parent_names[] = {
 614         "core_ck", "sys_ck", "cm_96m_fck", "omap_54m_fck",
 615 };
 616
 617 static const struct clk_ops clkout2_src_ck_ops = {
 618         .init           = &omap2_init_clk_clkdm,
 619         .enable         = &omap2_dflt_clk_enable,
 620         .disable        = &omap2_dflt_clk_disable,
 621         .is_enabled     = &omap2_dflt_clk_is_enabled,
 622         .recalc_rate    = &omap2_clksel_recalc,
 623         .get_parent     = &omap2_clksel_find_parent_index,
 624         .set_parent     = &omap2_clksel_set_parent,
 625 };
 626
 627 DEFINE_CLK_OMAP_MUX_GATE(clkout2_src_ck, "core_clkdm",
 628                          clkout2_src_clksel, OMAP3430_CM_CLKOUT_CTRL,
 629                          OMAP3430_CLKOUT2SOURCE_MASK,
 630                          OMAP3430_CM_CLKOUT_CTRL, OMAP3430_CLKOUT2_EN_SHIFT,
 631                          NULL, clkout2_src_ck_parent_names, clkout2_src_ck_ops);
 632
 633 static const struct clksel_rate omap_48m_cm96m_rates[] = {
 634         { .div = 2, .val = 0, .flags = RATE_IN_3XXX },
 635         { .div = 0 }
 636 };
 637
 638 static const struct clksel_rate omap_48m_alt_rates[] = {
 639         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 640         { .div = 0 }
 641 };
 642
 643 static const struct clksel omap_48m_clksel[] = {
 644         { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
 645         { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
 646         { .parent = NULL },
 647 };
 648
 649 static const char *omap_48m_fck_parent_names[] = {
 650         "cm_96m_fck", "sys_altclk",
 651 };
 652
 653 static struct clk omap_48m_fck;
 654
 655 static const struct clk_ops omap_48m_fck_ops = {
 656         .recalc_rate    = &omap2_clksel_recalc,
 657         .get_parent     = &omap2_clksel_find_parent_index,
 658         .set_parent     = &omap2_clksel_set_parent,
 659 };
 660
 661 static struct clk_hw_omap omap_48m_fck_hw = {
 662         .hw = {
 663                 .clk = &omap_48m_fck,
 664         },
 665         .clksel         = omap_48m_clksel,
 666         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 667         .clksel_mask    = OMAP3430_SOURCE_48M_MASK,
 668 };
 669
 670 DEFINE_STRUCT_CLK(omap_48m_fck, omap_48m_fck_parent_names, omap_48m_fck_ops);
 671
 672 DEFINE_CLK_FIXED_FACTOR(omap_12m_fck, "omap_48m_fck", &omap_48m_fck, 0x0, 1, 4);
 673
 674 static struct clk core_12m_fck;
 675
 676 static const char *core_12m_fck_parent_names[] = {
 677         "omap_12m_fck",
 678 };
 679
 680 DEFINE_STRUCT_CLK_HW_OMAP(core_12m_fck, "core_l4_clkdm");
 681 DEFINE_STRUCT_CLK(core_12m_fck, core_12m_fck_parent_names, core_l4_ick_ops);
 682
 683 static struct clk core_48m_fck;
 684
 685 static const char *core_48m_fck_parent_names[] = {
 686         "omap_48m_fck",
 687 };
 688
 689 DEFINE_STRUCT_CLK_HW_OMAP(core_48m_fck, "core_l4_clkdm");
 690 DEFINE_STRUCT_CLK(core_48m_fck, core_48m_fck_parent_names, core_l4_ick_ops);
 691
 692 static const char *omap_96m_fck_parent_names[] = {
 693         "cm_96m_fck", "sys_ck",
 694 };
 695
 696 DEFINE_CLK_MUX(omap_96m_fck, omap_96m_fck_parent_names, NULL, 0x0,
 697                OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 698                OMAP3430_SOURCE_96M_SHIFT, OMAP3430_SOURCE_96M_WIDTH, 0x0, NULL);
 699
 700 static struct clk core_96m_fck;
 701
 702 static const char *core_96m_fck_parent_names[] = {
 703         "omap_96m_fck",
 704 };
 705
 706 DEFINE_STRUCT_CLK_HW_OMAP(core_96m_fck, "core_l4_clkdm");
 707 DEFINE_STRUCT_CLK(core_96m_fck, core_96m_fck_parent_names, core_l4_ick_ops);
 708
 709 static struct clk core_l3_ick;
 710
 711 static const char *core_l3_ick_parent_names[] = {
 712         "l3_ick",
 713 };
 714
 715 DEFINE_STRUCT_CLK_HW_OMAP(core_l3_ick, "core_l3_clkdm");
 716 DEFINE_STRUCT_CLK(core_l3_ick, core_l3_ick_parent_names, core_l4_ick_ops);
 717
 718 DEFINE_CLK_FIXED_FACTOR(dpll3_m2x2_ck, "dpll3_m2_ck", &dpll3_m2_ck, 0x0, 2, 1);
 719
 720 static struct clk corex2_fck;
 721
 722 static const char *corex2_fck_parent_names[] = {
 723         "dpll3_m2x2_ck",
 724 };
 725
 726 DEFINE_STRUCT_CLK_HW_OMAP(corex2_fck, NULL);
 727 DEFINE_STRUCT_CLK(corex2_fck, corex2_fck_parent_names, core_ck_ops);
 728
 729 static struct clk cpefuse_fck;
 730
 731 static struct clk_hw_omap cpefuse_fck_hw = {
 732         .hw = {
 733                 .clk = &cpefuse_fck,
 734         },
 735         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
 736         .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
 737         .clkdm_name     = "core_l4_clkdm",
 738 };
 739
 740 DEFINE_STRUCT_CLK(cpefuse_fck, dpll3_ck_parent_names, aes2_ick_ops);
 741
 742 static struct clk csi2_96m_fck;
 743
 744 static const char *csi2_96m_fck_parent_names[] = {
 745         "core_96m_fck",
 746 };
 747
 748 static struct clk_hw_omap csi2_96m_fck_hw = {
 749         .hw = {
 750                 .clk = &csi2_96m_fck,
 751         },
 752         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
 753         .enable_bit     = OMAP3430_EN_CSI2_SHIFT,
 754         .clkdm_name     = "cam_clkdm",
 755 };
 756
 757 DEFINE_STRUCT_CLK(csi2_96m_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
 758
 759 static struct clk d2d_26m_fck;
 760
 761 static struct clk_hw_omap d2d_26m_fck_hw = {
 762         .hw = {
 763                 .clk = &d2d_26m_fck,
 764         },
 765         .ops            = &clkhwops_wait,
 766         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 767         .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
 768         .clkdm_name     = "d2d_clkdm",
 769 };
 770
 771 DEFINE_STRUCT_CLK(d2d_26m_fck, dpll3_ck_parent_names, aes2_ick_ops);
 772
 773 static struct clk des1_ick;
 774
 775 static struct clk_hw_omap des1_ick_hw = {
 776         .hw = {
 777                 .clk = &des1_ick,
 778         },
 779         .ops            = &clkhwops_iclk_wait,
 780         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
 781         .enable_bit     = OMAP3430_EN_DES1_SHIFT,
 782 };
 783
 784 DEFINE_STRUCT_CLK(des1_ick, aes1_ick_parent_names, aes1_ick_ops);
 785
 786 static struct clk des2_ick;
 787
 788 static struct clk_hw_omap des2_ick_hw = {
 789         .hw = {
 790                 .clk = &des2_ick,
 791         },
 792         .ops            = &clkhwops_iclk_wait,
 793         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 794         .enable_bit     = OMAP3430_EN_DES2_SHIFT,
 795         .clkdm_name     = "core_l4_clkdm",
 796 };
 797
 798 DEFINE_STRUCT_CLK(des2_ick, aes2_ick_parent_names, aes2_ick_ops);
 799
 800 DEFINE_CLK_DIVIDER(dpll1_fck, "core_ck", &core_ck, 0x0,
 801                    OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 802                    OMAP3430_MPU_CLK_SRC_SHIFT, OMAP3430_MPU_CLK_SRC_WIDTH,
 803                    CLK_DIVIDER_ONE_BASED, NULL);
 804
 805 static struct clk dpll2_fck;
 806
 807 static struct dpll_data dpll2_dd = {
 808         .mult_div1_reg  = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
 809         .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
 810         .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
 811         .clk_bypass     = &dpll2_fck,
 812         .clk_ref        = &sys_ck,
 813         .freqsel_mask   = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
 814         .control_reg    = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
 815         .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
 816         .modes          = ((1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
 817                            (1 << DPLL_LOW_POWER_BYPASS)),
 818         .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
 819         .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
 820         .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
 821         .autoidle_reg   = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 822         .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
 823         .idlest_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
 824         .idlest_mask    = OMAP3430_ST_IVA2_CLK_MASK,
 825         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 826         .min_divider    = 1,
 827         .max_divider    = OMAP3_MAX_DPLL_DIV,
 828 };
 829
 830 static struct clk dpll2_ck;
 831
 832 static struct clk_hw_omap dpll2_ck_hw = {
 833         .hw = {
 834                 .clk = &dpll2_ck,
 835         },
 836         .ops            = &clkhwops_omap3_dpll,
 837         .dpll_data      = &dpll2_dd,
 838         .clkdm_name     = "dpll2_clkdm",
 839 };
 840
 841 DEFINE_STRUCT_CLK(dpll2_ck, dpll3_ck_parent_names, dpll1_ck_ops);
 842
 843 DEFINE_CLK_DIVIDER(dpll2_fck, "core_ck", &core_ck, 0x0,
 844                    OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
 845                    OMAP3430_IVA2_CLK_SRC_SHIFT, OMAP3430_IVA2_CLK_SRC_WIDTH,
 846                    CLK_DIVIDER_ONE_BASED, NULL);
 847
 848 DEFINE_CLK_DIVIDER(dpll2_m2_ck, "dpll2_ck", &dpll2_ck, 0x0,
 849                    OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL2_PLL),
 850                    OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT,
 851                    OMAP3430_IVA2_DPLL_CLKOUT_DIV_WIDTH,
 852                    CLK_DIVIDER_ONE_BASED, NULL);
 853
 854 DEFINE_CLK_DIVIDER(dpll3_m3_ck, "dpll3_ck", &dpll3_ck, 0x0,
 855                    OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 856                    OMAP3430_DIV_DPLL3_SHIFT, OMAP3430_DIV_DPLL3_WIDTH,
 857                    CLK_DIVIDER_ONE_BASED, NULL);
 858
 859 static struct clk dpll3_m3x2_ck;
 860
 861 static const char *dpll3_m3x2_ck_parent_names[] = {
 862         "dpll3_m3_ck",
 863 };
 864
 865 static struct clk_hw_omap dpll3_m3x2_ck_hw = {
 866         .hw = {
 867                 .clk = &dpll3_m3x2_ck,
 868         },
 869         .ops            = &clkhwops_wait,
 870         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 871         .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
 872         .flags          = INVERT_ENABLE,
 873         .clkdm_name     = "dpll3_clkdm",
 874 };
 875
 876 DEFINE_STRUCT_CLK(dpll3_m3x2_ck, dpll3_m3x2_ck_parent_names, dpll4_m5x2_ck_ops);
 877
 878 static struct clk dpll3_m3x2_ck_3630 = {
 879         .name           = "dpll3_m3x2_ck",
 880         .hw             = &dpll3_m3x2_ck_hw.hw,
 881         .parent_names   = dpll3_m3x2_ck_parent_names,
 882         .num_parents    = ARRAY_SIZE(dpll3_m3x2_ck_parent_names),
 883         .ops            = &dpll4_m5x2_ck_3630_ops,
 884 };
 885
 886 DEFINE_CLK_FIXED_FACTOR(dpll3_x2_ck, "dpll3_ck", &dpll3_ck, 0x0, 2, 1);
 887
 888 DEFINE_CLK_DIVIDER_TABLE(dpll4_m4_ck, "dpll4_ck", &dpll4_ck, 0x0,
 889                    OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 890                    OMAP3430_CLKSEL_DSS1_SHIFT, OMAP3630_CLKSEL_DSS1_WIDTH,
 891                    0, dpll4_mx_ck_div_table, NULL);
 892
 893 static struct clk dpll4_m4x2_ck;
 894
 895 static const char *dpll4_m4x2_ck_parent_names[] = {
 896         "dpll4_m4_ck",
 897 };
 898
 899 static struct clk_hw_omap dpll4_m4x2_ck_hw = {
 900         .hw = {
 901                 .clk = &dpll4_m4x2_ck,
 902         },
 903         .ops            = &clkhwops_wait,
 904         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 905         .enable_bit     = OMAP3430_PWRDN_DSS1_SHIFT,
 906         .flags          = INVERT_ENABLE,
 907         .clkdm_name     = "dpll4_clkdm",
 908 };
 909
 910 DEFINE_STRUCT_CLK_FLAGS(dpll4_m4x2_ck, dpll4_m4x2_ck_parent_names,
 911                 dpll4_m5x2_ck_ops, CLK_SET_RATE_PARENT);
 912
 913 static struct clk dpll4_m4x2_ck_3630 = {
 914         .name           = "dpll4_m4x2_ck",
 915         .hw             = &dpll4_m4x2_ck_hw.hw,
 916         .parent_names   = dpll4_m4x2_ck_parent_names,
 917         .num_parents    = ARRAY_SIZE(dpll4_m4x2_ck_parent_names),
 918         .ops            = &dpll4_m5x2_ck_3630_ops,
 919         .flags          = CLK_SET_RATE_PARENT,
 920 };
 921
 922 DEFINE_CLK_DIVIDER(dpll4_m6_ck, "dpll4_ck", &dpll4_ck, 0x0,
 923                    OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 924                    OMAP3430_DIV_DPLL4_SHIFT, OMAP3630_DIV_DPLL4_WIDTH,
 925                    CLK_DIVIDER_ONE_BASED, NULL);
 926
 927 static struct clk dpll4_m6x2_ck;
 928
 929 static const char *dpll4_m6x2_ck_parent_names[] = {
 930         "dpll4_m6_ck",
 931 };
 932
 933 static struct clk_hw_omap dpll4_m6x2_ck_hw = {
 934         .hw = {
 935                 .clk = &dpll4_m6x2_ck,
 936         },
 937         .ops            = &clkhwops_wait,
 938         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 939         .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
 940         .flags          = INVERT_ENABLE,
 941         .clkdm_name     = "dpll4_clkdm",
 942 };
 943
 944 DEFINE_STRUCT_CLK(dpll4_m6x2_ck, dpll4_m6x2_ck_parent_names, dpll4_m5x2_ck_ops);
 945
 946 static struct clk dpll4_m6x2_ck_3630 = {
 947         .name           = "dpll4_m6x2_ck",
 948         .hw             = &dpll4_m6x2_ck_hw.hw,
 949         .parent_names   = dpll4_m6x2_ck_parent_names,
 950         .num_parents    = ARRAY_SIZE(dpll4_m6x2_ck_parent_names),
 951         .ops            = &dpll4_m5x2_ck_3630_ops,
 952 };
 953
 954 DEFINE_CLK_FIXED_FACTOR(dpll4_x2_ck, "dpll4_ck", &dpll4_ck, 0x0, 2, 1);
 955
 956 static struct dpll_data dpll5_dd = {
 957         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
 958         .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
 959         .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
 960         .clk_bypass     = &sys_ck,
 961         .clk_ref        = &sys_ck,
 962         .freqsel_mask   = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
 963         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
 964         .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
 965         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 966         .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
 967         .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
 968         .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
 969         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
 970         .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
 971         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 972         .idlest_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
 973         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 974         .min_divider    = 1,
 975         .max_divider    = OMAP3_MAX_DPLL_DIV,
 976 };
 977
 978 static struct clk dpll5_ck;
 979
 980 static struct clk_hw_omap dpll5_ck_hw = {
 981         .hw = {
 982                 .clk = &dpll5_ck,
 983         },
 984         .ops            = &clkhwops_omap3_dpll,
 985         .dpll_data      = &dpll5_dd,
 986         .clkdm_name     = "dpll5_clkdm",
 987 };
 988
 989 DEFINE_STRUCT_CLK(dpll5_ck, dpll3_ck_parent_names, dpll1_ck_ops);
 990
 991 DEFINE_CLK_DIVIDER(dpll5_m2_ck, "dpll5_ck", &dpll5_ck, 0x0,
 992                    OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
 993                    OMAP3430ES2_DIV_120M_SHIFT, OMAP3430ES2_DIV_120M_WIDTH,
 994                    CLK_DIVIDER_ONE_BASED, NULL);
 995
 996 static struct clk dss1_alwon_fck_3430es1;
 997
 998 static const char *dss1_alwon_fck_3430es1_parent_names[] = {
 999         "dpll4_m4x2_ck",
1000 };
1001
1002 static struct clk_hw_omap dss1_alwon_fck_3430es1_hw = {
1003         .hw = {
1004                 .clk = &dss1_alwon_fck_3430es1,
1005         },
1006         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1007         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
1008         .clkdm_name     = "dss_clkdm",
1009 };
1010
1011 DEFINE_STRUCT_CLK_FLAGS(dss1_alwon_fck_3430es1,
1012                 dss1_alwon_fck_3430es1_parent_names, aes2_ick_ops,
1013                 CLK_SET_RATE_PARENT);
1014
1015 static struct clk dss1_alwon_fck_3430es2;
1016
1017 static struct clk_hw_omap dss1_alwon_fck_3430es2_hw = {
1018         .hw = {
1019                 .clk = &dss1_alwon_fck_3430es2,
1020         },
1021         .ops            = &clkhwops_omap3430es2_dss_usbhost_wait,
1022         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1023         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
1024         .clkdm_name     = "dss_clkdm",
1025 };
1026
1027 DEFINE_STRUCT_CLK_FLAGS(dss1_alwon_fck_3430es2,
1028                 dss1_alwon_fck_3430es1_parent_names, aes2_ick_ops,
1029                 CLK_SET_RATE_PARENT);
1030
1031 static struct clk dss2_alwon_fck;
1032
1033 static struct clk_hw_omap dss2_alwon_fck_hw = {
1034         .hw = {
1035                 .clk = &dss2_alwon_fck,
1036         },
1037         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1038         .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
1039         .clkdm_name     = "dss_clkdm",
1040 };
1041
1042 DEFINE_STRUCT_CLK(dss2_alwon_fck, dpll3_ck_parent_names, aes2_ick_ops);
1043
1044 static struct clk dss_96m_fck;
1045
1046 static struct clk_hw_omap dss_96m_fck_hw = {
1047         .hw = {
1048                 .clk = &dss_96m_fck,
1049         },
1050         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1051         .enable_bit     = OMAP3430_EN_TV_SHIFT,
1052         .clkdm_name     = "dss_clkdm",
1053 };
1054
1055 DEFINE_STRUCT_CLK(dss_96m_fck, core_96m_fck_parent_names, aes2_ick_ops);
1056
1057 static struct clk dss_ick_3430es1;
1058
1059 static struct clk_hw_omap dss_ick_3430es1_hw = {
1060         .hw = {
1061                 .clk = &dss_ick_3430es1,
1062         },
1063         .ops            = &clkhwops_iclk,
1064         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
1065         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
1066         .clkdm_name     = "dss_clkdm",
1067 };
1068
1069 DEFINE_STRUCT_CLK(dss_ick_3430es1, security_l4_ick2_parent_names, aes2_ick_ops);
1070
1071 static struct clk dss_ick_3430es2;
1072
1073 static struct clk_hw_omap dss_ick_3430es2_hw = {
1074         .hw = {
1075                 .clk = &dss_ick_3430es2,
1076         },
1077         .ops            = &clkhwops_omap3430es2_iclk_dss_usbhost_wait,
1078         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
1079         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
1080         .clkdm_name     = "dss_clkdm",
1081 };
1082
1083 DEFINE_STRUCT_CLK(dss_ick_3430es2, security_l4_ick2_parent_names, aes2_ick_ops);
1084
1085 static struct clk dss_tv_fck;
1086
1087 static const char *dss_tv_fck_parent_names[] = {
1088         "omap_54m_fck",
1089 };
1090
1091 static struct clk_hw_omap dss_tv_fck_hw = {
1092         .hw = {
1093                 .clk = &dss_tv_fck,
1094         },
1095         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1096         .enable_bit     = OMAP3430_EN_TV_SHIFT,
1097         .clkdm_name     = "dss_clkdm",
1098 };
1099
1100 DEFINE_STRUCT_CLK(dss_tv_fck, dss_tv_fck_parent_names, aes2_ick_ops);
1101
1102 static struct clk emac_fck;
1103
1104 static const char *emac_fck_parent_names[] = {
1105         "rmii_ck",
1106 };
1107
1108 static struct clk_hw_omap emac_fck_hw = {
1109         .hw = {
1110                 .clk = &emac_fck,
1111         },
1112         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
1113         .enable_bit     = AM35XX_CPGMAC_FCLK_SHIFT,
1114 };
1115
1116 DEFINE_STRUCT_CLK(emac_fck, emac_fck_parent_names, aes1_ick_ops);
1117
1118 static struct clk ipss_ick;
1119
1120 static const char *ipss_ick_parent_names[] = {
1121         "core_l3_ick",
1122 };
1123
1124 static struct clk_hw_omap ipss_ick_hw = {
1125         .hw = {
1126                 .clk = &ipss_ick,
1127         },
1128         .ops            = &clkhwops_am35xx_ipss_wait,
1129         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1130         .enable_bit     = AM35XX_EN_IPSS_SHIFT,
1131         .clkdm_name     = "core_l3_clkdm",
1132 };
1133
1134 DEFINE_STRUCT_CLK(ipss_ick, ipss_ick_parent_names, aes2_ick_ops);
1135
1136 static struct clk emac_ick;
1137
1138 static const char *emac_ick_parent_names[] = {
1139         "ipss_ick",
1140 };
1141
1142 static struct clk_hw_omap emac_ick_hw = {
1143         .hw = {
1144                 .clk = &emac_ick,
1145         },
1146         .ops            = &clkhwops_am35xx_ipss_module_wait,
1147         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
1148         .enable_bit     = AM35XX_CPGMAC_VBUSP_CLK_SHIFT,
1149         .clkdm_name     = "core_l3_clkdm",
1150 };
1151
1152 DEFINE_STRUCT_CLK(emac_ick, emac_ick_parent_names, aes2_ick_ops);
1153
1154 static struct clk emu_core_alwon_ck;
1155
1156 static const char *emu_core_alwon_ck_parent_names[] = {
1157         "dpll3_m3x2_ck",
1158 };
1159
1160 DEFINE_STRUCT_CLK_HW_OMAP(emu_core_alwon_ck, "dpll3_clkdm");
1161 DEFINE_STRUCT_CLK(emu_core_alwon_ck, emu_core_alwon_ck_parent_names,
1162                   core_l4_ick_ops);
1163
1164 static struct clk emu_mpu_alwon_ck;
1165
1166 static const char *emu_mpu_alwon_ck_parent_names[] = {
1167         "mpu_ck",
1168 };
1169
1170 DEFINE_STRUCT_CLK_HW_OMAP(emu_mpu_alwon_ck, NULL);
1171 DEFINE_STRUCT_CLK(emu_mpu_alwon_ck, emu_mpu_alwon_ck_parent_names, core_ck_ops);
1172
1173 static struct clk emu_per_alwon_ck;
1174
1175 static const char *emu_per_alwon_ck_parent_names[] = {
1176         "dpll4_m6x2_ck",
1177 };
1178
1179 DEFINE_STRUCT_CLK_HW_OMAP(emu_per_alwon_ck, "dpll4_clkdm");
1180 DEFINE_STRUCT_CLK(emu_per_alwon_ck, emu_per_alwon_ck_parent_names,
1181                   core_l4_ick_ops);
1182
1183 static const char *emu_src_ck_parent_names[] = {
1184         "sys_ck", "emu_core_alwon_ck", "emu_per_alwon_ck", "emu_mpu_alwon_ck",
1185 };
1186
1187 static const struct clksel_rate emu_src_sys_rates[] = {
1188         { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
1189         { .div = 0 },
1190 };
1191
1192 static const struct clksel_rate emu_src_core_rates[] = {
1193         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1194         { .div = 0 },
1195 };
1196
1197 static const struct clksel_rate emu_src_per_rates[] = {
1198         { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
1199         { .div = 0 },
1200 };
1201
1202 static const struct clksel_rate emu_src_mpu_rates[] = {
1203         { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
1204         { .div = 0 },
1205 };
1206
1207 static const struct clksel emu_src_clksel[] = {
1208         { .parent = &sys_ck,            .rates = emu_src_sys_rates },
1209         { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
1210         { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
1211         { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
1212         { .parent = NULL },
1213 };
1214
1215 static const struct clk_ops emu_src_ck_ops = {
1216         .init           = &omap2_init_clk_clkdm,
1217         .recalc_rate    = &omap2_clksel_recalc,
1218         .get_parent     = &omap2_clksel_find_parent_index,
1219         .set_parent     = &omap2_clksel_set_parent,
1220         .enable         = &omap2_clkops_enable_clkdm,
1221         .disable        = &omap2_clkops_disable_clkdm,
1222 };
1223
1224 static struct clk emu_src_ck;
1225
1226 static struct clk_hw_omap emu_src_ck_hw = {
1227         .hw = {
1228                 .clk = &emu_src_ck,
1229         },
1230         .clksel         = emu_src_clksel,
1231         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
1232         .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
1233         .clkdm_name     = "emu_clkdm",
1234 };
1235
1236 DEFINE_STRUCT_CLK(emu_src_ck, emu_src_ck_parent_names, emu_src_ck_ops);
1237
1238 DEFINE_CLK_DIVIDER(atclk_fck, "emu_src_ck", &emu_src_ck, 0x0,
1239                    OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
1240                    OMAP3430_CLKSEL_ATCLK_SHIFT, OMAP3430_CLKSEL_ATCLK_WIDTH,
1241                    CLK_DIVIDER_ONE_BASED, NULL);
1242
1243 static struct clk fac_ick;
1244
1245 static struct clk_hw_omap fac_ick_hw = {
1246         .hw = {
1247                 .clk = &fac_ick,
1248         },
1249         .ops            = &clkhwops_iclk_wait,
1250         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1251         .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
1252         .clkdm_name     = "core_l4_clkdm",
1253 };
1254
1255 DEFINE_STRUCT_CLK(fac_ick, aes2_ick_parent_names, aes2_ick_ops);
1256
1257 static struct clk fshostusb_fck;
1258
1259 static const char *fshostusb_fck_parent_names[] = {
1260         "core_48m_fck",
1261 };
1262
1263 static struct clk_hw_omap fshostusb_fck_hw = {
1264         .hw = {
1265                 .clk = &fshostusb_fck,
1266         },
1267         .ops            = &clkhwops_wait,
1268         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1269         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1270         .clkdm_name     = "core_l4_clkdm",
1271 };
1272
1273 DEFINE_STRUCT_CLK(fshostusb_fck, fshostusb_fck_parent_names, aes2_ick_ops);
1274
1275 static struct clk gfx_l3_ck;
1276
1277 static struct clk_hw_omap gfx_l3_ck_hw = {
1278         .hw = {
1279                 .clk = &gfx_l3_ck,
1280         },
1281         .ops            = &clkhwops_wait,
1282         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1283         .enable_bit     = OMAP_EN_GFX_SHIFT,
1284         .clkdm_name     = "gfx_3430es1_clkdm",
1285 };
1286
1287 DEFINE_STRUCT_CLK(gfx_l3_ck, core_l3_ick_parent_names, aes1_ick_ops);
1288
1289 DEFINE_CLK_DIVIDER(gfx_l3_fck, "l3_ick", &l3_ick, 0x0,
1290                    OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1291                    OMAP_CLKSEL_GFX_SHIFT, OMAP_CLKSEL_GFX_WIDTH,
1292                    CLK_DIVIDER_ONE_BASED, NULL);
1293
1294 static struct clk gfx_cg1_ck;
1295
1296 static const char *gfx_cg1_ck_parent_names[] = {
1297         "gfx_l3_fck",
1298 };
1299
1300 static struct clk_hw_omap gfx_cg1_ck_hw = {
1301         .hw = {
1302                 .clk = &gfx_cg1_ck,
1303         },
1304         .ops            = &clkhwops_wait,
1305         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1306         .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
1307         .clkdm_name     = "gfx_3430es1_clkdm",
1308 };
1309
1310 DEFINE_STRUCT_CLK(gfx_cg1_ck, gfx_cg1_ck_parent_names, aes2_ick_ops);
1311
1312 static struct clk gfx_cg2_ck;
1313
1314 static struct clk_hw_omap gfx_cg2_ck_hw = {
1315         .hw = {
1316                 .clk = &gfx_cg2_ck,
1317         },
1318         .ops            = &clkhwops_wait,
1319         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1320         .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
1321         .clkdm_name     = "gfx_3430es1_clkdm",
1322 };
1323
1324 DEFINE_STRUCT_CLK(gfx_cg2_ck, gfx_cg1_ck_parent_names, aes2_ick_ops);
1325
1326 static struct clk gfx_l3_ick;
1327
1328 static const char *gfx_l3_ick_parent_names[] = {
1329         "gfx_l3_ck",
1330 };
1331
1332 DEFINE_STRUCT_CLK_HW_OMAP(gfx_l3_ick, "gfx_3430es1_clkdm");
1333 DEFINE_STRUCT_CLK(gfx_l3_ick, gfx_l3_ick_parent_names, core_l4_ick_ops);
1334
1335 static struct clk wkup_32k_fck;
1336
1337 static const char *wkup_32k_fck_parent_names[] = {
1338         "omap_32k_fck",
1339 };
1340
1341 DEFINE_STRUCT_CLK_HW_OMAP(wkup_32k_fck, "wkup_clkdm");
1342 DEFINE_STRUCT_CLK(wkup_32k_fck, wkup_32k_fck_parent_names, core_l4_ick_ops);
1343
1344 static struct clk gpio1_dbck;
1345
1346 static const char *gpio1_dbck_parent_names[] = {
1347         "wkup_32k_fck",
1348 };
1349
1350 static struct clk_hw_omap gpio1_dbck_hw = {
1351         .hw = {
1352                 .clk = &gpio1_dbck,
1353         },
1354         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1355         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
1356         .clkdm_name     = "wkup_clkdm",
1357 };
1358
1359 DEFINE_STRUCT_CLK(gpio1_dbck, gpio1_dbck_parent_names, aes2_ick_ops);
1360
1361 static struct clk wkup_l4_ick;
1362
1363 DEFINE_STRUCT_CLK_HW_OMAP(wkup_l4_ick, "wkup_clkdm");
1364 DEFINE_STRUCT_CLK(wkup_l4_ick, dpll3_ck_parent_names, core_l4_ick_ops);
1365
1366 static struct clk gpio1_ick;
1367
1368 static const char *gpio1_ick_parent_names[] = {
1369         "wkup_l4_ick",
1370 };
1371
1372 static struct clk_hw_omap gpio1_ick_hw = {
1373         .hw = {
1374                 .clk = &gpio1_ick,
1375         },
1376         .ops            = &clkhwops_iclk_wait,
1377         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1378         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
1379         .clkdm_name     = "wkup_clkdm",
1380 };
1381
1382 DEFINE_STRUCT_CLK(gpio1_ick, gpio1_ick_parent_names, aes2_ick_ops);
1383
1384 static struct clk per_32k_alwon_fck;
1385
1386 DEFINE_STRUCT_CLK_HW_OMAP(per_32k_alwon_fck, "per_clkdm");
1387 DEFINE_STRUCT_CLK(per_32k_alwon_fck, wkup_32k_fck_parent_names,
1388                   core_l4_ick_ops);
1389
1390 static struct clk gpio2_dbck;
1391
1392 static const char *gpio2_dbck_parent_names[] = {
1393         "per_32k_alwon_fck",
1394 };
1395
1396 static struct clk_hw_omap gpio2_dbck_hw = {
1397         .hw = {
1398                 .clk = &gpio2_dbck,
1399         },
1400         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1401         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
1402         .clkdm_name     = "per_clkdm",
1403 };
1404
1405 DEFINE_STRUCT_CLK(gpio2_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
1406
1407 static struct clk per_l4_ick;
1408
1409 DEFINE_STRUCT_CLK_HW_OMAP(per_l4_ick, "per_clkdm");
1410 DEFINE_STRUCT_CLK(per_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops);
1411
1412 static struct clk gpio2_ick;
1413
1414 static const char *gpio2_ick_parent_names[] = {
1415         "per_l4_ick",
1416 };
1417
1418 static struct clk_hw_omap gpio2_ick_hw = {
1419         .hw = {
1420                 .clk = &gpio2_ick,
1421         },
1422         .ops            = &clkhwops_iclk_wait,
1423         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1424         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
1425         .clkdm_name     = "per_clkdm",
1426 };
1427
1428 DEFINE_STRUCT_CLK(gpio2_ick, gpio2_ick_parent_names, aes2_ick_ops);
1429
1430 static struct clk gpio3_dbck;
1431
1432 static struct clk_hw_omap gpio3_dbck_hw = {
1433         .hw = {
1434                 .clk = &gpio3_dbck,
1435         },
1436         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1437         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
1438         .clkdm_name     = "per_clkdm",
1439 };
1440
1441 DEFINE_STRUCT_CLK(gpio3_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
1442
1443 static struct clk gpio3_ick;
1444
1445 static struct clk_hw_omap gpio3_ick_hw = {
1446         .hw = {
1447                 .clk = &gpio3_ick,
1448         },
1449         .ops            = &clkhwops_iclk_wait,
1450         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1451         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
1452         .clkdm_name     = "per_clkdm",
1453 };
1454
1455 DEFINE_STRUCT_CLK(gpio3_ick, gpio2_ick_parent_names, aes2_ick_ops);
1456
1457 static struct clk gpio4_dbck;
1458
1459 static struct clk_hw_omap gpio4_dbck_hw = {
1460         .hw = {
1461                 .clk = &gpio4_dbck,
1462         },
1463         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1464         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
1465         .clkdm_name     = "per_clkdm",
1466 };
1467
1468 DEFINE_STRUCT_CLK(gpio4_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
1469
1470 static struct clk gpio4_ick;
1471
1472 static struct clk_hw_omap gpio4_ick_hw = {
1473         .hw = {
1474                 .clk = &gpio4_ick,
1475         },
1476         .ops            = &clkhwops_iclk_wait,
1477         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1478         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
1479         .clkdm_name     = "per_clkdm",
1480 };
1481
1482 DEFINE_STRUCT_CLK(gpio4_ick, gpio2_ick_parent_names, aes2_ick_ops);
1483
1484 static struct clk gpio5_dbck;
1485
1486 static struct clk_hw_omap gpio5_dbck_hw = {
1487         .hw = {
1488                 .clk = &gpio5_dbck,
1489         },
1490         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1491         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
1492         .clkdm_name     = "per_clkdm",
1493 };
1494
1495 DEFINE_STRUCT_CLK(gpio5_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
1496
1497 static struct clk gpio5_ick;
1498
1499 static struct clk_hw_omap gpio5_ick_hw = {
1500         .hw = {
1501                 .clk = &gpio5_ick,
1502         },
1503         .ops            = &clkhwops_iclk_wait,
1504         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1505         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
1506         .clkdm_name     = "per_clkdm",
1507 };
1508
1509 DEFINE_STRUCT_CLK(gpio5_ick, gpio2_ick_parent_names, aes2_ick_ops);
1510
1511 static struct clk gpio6_dbck;
1512
1513 static struct clk_hw_omap gpio6_dbck_hw = {
1514         .hw = {
1515                 .clk = &gpio6_dbck,
1516         },
1517         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1518         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
1519         .clkdm_name     = "per_clkdm",
1520 };
1521
1522 DEFINE_STRUCT_CLK(gpio6_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
1523
1524 static struct clk gpio6_ick;
1525
1526 static struct clk_hw_omap gpio6_ick_hw = {
1527         .hw = {
1528                 .clk = &gpio6_ick,
1529         },
1530         .ops            = &clkhwops_iclk_wait,
1531         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1532         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
1533         .clkdm_name     = "per_clkdm",
1534 };
1535
1536 DEFINE_STRUCT_CLK(gpio6_ick, gpio2_ick_parent_names, aes2_ick_ops);
1537
1538 static struct clk gpmc_fck;
1539
1540 static struct clk_hw_omap gpmc_fck_hw = {
1541         .hw = {
1542                 .clk = &gpmc_fck,
1543         },
1544         .flags          = ENABLE_ON_INIT,
1545         .clkdm_name     = "core_l3_clkdm",
1546 };
1547
1548 DEFINE_STRUCT_CLK(gpmc_fck, ipss_ick_parent_names, core_l4_ick_ops);
1549
1550 static const struct clksel omap343x_gpt_clksel[] = {
1551         { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1552         { .parent = &sys_ck, .rates = gpt_sys_rates },
1553         { .parent = NULL },
1554 };
1555
1556 static const char *gpt10_fck_parent_names[] = {
1557         "omap_32k_fck", "sys_ck",
1558 };
1559
1560 DEFINE_CLK_OMAP_MUX_GATE(gpt10_fck, "core_l4_clkdm", omap343x_gpt_clksel,
1561                          OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1562                          OMAP3430_CLKSEL_GPT10_MASK,
1563                          OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1564                          OMAP3430_EN_GPT10_SHIFT, &clkhwops_wait,
1565                          gpt10_fck_parent_names, clkout2_src_ck_ops);
1566
1567 static struct clk gpt10_ick;
1568
1569 static struct clk_hw_omap gpt10_ick_hw = {
1570         .hw = {
1571                 .clk = &gpt10_ick,
1572         },
1573         .ops            = &clkhwops_iclk_wait,
1574         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1575         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1576         .clkdm_name     = "core_l4_clkdm",
1577 };
1578
1579 DEFINE_STRUCT_CLK(gpt10_ick, aes2_ick_parent_names, aes2_ick_ops);
1580
1581 DEFINE_CLK_OMAP_MUX_GATE(gpt11_fck, "core_l4_clkdm", omap343x_gpt_clksel,
1582                          OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1583                          OMAP3430_CLKSEL_GPT11_MASK,
1584                          OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1585                          OMAP3430_EN_GPT11_SHIFT, &clkhwops_wait,
1586                          gpt10_fck_parent_names, clkout2_src_ck_ops);
1587
1588 static struct clk gpt11_ick;
1589
1590 static struct clk_hw_omap gpt11_ick_hw = {
1591         .hw = {
1592                 .clk = &gpt11_ick,
1593         },
1594         .ops            = &clkhwops_iclk_wait,
1595         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1596         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1597         .clkdm_name     = "core_l4_clkdm",
1598 };
1599
1600 DEFINE_STRUCT_CLK(gpt11_ick, aes2_ick_parent_names, aes2_ick_ops);
1601
1602 static struct clk gpt12_fck;
1603
1604 static const char *gpt12_fck_parent_names[] = {
1605         "secure_32k_fck",
1606 };
1607
1608 DEFINE_STRUCT_CLK_HW_OMAP(gpt12_fck, "wkup_clkdm");
1609 DEFINE_STRUCT_CLK(gpt12_fck, gpt12_fck_parent_names, core_l4_ick_ops);
1610
1611 static struct clk gpt12_ick;
1612
1613 static struct clk_hw_omap gpt12_ick_hw = {
1614         .hw = {
1615                 .clk = &gpt12_ick,
1616         },
1617         .ops            = &clkhwops_iclk_wait,
1618         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1619         .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
1620         .clkdm_name     = "wkup_clkdm",
1621 };
1622
1623 DEFINE_STRUCT_CLK(gpt12_ick, gpio1_ick_parent_names, aes2_ick_ops);
1624
1625 DEFINE_CLK_OMAP_MUX_GATE(gpt1_fck, "wkup_clkdm", omap343x_gpt_clksel,
1626                          OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1627                          OMAP3430_CLKSEL_GPT1_MASK,
1628                          OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1629                          OMAP3430_EN_GPT1_SHIFT, &clkhwops_wait,
1630                          gpt10_fck_parent_names, clkout2_src_ck_ops);
1631
1632 static struct clk gpt1_ick;
1633
1634 static struct clk_hw_omap gpt1_ick_hw = {
1635         .hw = {
1636                 .clk = &gpt1_ick,
1637         },
1638         .ops            = &clkhwops_iclk_wait,
1639         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1640         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
1641         .clkdm_name     = "wkup_clkdm",
1642 };
1643
1644 DEFINE_STRUCT_CLK(gpt1_ick, gpio1_ick_parent_names, aes2_ick_ops);
1645
1646 DEFINE_CLK_OMAP_MUX_GATE(gpt2_fck, "per_clkdm", omap343x_gpt_clksel,
1647                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1648                          OMAP3430_CLKSEL_GPT2_MASK,
1649                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1650                          OMAP3430_EN_GPT2_SHIFT, &clkhwops_wait,
1651                          gpt10_fck_parent_names, clkout2_src_ck_ops);
1652
1653 static struct clk gpt2_ick;
1654
1655 static struct clk_hw_omap gpt2_ick_hw = {
1656         .hw = {
1657                 .clk = &gpt2_ick,
1658         },
1659         .ops            = &clkhwops_iclk_wait,
1660         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1661         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
1662         .clkdm_name     = "per_clkdm",
1663 };
1664
1665 DEFINE_STRUCT_CLK(gpt2_ick, gpio2_ick_parent_names, aes2_ick_ops);
1666
1667 DEFINE_CLK_OMAP_MUX_GATE(gpt3_fck, "per_clkdm", omap343x_gpt_clksel,
1668                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1669                          OMAP3430_CLKSEL_GPT3_MASK,
1670                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1671                          OMAP3430_EN_GPT3_SHIFT, &clkhwops_wait,
1672                          gpt10_fck_parent_names, clkout2_src_ck_ops);
1673
1674 static struct clk gpt3_ick;
1675
1676 static struct clk_hw_omap gpt3_ick_hw = {
1677         .hw = {
1678                 .clk = &gpt3_ick,
1679         },
1680         .ops            = &clkhwops_iclk_wait,
1681         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1682         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
1683         .clkdm_name     = "per_clkdm",
1684 };
1685
1686 DEFINE_STRUCT_CLK(gpt3_ick, gpio2_ick_parent_names, aes2_ick_ops);
1687
1688 DEFINE_CLK_OMAP_MUX_GATE(gpt4_fck, "per_clkdm", omap343x_gpt_clksel,
1689                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1690                          OMAP3430_CLKSEL_GPT4_MASK,
1691                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1692                          OMAP3430_EN_GPT4_SHIFT, &clkhwops_wait,
1693                          gpt10_fck_parent_names, clkout2_src_ck_ops);
1694
1695 static struct clk gpt4_ick;
1696
1697 static struct clk_hw_omap gpt4_ick_hw = {
1698         .hw = {
1699                 .clk = &gpt4_ick,
1700         },
1701         .ops            = &clkhwops_iclk_wait,
1702         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1703         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
1704         .clkdm_name     = "per_clkdm",
1705 };
1706
1707 DEFINE_STRUCT_CLK(gpt4_ick, gpio2_ick_parent_names, aes2_ick_ops);
1708
1709 DEFINE_CLK_OMAP_MUX_GATE(gpt5_fck, "per_clkdm", omap343x_gpt_clksel,
1710                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1711                          OMAP3430_CLKSEL_GPT5_MASK,
1712                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1713                          OMAP3430_EN_GPT5_SHIFT, &clkhwops_wait,
1714                          gpt10_fck_parent_names, clkout2_src_ck_ops);
1715
1716 static struct clk gpt5_ick;
1717
1718 static struct clk_hw_omap gpt5_ick_hw = {
1719         .hw = {
1720                 .clk = &gpt5_ick,
1721         },
1722         .ops            = &clkhwops_iclk_wait,
1723         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1724         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
1725         .clkdm_name     = "per_clkdm",
1726 };
1727
1728 DEFINE_STRUCT_CLK(gpt5_ick, gpio2_ick_parent_names, aes2_ick_ops);
1729
1730 DEFINE_CLK_OMAP_MUX_GATE(gpt6_fck, "per_clkdm", omap343x_gpt_clksel,
1731                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1732                          OMAP3430_CLKSEL_GPT6_MASK,
1733                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1734                          OMAP3430_EN_GPT6_SHIFT, &clkhwops_wait,
1735                          gpt10_fck_parent_names, clkout2_src_ck_ops);
1736
1737 static struct clk gpt6_ick;
1738
1739 static struct clk_hw_omap gpt6_ick_hw = {
1740         .hw = {
1741                 .clk = &gpt6_ick,
1742         },
1743         .ops            = &clkhwops_iclk_wait,
1744         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1745         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
1746         .clkdm_name     = "per_clkdm",
1747 };
1748
1749 DEFINE_STRUCT_CLK(gpt6_ick, gpio2_ick_parent_names, aes2_ick_ops);
1750
1751 DEFINE_CLK_OMAP_MUX_GATE(gpt7_fck, "per_clkdm", omap343x_gpt_clksel,
1752                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1753                          OMAP3430_CLKSEL_GPT7_MASK,
1754                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1755                          OMAP3430_EN_GPT7_SHIFT, &clkhwops_wait,
1756                          gpt10_fck_parent_names, clkout2_src_ck_ops);
1757
1758 static struct clk gpt7_ick;
1759
1760 static struct clk_hw_omap gpt7_ick_hw = {
1761         .hw = {
1762                 .clk = &gpt7_ick,
1763         },
1764         .ops            = &clkhwops_iclk_wait,
1765         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1766         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
1767         .clkdm_name     = "per_clkdm",
1768 };
1769
1770 DEFINE_STRUCT_CLK(gpt7_ick, gpio2_ick_parent_names, aes2_ick_ops);
1771
1772 DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck, "per_clkdm", omap343x_gpt_clksel,
1773                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1774                          OMAP3430_CLKSEL_GPT8_MASK,
1775                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1776                          OMAP3430_EN_GPT8_SHIFT, &clkhwops_wait,
1777                          gpt10_fck_parent_names, clkout2_src_ck_ops);
1778
1779 static struct clk gpt8_ick;
1780
1781 static struct clk_hw_omap gpt8_ick_hw = {
1782         .hw = {
1783                 .clk = &gpt8_ick,
1784         },
1785         .ops            = &clkhwops_iclk_wait,
1786         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1787         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
1788         .clkdm_name     = "per_clkdm",
1789 };
1790
1791 DEFINE_STRUCT_CLK(gpt8_ick, gpio2_ick_parent_names, aes2_ick_ops);
1792
1793 DEFINE_CLK_OMAP_MUX_GATE(gpt9_fck, "per_clkdm", omap343x_gpt_clksel,
1794                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1795                          OMAP3430_CLKSEL_GPT9_MASK,
1796                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1797                          OMAP3430_EN_GPT9_SHIFT, &clkhwops_wait,
1798                          gpt10_fck_parent_names, clkout2_src_ck_ops);
1799
1800 static struct clk gpt9_ick;
1801
1802 static struct clk_hw_omap gpt9_ick_hw = {
1803         .hw = {
1804                 .clk = &gpt9_ick,
1805         },
1806         .ops            = &clkhwops_iclk_wait,
1807         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1808         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
1809         .clkdm_name     = "per_clkdm",
1810 };
1811
1812 DEFINE_STRUCT_CLK(gpt9_ick, gpio2_ick_parent_names, aes2_ick_ops);
1813
1814 static struct clk hdq_fck;
1815
1816 static const char *hdq_fck_parent_names[] = {
1817         "core_12m_fck",
1818 };
1819
1820 static struct clk_hw_omap hdq_fck_hw = {
1821         .hw = {
1822                 .clk = &hdq_fck,
1823         },
1824         .ops            = &clkhwops_wait,
1825         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1826         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1827         .clkdm_name     = "core_l4_clkdm",
1828 };
1829
1830 DEFINE_STRUCT_CLK(hdq_fck, hdq_fck_parent_names, aes2_ick_ops);
1831
1832 static struct clk hdq_ick;
1833
1834 static struct clk_hw_omap hdq_ick_hw = {
1835         .hw = {
1836                 .clk = &hdq_ick,
1837         },
1838         .ops            = &clkhwops_iclk_wait,
1839         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1840         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1841         .clkdm_name     = "core_l4_clkdm",
1842 };
1843
1844 DEFINE_STRUCT_CLK(hdq_ick, aes2_ick_parent_names, aes2_ick_ops);
1845
1846 static struct clk hecc_ck;
1847
1848 static struct clk_hw_omap hecc_ck_hw = {
1849         .hw = {
1850                 .clk = &hecc_ck,
1851         },
1852         .ops            = &clkhwops_am35xx_ipss_module_wait,
1853         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
1854         .enable_bit     = AM35XX_HECC_VBUSP_CLK_SHIFT,
1855         .clkdm_name     = "core_l3_clkdm",
1856 };
1857
1858 DEFINE_STRUCT_CLK(hecc_ck, dpll3_ck_parent_names, aes2_ick_ops);
1859
1860 static struct clk hsotgusb_fck_am35xx;
1861
1862 static struct clk_hw_omap hsotgusb_fck_am35xx_hw = {
1863         .hw = {
1864                 .clk = &hsotgusb_fck_am35xx,
1865         },
1866         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
1867         .enable_bit     = AM35XX_USBOTG_FCLK_SHIFT,
1868         .clkdm_name     = "core_l3_clkdm",
1869 };
1870
1871 DEFINE_STRUCT_CLK(hsotgusb_fck_am35xx, dpll3_ck_parent_names, aes2_ick_ops);
1872
1873 static struct clk hsotgusb_ick_3430es1;
1874
1875 static struct clk_hw_omap hsotgusb_ick_3430es1_hw = {
1876         .hw = {
1877                 .clk = &hsotgusb_ick_3430es1,
1878         },
1879         .ops            = &clkhwops_iclk,
1880         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1881         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1882         .clkdm_name     = "core_l3_clkdm",
1883 };
1884
1885 DEFINE_STRUCT_CLK(hsotgusb_ick_3430es1, ipss_ick_parent_names, aes2_ick_ops);
1886
1887 static struct clk hsotgusb_ick_3430es2;
1888
1889 static struct clk_hw_omap hsotgusb_ick_3430es2_hw = {
1890         .hw = {
1891                 .clk = &hsotgusb_ick_3430es2,
1892         },
1893         .ops            = &clkhwops_omap3430es2_iclk_hsotgusb_wait,
1894         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1895         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1896         .clkdm_name     = "core_l3_clkdm",
1897 };
1898
1899 DEFINE_STRUCT_CLK(hsotgusb_ick_3430es2, ipss_ick_parent_names, aes2_ick_ops);
1900
1901 static struct clk hsotgusb_ick_am35xx;
1902
1903 static struct clk_hw_omap hsotgusb_ick_am35xx_hw = {
1904         .hw = {
1905                 .clk = &hsotgusb_ick_am35xx,
1906         },
1907         .ops            = &clkhwops_am35xx_ipss_module_wait,
1908         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
1909         .enable_bit     = AM35XX_USBOTG_VBUSP_CLK_SHIFT,
1910         .clkdm_name     = "core_l3_clkdm",
1911 };
1912
1913 DEFINE_STRUCT_CLK(hsotgusb_ick_am35xx, emac_ick_parent_names, aes2_ick_ops);
1914
1915 static struct clk i2c1_fck;
1916
1917 static struct clk_hw_omap i2c1_fck_hw = {
1918         .hw = {
1919                 .clk = &i2c1_fck,
1920         },
1921         .ops            = &clkhwops_wait,
1922         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1923         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1924         .clkdm_name     = "core_l4_clkdm",
1925 };
1926
1927 DEFINE_STRUCT_CLK(i2c1_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
1928
1929 static struct clk i2c1_ick;
1930
1931 static struct clk_hw_omap i2c1_ick_hw = {
1932         .hw = {
1933                 .clk = &i2c1_ick,
1934         },
1935         .ops            = &clkhwops_iclk_wait,
1936         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1937         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1938         .clkdm_name     = "core_l4_clkdm",
1939 };
1940
1941 DEFINE_STRUCT_CLK(i2c1_ick, aes2_ick_parent_names, aes2_ick_ops);
1942
1943 static struct clk i2c2_fck;
1944
1945 static struct clk_hw_omap i2c2_fck_hw = {
1946         .hw = {
1947                 .clk = &i2c2_fck,
1948         },
1949         .ops            = &clkhwops_wait,
1950         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1951         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1952         .clkdm_name     = "core_l4_clkdm",
1953 };
1954
1955 DEFINE_STRUCT_CLK(i2c2_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
1956
1957 static struct clk i2c2_ick;
1958
1959 static struct clk_hw_omap i2c2_ick_hw = {
1960         .hw = {
1961                 .clk = &i2c2_ick,
1962         },
1963         .ops            = &clkhwops_iclk_wait,
1964         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1965         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1966         .clkdm_name     = "core_l4_clkdm",
1967 };
1968
1969 DEFINE_STRUCT_CLK(i2c2_ick, aes2_ick_parent_names, aes2_ick_ops);
1970
1971 static struct clk i2c3_fck;
1972
1973 static struct clk_hw_omap i2c3_fck_hw = {
1974         .hw = {
1975                 .clk = &i2c3_fck,
1976         },
1977         .ops            = &clkhwops_wait,
1978         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1979         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1980         .clkdm_name     = "core_l4_clkdm",
1981 };
1982
1983 DEFINE_STRUCT_CLK(i2c3_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
1984
1985 static struct clk i2c3_ick;
1986
1987 static struct clk_hw_omap i2c3_ick_hw = {
1988         .hw = {
1989                 .clk = &i2c3_ick,
1990         },
1991         .ops            = &clkhwops_iclk_wait,
1992         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1993         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1994         .clkdm_name     = "core_l4_clkdm",
1995 };
1996
1997 DEFINE_STRUCT_CLK(i2c3_ick, aes2_ick_parent_names, aes2_ick_ops);
1998
1999 static struct clk icr_ick;
2000
2001 static struct clk_hw_omap icr_ick_hw = {
2002         .hw = {
2003                 .clk = &icr_ick,
2004         },
2005         .ops            = &clkhwops_iclk_wait,
2006         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2007         .enable_bit     = OMAP3430_EN_ICR_SHIFT,
2008         .clkdm_name     = "core_l4_clkdm",
2009 };
2010
2011 DEFINE_STRUCT_CLK(icr_ick, aes2_ick_parent_names, aes2_ick_ops);
2012
2013 static struct clk iva2_ck;
2014
2015 static const char *iva2_ck_parent_names[] = {
2016         "dpll2_m2_ck",
2017 };
2018
2019 static struct clk_hw_omap iva2_ck_hw = {
2020         .hw = {
2021                 .clk = &iva2_ck,
2022         },
2023         .ops            = &clkhwops_wait,
2024         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
2025         .enable_bit     = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
2026         .clkdm_name     = "iva2_clkdm",
2027 };
2028
2029 DEFINE_STRUCT_CLK(iva2_ck, iva2_ck_parent_names, aes2_ick_ops);
2030
2031 static struct clk mad2d_ick;
2032
2033 static struct clk_hw_omap mad2d_ick_hw = {
2034         .hw = {
2035                 .clk = &mad2d_ick,
2036         },
2037         .ops            = &clkhwops_iclk_wait,
2038         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
2039         .enable_bit     = OMAP3430_EN_MAD2D_SHIFT,
2040         .clkdm_name     = "d2d_clkdm",
2041 };
2042
2043 DEFINE_STRUCT_CLK(mad2d_ick, core_l3_ick_parent_names, aes2_ick_ops);
2044
2045 static struct clk mailboxes_ick;
2046
2047 static struct clk_hw_omap mailboxes_ick_hw = {
2048         .hw = {
2049                 .clk = &mailboxes_ick,
2050         },
2051         .ops            = &clkhwops_iclk_wait,
2052         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2053         .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
2054         .clkdm_name     = "core_l4_clkdm",
2055 };
2056
2057 DEFINE_STRUCT_CLK(mailboxes_ick, aes2_ick_parent_names, aes2_ick_ops);
2058
2059 static const struct clksel_rate common_mcbsp_96m_rates[] = {
2060         { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
2061         { .div = 0 }
2062 };
2063
2064 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
2065         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
2066         { .div = 0 }
2067 };
2068
2069 static const struct clksel mcbsp_15_clksel[] = {
2070         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
2071         { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
2072         { .parent = NULL },
2073 };
2074
2075 static const char *mcbsp1_fck_parent_names[] = {
2076         "core_96m_fck", "mcbsp_clks",
2077 };
2078
2079 DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "core_l4_clkdm", mcbsp_15_clksel,
2080                          OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2081                          OMAP2_MCBSP1_CLKS_MASK,
2082                          OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2083                          OMAP3430_EN_MCBSP1_SHIFT, &clkhwops_wait,
2084                          mcbsp1_fck_parent_names, clkout2_src_ck_ops);
2085
2086 static struct clk mcbsp1_ick;
2087
2088 static struct clk_hw_omap mcbsp1_ick_hw = {
2089         .hw = {
2090                 .clk = &mcbsp1_ick,
2091         },
2092         .ops            = &clkhwops_iclk_wait,
2093         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2094         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
2095         .clkdm_name     = "core_l4_clkdm",
2096 };
2097
2098 DEFINE_STRUCT_CLK(mcbsp1_ick, aes2_ick_parent_names, aes2_ick_ops);
2099
2100 static struct clk per_96m_fck;
2101
2102 DEFINE_STRUCT_CLK_HW_OMAP(per_96m_fck, "per_clkdm");
2103 DEFINE_STRUCT_CLK(per_96m_fck, cm_96m_fck_parent_names, core_l4_ick_ops);
2104
2105 static const struct clksel mcbsp_234_clksel[] = {
2106         { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
2107         { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
2108         { .parent = NULL },
2109 };
2110
2111 static const char *mcbsp2_fck_parent_names[] = {
2112         "per_96m_fck", "mcbsp_clks",
2113 };
2114
2115 DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "per_clkdm", mcbsp_234_clksel,
2116                          OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2117                          OMAP2_MCBSP2_CLKS_MASK,
2118                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2119                          OMAP3430_EN_MCBSP2_SHIFT, &clkhwops_wait,
2120                          mcbsp2_fck_parent_names, clkout2_src_ck_ops);
2121
2122 static struct clk mcbsp2_ick;
2123
2124 static struct clk_hw_omap mcbsp2_ick_hw = {
2125         .hw = {
2126                 .clk = &mcbsp2_ick,
2127         },
2128         .ops            = &clkhwops_iclk_wait,
2129         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2130         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2131         .clkdm_name     = "per_clkdm",
2132 };
2133
2134 DEFINE_STRUCT_CLK(mcbsp2_ick, gpio2_ick_parent_names, aes2_ick_ops);
2135
2136 DEFINE_CLK_OMAP_MUX_GATE(mcbsp3_fck, "per_clkdm", mcbsp_234_clksel,
2137                          OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2138                          OMAP2_MCBSP3_CLKS_MASK,
2139                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2140                          OMAP3430_EN_MCBSP3_SHIFT, &clkhwops_wait,
2141                          mcbsp2_fck_parent_names, clkout2_src_ck_ops);
2142
2143 static struct clk mcbsp3_ick;
2144
2145 static struct clk_hw_omap mcbsp3_ick_hw = {
2146         .hw = {
2147                 .clk = &mcbsp3_ick,
2148         },
2149         .ops            = &clkhwops_iclk_wait,
2150         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2151         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2152         .clkdm_name     = "per_clkdm",
2153 };
2154
2155 DEFINE_STRUCT_CLK(mcbsp3_ick, gpio2_ick_parent_names, aes2_ick_ops);
2156
2157 DEFINE_CLK_OMAP_MUX_GATE(mcbsp4_fck, "per_clkdm", mcbsp_234_clksel,
2158                          OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2159                          OMAP2_MCBSP4_CLKS_MASK,
2160                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2161                          OMAP3430_EN_MCBSP4_SHIFT, &clkhwops_wait,
2162                          mcbsp2_fck_parent_names, clkout2_src_ck_ops);
2163
2164 static struct clk mcbsp4_ick;
2165
2166 static struct clk_hw_omap mcbsp4_ick_hw = {
2167         .hw = {
2168                 .clk = &mcbsp4_ick,
2169         },
2170         .ops            = &clkhwops_iclk_wait,
2171         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2172         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2173         .clkdm_name     = "per_clkdm",
2174 };
2175
2176 DEFINE_STRUCT_CLK(mcbsp4_ick, gpio2_ick_parent_names, aes2_ick_ops);
2177
2178 DEFINE_CLK_OMAP_MUX_GATE(mcbsp5_fck, "core_l4_clkdm", mcbsp_15_clksel,
2179                          OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2180                          OMAP2_MCBSP5_CLKS_MASK,
2181                          OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2182                          OMAP3430_EN_MCBSP5_SHIFT, &clkhwops_wait,
2183                          mcbsp1_fck_parent_names, clkout2_src_ck_ops);
2184
2185 static struct clk mcbsp5_ick;
2186
2187 static struct clk_hw_omap mcbsp5_ick_hw = {
2188         .hw = {
2189                 .clk = &mcbsp5_ick,
2190         },
2191         .ops            = &clkhwops_iclk_wait,
2192         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2193         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
2194         .clkdm_name     = "core_l4_clkdm",
2195 };
2196
2197 DEFINE_STRUCT_CLK(mcbsp5_ick, aes2_ick_parent_names, aes2_ick_ops);
2198
2199 static struct clk mcspi1_fck;
2200
2201 static struct clk_hw_omap mcspi1_fck_hw = {
2202         .hw = {
2203                 .clk = &mcspi1_fck,
2204         },
2205         .ops            = &clkhwops_wait,
2206         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2207         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
2208         .clkdm_name     = "core_l4_clkdm",
2209 };
2210
2211 DEFINE_STRUCT_CLK(mcspi1_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2212
2213 static struct clk mcspi1_ick;
2214
2215 static struct clk_hw_omap mcspi1_ick_hw = {
2216         .hw = {
2217                 .clk = &mcspi1_ick,
2218         },
2219         .ops            = &clkhwops_iclk_wait,
2220         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2221         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
2222         .clkdm_name     = "core_l4_clkdm",
2223 };
2224
2225 DEFINE_STRUCT_CLK(mcspi1_ick, aes2_ick_parent_names, aes2_ick_ops);
2226
2227 static struct clk mcspi2_fck;
2228
2229 static struct clk_hw_omap mcspi2_fck_hw = {
2230         .hw = {
2231                 .clk = &mcspi2_fck,
2232         },
2233         .ops            = &clkhwops_wait,
2234         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2235         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
2236         .clkdm_name     = "core_l4_clkdm",
2237 };
2238
2239 DEFINE_STRUCT_CLK(mcspi2_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2240
2241 static struct clk mcspi2_ick;
2242
2243 static struct clk_hw_omap mcspi2_ick_hw = {
2244         .hw = {
2245                 .clk = &mcspi2_ick,
2246         },
2247         .ops            = &clkhwops_iclk_wait,
2248         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2249         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
2250         .clkdm_name     = "core_l4_clkdm",
2251 };
2252
2253 DEFINE_STRUCT_CLK(mcspi2_ick, aes2_ick_parent_names, aes2_ick_ops);
2254
2255 static struct clk mcspi3_fck;
2256
2257 static struct clk_hw_omap mcspi3_fck_hw = {
2258         .hw = {
2259                 .clk = &mcspi3_fck,
2260         },
2261         .ops            = &clkhwops_wait,
2262         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2263         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
2264         .clkdm_name     = "core_l4_clkdm",
2265 };
2266
2267 DEFINE_STRUCT_CLK(mcspi3_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2268
2269 static struct clk mcspi3_ick;
2270
2271 static struct clk_hw_omap mcspi3_ick_hw = {
2272         .hw = {
2273                 .clk = &mcspi3_ick,
2274         },
2275         .ops            = &clkhwops_iclk_wait,
2276         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2277         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
2278         .clkdm_name     = "core_l4_clkdm",
2279 };
2280
2281 DEFINE_STRUCT_CLK(mcspi3_ick, aes2_ick_parent_names, aes2_ick_ops);
2282
2283 static struct clk mcspi4_fck;
2284
2285 static struct clk_hw_omap mcspi4_fck_hw = {
2286         .hw = {
2287                 .clk = &mcspi4_fck,
2288         },
2289         .ops            = &clkhwops_wait,
2290         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2291         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
2292         .clkdm_name     = "core_l4_clkdm",
2293 };
2294
2295 DEFINE_STRUCT_CLK(mcspi4_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2296
2297 static struct clk mcspi4_ick;
2298
2299 static struct clk_hw_omap mcspi4_ick_hw = {
2300         .hw = {
2301                 .clk = &mcspi4_ick,
2302         },
2303         .ops            = &clkhwops_iclk_wait,
2304         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2305         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
2306         .clkdm_name     = "core_l4_clkdm",
2307 };
2308
2309 DEFINE_STRUCT_CLK(mcspi4_ick, aes2_ick_parent_names, aes2_ick_ops);
2310
2311 static struct clk mmchs1_fck;
2312
2313 static struct clk_hw_omap mmchs1_fck_hw = {
2314         .hw = {
2315                 .clk = &mmchs1_fck,
2316         },
2317         .ops            = &clkhwops_wait,
2318         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2319         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
2320         .clkdm_name     = "core_l4_clkdm",
2321 };
2322
2323 DEFINE_STRUCT_CLK(mmchs1_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
2324
2325 static struct clk mmchs1_ick;
2326
2327 static struct clk_hw_omap mmchs1_ick_hw = {
2328         .hw = {
2329                 .clk = &mmchs1_ick,
2330         },
2331         .ops            = &clkhwops_iclk_wait,
2332         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2333         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
2334         .clkdm_name     = "core_l4_clkdm",
2335 };
2336
2337 DEFINE_STRUCT_CLK(mmchs1_ick, aes2_ick_parent_names, aes2_ick_ops);
2338
2339 static struct clk mmchs2_fck;
2340
2341 static struct clk_hw_omap mmchs2_fck_hw = {
2342         .hw = {
2343                 .clk = &mmchs2_fck,
2344         },
2345         .ops            = &clkhwops_wait,
2346         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2347         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
2348         .clkdm_name     = "core_l4_clkdm",
2349 };
2350
2351 DEFINE_STRUCT_CLK(mmchs2_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
2352
2353 static struct clk mmchs2_ick;
2354
2355 static struct clk_hw_omap mmchs2_ick_hw = {
2356         .hw = {
2357                 .clk = &mmchs2_ick,
2358         },
2359         .ops            = &clkhwops_iclk_wait,
2360         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2361         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
2362         .clkdm_name     = "core_l4_clkdm",
2363 };
2364
2365 DEFINE_STRUCT_CLK(mmchs2_ick, aes2_ick_parent_names, aes2_ick_ops);
2366
2367 static struct clk mmchs3_fck;
2368
2369 static struct clk_hw_omap mmchs3_fck_hw = {
2370         .hw = {
2371                 .clk = &mmchs3_fck,
2372         },
2373         .ops            = &clkhwops_wait,
2374         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2375         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
2376         .clkdm_name     = "core_l4_clkdm",
2377 };
2378
2379 DEFINE_STRUCT_CLK(mmchs3_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
2380
2381 static struct clk mmchs3_ick;
2382
2383 static struct clk_hw_omap mmchs3_ick_hw = {
2384         .hw = {
2385                 .clk = &mmchs3_ick,
2386         },
2387         .ops            = &clkhwops_iclk_wait,
2388         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2389         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
2390         .clkdm_name     = "core_l4_clkdm",
2391 };
2392
2393 DEFINE_STRUCT_CLK(mmchs3_ick, aes2_ick_parent_names, aes2_ick_ops);
2394
2395 static struct clk modem_fck;
2396
2397 static struct clk_hw_omap modem_fck_hw = {
2398         .hw = {
2399                 .clk = &modem_fck,
2400         },
2401         .ops            = &clkhwops_iclk_wait,
2402         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2403         .enable_bit     = OMAP3430_EN_MODEM_SHIFT,
2404         .clkdm_name     = "d2d_clkdm",
2405 };
2406
2407 DEFINE_STRUCT_CLK(modem_fck, dpll3_ck_parent_names, aes2_ick_ops);
2408
2409 static struct clk mspro_fck;
2410
2411 static struct clk_hw_omap mspro_fck_hw = {
2412         .hw = {
2413                 .clk = &mspro_fck,
2414         },
2415         .ops            = &clkhwops_wait,
2416         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2417         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
2418         .clkdm_name     = "core_l4_clkdm",
2419 };
2420
2421 DEFINE_STRUCT_CLK(mspro_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
2422
2423 static struct clk mspro_ick;
2424
2425 static struct clk_hw_omap mspro_ick_hw = {
2426         .hw = {
2427                 .clk = &mspro_ick,
2428         },
2429         .ops            = &clkhwops_iclk_wait,
2430         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2431         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
2432         .clkdm_name     = "core_l4_clkdm",
2433 };
2434
2435 DEFINE_STRUCT_CLK(mspro_ick, aes2_ick_parent_names, aes2_ick_ops);
2436
2437 static struct clk omap_192m_alwon_fck;
2438
2439 DEFINE_STRUCT_CLK_HW_OMAP(omap_192m_alwon_fck, NULL);
2440 DEFINE_STRUCT_CLK(omap_192m_alwon_fck, omap_96m_alwon_fck_parent_names,
2441                   core_ck_ops);
2442
2443 static struct clk omap_32ksync_ick;
2444
2445 static struct clk_hw_omap omap_32ksync_ick_hw = {
2446         .hw = {
2447                 .clk = &omap_32ksync_ick,
2448         },
2449         .ops            = &clkhwops_iclk_wait,
2450         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2451         .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
2452         .clkdm_name     = "wkup_clkdm",
2453 };
2454
2455 DEFINE_STRUCT_CLK(omap_32ksync_ick, gpio1_ick_parent_names, aes2_ick_ops);
2456
2457 static const struct clksel_rate omap_96m_alwon_fck_rates[] = {
2458         { .div = 1, .val = 1, .flags = RATE_IN_36XX },
2459         { .div = 2, .val = 2, .flags = RATE_IN_36XX },
2460         { .div = 0 }
2461 };
2462
2463 static const struct clksel omap_96m_alwon_fck_clksel[] = {
2464         { .parent = &omap_192m_alwon_fck, .rates = omap_96m_alwon_fck_rates },
2465         { .parent = NULL }
2466 };
2467
2468 static struct clk omap_96m_alwon_fck_3630;
2469
2470 static const char *omap_96m_alwon_fck_3630_parent_names[] = {
2471         "omap_192m_alwon_fck",
2472 };
2473
2474 static const struct clk_ops omap_96m_alwon_fck_3630_ops = {
2475         .set_rate       = &omap2_clksel_set_rate,
2476         .recalc_rate    = &omap2_clksel_recalc,
2477         .round_rate     = &omap2_clksel_round_rate,
2478 };
2479
2480 static struct clk_hw_omap omap_96m_alwon_fck_3630_hw = {
2481         .hw = {
2482                 .clk = &omap_96m_alwon_fck_3630,
2483         },
2484         .clksel         = omap_96m_alwon_fck_clksel,
2485         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2486         .clksel_mask    = OMAP3630_CLKSEL_96M_MASK,
2487 };
2488
2489 static struct clk omap_96m_alwon_fck_3630 = {
2490         .name   = "omap_96m_alwon_fck",
2491         .hw     = &omap_96m_alwon_fck_3630_hw.hw,
2492         .parent_names   = omap_96m_alwon_fck_3630_parent_names,
2493         .num_parents    = ARRAY_SIZE(omap_96m_alwon_fck_3630_parent_names),
2494         .ops    = &omap_96m_alwon_fck_3630_ops,
2495 };
2496
2497 static struct clk omapctrl_ick;
2498
2499 static struct clk_hw_omap omapctrl_ick_hw = {
2500         .hw = {
2501                 .clk = &omapctrl_ick,
2502         },
2503         .ops            = &clkhwops_iclk_wait,
2504         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2505         .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
2506         .flags          = ENABLE_ON_INIT,
2507         .clkdm_name     = "core_l4_clkdm",
2508 };
2509
2510 DEFINE_STRUCT_CLK(omapctrl_ick, aes2_ick_parent_names, aes2_ick_ops);
2511
2512 DEFINE_CLK_DIVIDER(pclk_fck, "emu_src_ck", &emu_src_ck, 0x0,
2513                    OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2514                    OMAP3430_CLKSEL_PCLK_SHIFT, OMAP3430_CLKSEL_PCLK_WIDTH,
2515                    CLK_DIVIDER_ONE_BASED, NULL);
2516
2517 DEFINE_CLK_DIVIDER(pclkx2_fck, "emu_src_ck", &emu_src_ck, 0x0,
2518                    OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2519                    OMAP3430_CLKSEL_PCLKX2_SHIFT, OMAP3430_CLKSEL_PCLKX2_WIDTH,
2520                    CLK_DIVIDER_ONE_BASED, NULL);
2521
2522 static struct clk per_48m_fck;
2523
2524 DEFINE_STRUCT_CLK_HW_OMAP(per_48m_fck, "per_clkdm");
2525 DEFINE_STRUCT_CLK(per_48m_fck, core_48m_fck_parent_names, core_l4_ick_ops);
2526
2527 static struct clk security_l3_ick;
2528
2529 DEFINE_STRUCT_CLK_HW_OMAP(security_l3_ick, NULL);
2530 DEFINE_STRUCT_CLK(security_l3_ick, core_l3_ick_parent_names, core_ck_ops);
2531
2532 static struct clk pka_ick;
2533
2534 static const char *pka_ick_parent_names[] = {
2535         "security_l3_ick",
2536 };
2537
2538 static struct clk_hw_omap pka_ick_hw = {
2539         .hw = {
2540                 .clk = &pka_ick,
2541         },
2542         .ops            = &clkhwops_iclk_wait,
2543         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2544         .enable_bit     = OMAP3430_EN_PKA_SHIFT,
2545 };
2546
2547 DEFINE_STRUCT_CLK(pka_ick, pka_ick_parent_names, aes1_ick_ops);
2548
2549 DEFINE_CLK_DIVIDER(rm_ick, "l4_ick", &l4_ick, 0x0,
2550                    OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2551                    OMAP3430_CLKSEL_RM_SHIFT, OMAP3430_CLKSEL_RM_WIDTH,
2552                    CLK_DIVIDER_ONE_BASED, NULL);
2553
2554 static struct clk rng_ick;
2555
2556 static struct clk_hw_omap rng_ick_hw = {
2557         .hw = {
2558                 .clk = &rng_ick,
2559         },
2560         .ops            = &clkhwops_iclk_wait,
2561         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2562         .enable_bit     = OMAP3430_EN_RNG_SHIFT,
2563 };
2564
2565 DEFINE_STRUCT_CLK(rng_ick, aes1_ick_parent_names, aes1_ick_ops);
2566
2567 static struct clk sad2d_ick;
2568
2569 static struct clk_hw_omap sad2d_ick_hw = {
2570         .hw = {
2571                 .clk = &sad2d_ick,
2572         },
2573         .ops            = &clkhwops_iclk_wait,
2574         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2575         .enable_bit     = OMAP3430_EN_SAD2D_SHIFT,
2576         .clkdm_name     = "d2d_clkdm",
2577 };
2578
2579 DEFINE_STRUCT_CLK(sad2d_ick, core_l3_ick_parent_names, aes2_ick_ops);
2580
2581 static struct clk sdrc_ick;
2582
2583 static struct clk_hw_omap sdrc_ick_hw = {
2584         .hw = {
2585                 .clk = &sdrc_ick,
2586         },
2587         .ops            = &clkhwops_wait,
2588         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2589         .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
2590         .flags          = ENABLE_ON_INIT,
2591         .clkdm_name     = "core_l3_clkdm",
2592 };
2593
2594 DEFINE_STRUCT_CLK(sdrc_ick, ipss_ick_parent_names, aes2_ick_ops);
2595
2596 static const struct clksel_rate sgx_core_rates[] = {
2597         { .div = 2, .val = 5, .flags = RATE_IN_36XX },
2598         { .div = 3, .val = 0, .flags = RATE_IN_3XXX },
2599         { .div = 4, .val = 1, .flags = RATE_IN_3XXX },
2600         { .div = 6, .val = 2, .flags = RATE_IN_3XXX },
2601         { .div = 0 }
2602 };
2603
2604 static const struct clksel_rate sgx_96m_rates[] = {
2605         { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
2606         { .div = 0 }
2607 };
2608
2609 static const struct clksel_rate sgx_192m_rates[] = {
2610         { .div = 1, .val = 4, .flags = RATE_IN_36XX },
2611         { .div = 0 }
2612 };
2613
2614 static const struct clksel_rate sgx_corex2_rates[] = {
2615         { .div = 3, .val = 6, .flags = RATE_IN_36XX },
2616         { .div = 5, .val = 7, .flags = RATE_IN_36XX },
2617         { .div = 0 }
2618 };
2619
2620 static const struct clksel sgx_clksel[] = {
2621         { .parent = &core_ck, .rates = sgx_core_rates },
2622         { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
2623         { .parent = &omap_192m_alwon_fck, .rates = sgx_192m_rates },
2624         { .parent = &corex2_fck, .rates = sgx_corex2_rates },
2625         { .parent = NULL },
2626 };
2627
2628 static const char *sgx_fck_parent_names[] = {
2629         "core_ck", "cm_96m_fck", "omap_192m_alwon_fck", "corex2_fck",
2630 };
2631
2632 static struct clk sgx_fck;
2633
2634 static const struct clk_ops sgx_fck_ops = {
2635         .init           = &omap2_init_clk_clkdm,
2636         .enable         = &omap2_dflt_clk_enable,
2637         .disable        = &omap2_dflt_clk_disable,
2638         .is_enabled     = &omap2_dflt_clk_is_enabled,
2639         .recalc_rate    = &omap2_clksel_recalc,
2640         .set_rate       = &omap2_clksel_set_rate,
2641         .round_rate     = &omap2_clksel_round_rate,
2642         .get_parent     = &omap2_clksel_find_parent_index,
2643         .set_parent     = &omap2_clksel_set_parent,
2644 };
2645
2646 DEFINE_CLK_OMAP_MUX_GATE(sgx_fck, "sgx_clkdm", sgx_clksel,
2647                          OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
2648                          OMAP3430ES2_CLKSEL_SGX_MASK,
2649                          OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
2650                          OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
2651                          &clkhwops_wait, sgx_fck_parent_names, sgx_fck_ops);
2652
2653 static struct clk sgx_ick;
2654
2655 static struct clk_hw_omap sgx_ick_hw = {
2656         .hw = {
2657                 .clk = &sgx_ick,
2658         },
2659         .ops            = &clkhwops_wait,
2660         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
2661         .enable_bit     = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
2662         .clkdm_name     = "sgx_clkdm",
2663 };
2664
2665 DEFINE_STRUCT_CLK(sgx_ick, core_l3_ick_parent_names, aes2_ick_ops);
2666
2667 static struct clk sha11_ick;
2668
2669 static struct clk_hw_omap sha11_ick_hw = {
2670         .hw = {
2671                 .clk = &sha11_ick,
2672         },
2673         .ops            = &clkhwops_iclk_wait,
2674         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2675         .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
2676 };
2677
2678 DEFINE_STRUCT_CLK(sha11_ick, aes1_ick_parent_names, aes1_ick_ops);
2679
2680 static struct clk sha12_ick;
2681
2682 static struct clk_hw_omap sha12_ick_hw = {
2683         .hw = {
2684                 .clk = &sha12_ick,
2685         },
2686         .ops            = &clkhwops_iclk_wait,
2687         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2688         .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
2689         .clkdm_name     = "core_l4_clkdm",
2690 };
2691
2692 DEFINE_STRUCT_CLK(sha12_ick, aes2_ick_parent_names, aes2_ick_ops);
2693
2694 static struct clk sr1_fck;
2695
2696 static struct clk_hw_omap sr1_fck_hw = {
2697         .hw = {
2698                 .clk = &sr1_fck,
2699         },
2700         .ops            = &clkhwops_wait,
2701         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2702         .enable_bit     = OMAP3430_EN_SR1_SHIFT,
2703         .clkdm_name     = "wkup_clkdm",
2704 };
2705
2706 DEFINE_STRUCT_CLK(sr1_fck, dpll3_ck_parent_names, aes2_ick_ops);
2707
2708 static struct clk sr2_fck;
2709
2710 static struct clk_hw_omap sr2_fck_hw = {
2711         .hw = {
2712                 .clk = &sr2_fck,
2713         },
2714         .ops            = &clkhwops_wait,
2715         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2716         .enable_bit     = OMAP3430_EN_SR2_SHIFT,
2717         .clkdm_name     = "wkup_clkdm",
2718 };
2719
2720 DEFINE_STRUCT_CLK(sr2_fck, dpll3_ck_parent_names, aes2_ick_ops);
2721
2722 static struct clk sr_l4_ick;
2723
2724 DEFINE_STRUCT_CLK_HW_OMAP(sr_l4_ick, "core_l4_clkdm");
2725 DEFINE_STRUCT_CLK(sr_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops);
2726
2727 static struct clk ssi_l4_ick;
2728
2729 DEFINE_STRUCT_CLK_HW_OMAP(ssi_l4_ick, "core_l4_clkdm");
2730 DEFINE_STRUCT_CLK(ssi_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops);
2731
2732 static struct clk ssi_ick_3430es1;
2733
2734 static const char *ssi_ick_3430es1_parent_names[] = {
2735         "ssi_l4_ick",
2736 };
2737
2738 static struct clk_hw_omap ssi_ick_3430es1_hw = {
2739         .hw = {
2740                 .clk = &ssi_ick_3430es1,
2741         },
2742         .ops            = &clkhwops_iclk,
2743         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2744         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
2745         .clkdm_name     = "core_l4_clkdm",
2746 };
2747
2748 DEFINE_STRUCT_CLK(ssi_ick_3430es1, ssi_ick_3430es1_parent_names, aes2_ick_ops);
2749
2750 static struct clk ssi_ick_3430es2;
2751
2752 static struct clk_hw_omap ssi_ick_3430es2_hw = {
2753         .hw = {
2754                 .clk = &ssi_ick_3430es2,
2755         },
2756         .ops            = &clkhwops_omap3430es2_iclk_ssi_wait,
2757         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2758         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
2759         .clkdm_name     = "core_l4_clkdm",
2760 };
2761
2762 DEFINE_STRUCT_CLK(ssi_ick_3430es2, ssi_ick_3430es1_parent_names, aes2_ick_ops);
2763
2764 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
2765         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
2766         { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
2767         { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
2768         { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
2769         { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
2770         { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
2771         { .div = 0 }
2772 };
2773
2774 static const struct clksel ssi_ssr_clksel[] = {
2775         { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
2776         { .parent = NULL },
2777 };
2778
2779 static const char *ssi_ssr_fck_3430es1_parent_names[] = {
2780         "corex2_fck",
2781 };
2782
2783 static const struct clk_ops ssi_ssr_fck_3430es1_ops = {
2784         .init           = &omap2_init_clk_clkdm,
2785         .enable         = &omap2_dflt_clk_enable,
2786         .disable        = &omap2_dflt_clk_disable,
2787         .is_enabled     = &omap2_dflt_clk_is_enabled,
2788         .recalc_rate    = &omap2_clksel_recalc,
2789         .set_rate       = &omap2_clksel_set_rate,
2790         .round_rate     = &omap2_clksel_round_rate,
2791 };
2792
2793 DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_fck_3430es1, "core_l4_clkdm",
2794                          ssi_ssr_clksel, OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2795                          OMAP3430_CLKSEL_SSI_MASK,
2796                          OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2797                          OMAP3430_EN_SSI_SHIFT,
2798                          NULL, ssi_ssr_fck_3430es1_parent_names,
2799                          ssi_ssr_fck_3430es1_ops);
2800
2801 DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_fck_3430es2, "core_l4_clkdm",
2802                          ssi_ssr_clksel, OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2803                          OMAP3430_CLKSEL_SSI_MASK,
2804                          OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2805                          OMAP3430_EN_SSI_SHIFT,
2806                          NULL, ssi_ssr_fck_3430es1_parent_names,
2807                          ssi_ssr_fck_3430es1_ops);
2808
2809 DEFINE_CLK_FIXED_FACTOR(ssi_sst_fck_3430es1, "ssi_ssr_fck_3430es1",
2810                         &ssi_ssr_fck_3430es1, 0x0, 1, 2);
2811
2812 DEFINE_CLK_FIXED_FACTOR(ssi_sst_fck_3430es2, "ssi_ssr_fck_3430es2",
2813                         &ssi_ssr_fck_3430es2, 0x0, 1, 2);
2814
2815 static struct clk sys_clkout1;
2816
2817 static const char *sys_clkout1_parent_names[] = {
2818         "osc_sys_ck",
2819 };
2820
2821 static struct clk_hw_omap sys_clkout1_hw = {
2822         .hw = {
2823                 .clk = &sys_clkout1,
2824         },
2825         .enable_reg     = OMAP3430_PRM_CLKOUT_CTRL,
2826         .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
2827 };
2828
2829 DEFINE_STRUCT_CLK(sys_clkout1, sys_clkout1_parent_names, aes1_ick_ops);
2830
2831 DEFINE_CLK_DIVIDER(sys_clkout2, "clkout2_src_ck", &clkout2_src_ck, 0x0,
2832                    OMAP3430_CM_CLKOUT_CTRL, OMAP3430_CLKOUT2_DIV_SHIFT,
2833                    OMAP3430_CLKOUT2_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
2834
2835 DEFINE_CLK_MUX(traceclk_src_fck, emu_src_ck_parent_names, NULL, 0x0,
2836                OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2837                OMAP3430_TRACE_MUX_CTRL_SHIFT, OMAP3430_TRACE_MUX_CTRL_WIDTH,
2838                0x0, NULL);
2839
2840 DEFINE_CLK_DIVIDER(traceclk_fck, "traceclk_src_fck", &traceclk_src_fck, 0x0,
2841                    OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2842                    OMAP3430_CLKSEL_TRACECLK_SHIFT,
2843                    OMAP3430_CLKSEL_TRACECLK_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
2844
2845 static struct clk ts_fck;
2846
2847 static struct clk_hw_omap ts_fck_hw = {
2848         .hw = {
2849                 .clk = &ts_fck,
2850         },
2851         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
2852         .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
2853         .clkdm_name     = "core_l4_clkdm",
2854 };
2855
2856 DEFINE_STRUCT_CLK(ts_fck, wkup_32k_fck_parent_names, aes2_ick_ops);
2857
2858 static struct clk uart1_fck;
2859
2860 static struct clk_hw_omap uart1_fck_hw = {
2861         .hw = {
2862                 .clk = &uart1_fck,
2863         },
2864         .ops            = &clkhwops_wait,
2865         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2866         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
2867         .clkdm_name     = "core_l4_clkdm",
2868 };
2869
2870 DEFINE_STRUCT_CLK(uart1_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2871
2872 static struct clk uart1_ick;
2873
2874 static struct clk_hw_omap uart1_ick_hw = {
2875         .hw = {
2876                 .clk = &uart1_ick,
2877         },
2878         .ops            = &clkhwops_iclk_wait,
2879         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2880         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
2881         .clkdm_name     = "core_l4_clkdm",
2882 };
2883
2884 DEFINE_STRUCT_CLK(uart1_ick, aes2_ick_parent_names, aes2_ick_ops);
2885
2886 static struct clk uart2_fck;
2887
2888 static struct clk_hw_omap uart2_fck_hw = {
2889         .hw = {
2890                 .clk = &uart2_fck,
2891         },
2892         .ops            = &clkhwops_wait,
2893         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2894         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
2895         .clkdm_name     = "core_l4_clkdm",
2896 };
2897
2898 DEFINE_STRUCT_CLK(uart2_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2899
2900 static struct clk uart2_ick;
2901
2902 static struct clk_hw_omap uart2_ick_hw = {
2903         .hw = {
2904                 .clk = &uart2_ick,
2905         },
2906         .ops            = &clkhwops_iclk_wait,
2907         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2908         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
2909         .clkdm_name     = "core_l4_clkdm",
2910 };
2911
2912 DEFINE_STRUCT_CLK(uart2_ick, aes2_ick_parent_names, aes2_ick_ops);
2913
2914 static struct clk uart3_fck;
2915
2916 static const char *uart3_fck_parent_names[] = {
2917         "per_48m_fck",
2918 };
2919
2920 static struct clk_hw_omap uart3_fck_hw = {
2921         .hw = {
2922                 .clk = &uart3_fck,
2923         },
2924         .ops            = &clkhwops_wait,
2925         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2926         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2927         .clkdm_name     = "per_clkdm",
2928 };
2929
2930 DEFINE_STRUCT_CLK(uart3_fck, uart3_fck_parent_names, aes2_ick_ops);
2931
2932 static struct clk uart3_ick;
2933
2934 static struct clk_hw_omap uart3_ick_hw = {
2935         .hw = {
2936                 .clk = &uart3_ick,
2937         },
2938         .ops            = &clkhwops_iclk_wait,
2939         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2940         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2941         .clkdm_name     = "per_clkdm",
2942 };
2943
2944 DEFINE_STRUCT_CLK(uart3_ick, gpio2_ick_parent_names, aes2_ick_ops);
2945
2946 static struct clk uart4_fck;
2947
2948 static struct clk_hw_omap uart4_fck_hw = {
2949         .hw = {
2950                 .clk = &uart4_fck,
2951         },
2952         .ops            = &clkhwops_wait,
2953         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2954         .enable_bit     = OMAP3630_EN_UART4_SHIFT,
2955         .clkdm_name     = "per_clkdm",
2956 };
2957
2958 DEFINE_STRUCT_CLK(uart4_fck, uart3_fck_parent_names, aes2_ick_ops);
2959
2960 static struct clk uart4_fck_am35xx;
2961
2962 static struct clk_hw_omap uart4_fck_am35xx_hw = {
2963         .hw = {
2964                 .clk = &uart4_fck_am35xx,
2965         },
2966         .ops            = &clkhwops_wait,
2967         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2968         .enable_bit     = AM35XX_EN_UART4_SHIFT,
2969         .clkdm_name     = "core_l4_clkdm",
2970 };
2971
2972 DEFINE_STRUCT_CLK(uart4_fck_am35xx, fshostusb_fck_parent_names, aes2_ick_ops);
2973
2974 static struct clk uart4_ick;
2975
2976 static struct clk_hw_omap uart4_ick_hw = {
2977         .hw = {
2978                 .clk = &uart4_ick,
2979         },
2980         .ops            = &clkhwops_iclk_wait,
2981         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2982         .enable_bit     = OMAP3630_EN_UART4_SHIFT,
2983         .clkdm_name     = "per_clkdm",
2984 };
2985
2986 DEFINE_STRUCT_CLK(uart4_ick, gpio2_ick_parent_names, aes2_ick_ops);
2987
2988 static struct clk uart4_ick_am35xx;
2989
2990 static struct clk_hw_omap uart4_ick_am35xx_hw = {
2991         .hw = {
2992                 .clk = &uart4_ick_am35xx,
2993         },
2994         .ops            = &clkhwops_iclk_wait,
2995         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2996         .enable_bit     = AM35XX_EN_UART4_SHIFT,
2997         .clkdm_name     = "core_l4_clkdm",
2998 };
2999
3000 DEFINE_STRUCT_CLK(uart4_ick_am35xx, aes2_ick_parent_names, aes2_ick_ops);
3001
3002 static const struct clksel_rate div2_rates[] = {
3003         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
3004         { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
3005         { .div = 0 }
3006 };
3007
3008 static const struct clksel usb_l4_clksel[] = {
3009         { .parent = &l4_ick, .rates = div2_rates },
3010         { .parent = NULL },
3011 };
3012
3013 static const char *usb_l4_ick_parent_names[] = {
3014         "l4_ick",
3015 };
3016
3017 DEFINE_CLK_OMAP_MUX_GATE(usb_l4_ick, "core_l4_clkdm", usb_l4_clksel,
3018                          OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
3019                          OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
3020                          OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
3021                          OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
3022                          &clkhwops_iclk_wait, usb_l4_ick_parent_names,
3023                          ssi_ssr_fck_3430es1_ops);
3024
3025 static struct clk usbhost_120m_fck;
3026
3027 static const char *usbhost_120m_fck_parent_names[] = {
3028         "dpll5_m2_ck",
3029 };
3030
3031 static struct clk_hw_omap usbhost_120m_fck_hw = {
3032         .hw = {
3033                 .clk = &usbhost_120m_fck,
3034         },
3035         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
3036         .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
3037         .clkdm_name     = "usbhost_clkdm",
3038 };
3039
3040 DEFINE_STRUCT_CLK(usbhost_120m_fck, usbhost_120m_fck_parent_names,
3041                   aes2_ick_ops);
3042
3043 static struct clk usbhost_48m_fck;
3044
3045 static struct clk_hw_omap usbhost_48m_fck_hw = {
3046         .hw = {
3047                 .clk = &usbhost_48m_fck,
3048         },
3049         .ops            = &clkhwops_omap3430es2_dss_usbhost_wait,
3050         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
3051         .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
3052         .clkdm_name     = "usbhost_clkdm",
3053 };
3054
3055 DEFINE_STRUCT_CLK(usbhost_48m_fck, core_48m_fck_parent_names, aes2_ick_ops);
3056
3057 static struct clk usbhost_ick;
3058
3059 static struct clk_hw_omap usbhost_ick_hw = {
3060         .hw = {
3061                 .clk = &usbhost_ick,
3062         },
3063         .ops            = &clkhwops_omap3430es2_iclk_dss_usbhost_wait,
3064         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
3065         .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
3066         .clkdm_name     = "usbhost_clkdm",
3067 };
3068
3069 DEFINE_STRUCT_CLK(usbhost_ick, security_l4_ick2_parent_names, aes2_ick_ops);
3070
3071 static struct clk usbtll_fck;
3072
3073 static struct clk_hw_omap usbtll_fck_hw = {
3074         .hw = {
3075                 .clk = &usbtll_fck,
3076         },
3077         .ops            = &clkhwops_wait,
3078         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
3079         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
3080         .clkdm_name     = "core_l4_clkdm",
3081 };
3082
3083 DEFINE_STRUCT_CLK(usbtll_fck, usbhost_120m_fck_parent_names, aes2_ick_ops);
3084
3085 static struct clk usbtll_ick;
3086
3087 static struct clk_hw_omap usbtll_ick_hw = {
3088         .hw = {
3089                 .clk = &usbtll_ick,
3090         },
3091         .ops            = &clkhwops_iclk_wait,
3092         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
3093         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
3094         .clkdm_name     = "core_l4_clkdm",
3095 };
3096
3097 DEFINE_STRUCT_CLK(usbtll_ick, aes2_ick_parent_names, aes2_ick_ops);
3098
3099 static const struct clksel_rate usim_96m_rates[] = {
3100         { .div = 2, .val = 3, .flags = RATE_IN_3XXX },
3101         { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
3102         { .div = 8, .val = 5, .flags = RATE_IN_3XXX },
3103         { .div = 10, .val = 6, .flags = RATE_IN_3XXX },
3104         { .div = 0 }
3105 };
3106
3107 static const struct clksel_rate usim_120m_rates[] = {
3108         { .div = 4, .val = 7, .flags = RATE_IN_3XXX },
3109         { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
3110         { .div = 16, .val = 9, .flags = RATE_IN_3XXX },
3111         { .div = 20, .val = 10, .flags = RATE_IN_3XXX },
3112         { .div = 0 }
3113 };
3114
3115 static const struct clksel usim_clksel[] = {
3116         { .parent = &omap_96m_fck, .rates = usim_96m_rates },
3117         { .parent = &dpll5_m2_ck, .rates = usim_120m_rates },
3118         { .parent = &sys_ck, .rates = div2_rates },
3119         { .parent = NULL },
3120 };
3121
3122 static const char *usim_fck_parent_names[] = {
3123         "omap_96m_fck", "dpll5_m2_ck", "sys_ck",
3124 };
3125
3126 static struct clk usim_fck;
3127
3128 static const struct clk_ops usim_fck_ops = {
3129         .enable         = &omap2_dflt_clk_enable,
3130         .disable        = &omap2_dflt_clk_disable,
3131         .is_enabled     = &omap2_dflt_clk_is_enabled,
3132         .recalc_rate    = &omap2_clksel_recalc,
3133         .get_parent     = &omap2_clksel_find_parent_index,
3134         .set_parent     = &omap2_clksel_set_parent,
3135 };
3136
3137 DEFINE_CLK_OMAP_MUX_GATE(usim_fck, NULL, usim_clksel,
3138                          OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
3139                          OMAP3430ES2_CLKSEL_USIMOCP_MASK,
3140                          OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3141                          OMAP3430ES2_EN_USIMOCP_SHIFT, &clkhwops_wait,
3142                          usim_fck_parent_names, usim_fck_ops);
3143
3144 static struct clk usim_ick;
3145
3146 static struct clk_hw_omap usim_ick_hw = {
3147         .hw = {
3148                 .clk = &usim_ick,
3149         },
3150         .ops            = &clkhwops_iclk_wait,
3151         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
3152         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
3153         .clkdm_name     = "wkup_clkdm",
3154 };
3155
3156 DEFINE_STRUCT_CLK(usim_ick, gpio1_ick_parent_names, aes2_ick_ops);
3157
3158 static struct clk vpfe_fck;
3159
3160 static const char *vpfe_fck_parent_names[] = {
3161         "pclk_ck",
3162 };
3163
3164 static struct clk_hw_omap vpfe_fck_hw = {
3165         .hw = {
3166                 .clk = &vpfe_fck,
3167         },
3168         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3169         .enable_bit     = AM35XX_VPFE_FCLK_SHIFT,
3170 };
3171
3172 DEFINE_STRUCT_CLK(vpfe_fck, vpfe_fck_parent_names, aes1_ick_ops);
3173
3174 static struct clk vpfe_ick;
3175
3176 static struct clk_hw_omap vpfe_ick_hw = {
3177         .hw = {
3178                 .clk = &vpfe_ick,
3179         },
3180         .ops            = &clkhwops_am35xx_ipss_module_wait,
3181         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3182         .enable_bit     = AM35XX_VPFE_VBUSP_CLK_SHIFT,
3183         .clkdm_name     = "core_l3_clkdm",
3184 };
3185
3186 DEFINE_STRUCT_CLK(vpfe_ick, emac_ick_parent_names, aes2_ick_ops);
3187
3188 static struct clk wdt1_fck;
3189
3190 DEFINE_STRUCT_CLK_HW_OMAP(wdt1_fck, "wkup_clkdm");
3191 DEFINE_STRUCT_CLK(wdt1_fck, gpt12_fck_parent_names, core_l4_ick_ops);
3192
3193 static struct clk wdt1_ick;
3194
3195 static struct clk_hw_omap wdt1_ick_hw = {
3196         .hw = {
3197                 .clk = &wdt1_ick,
3198         },
3199         .ops            = &clkhwops_iclk_wait,
3200         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
3201         .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
3202         .clkdm_name     = "wkup_clkdm",
3203 };
3204
3205 DEFINE_STRUCT_CLK(wdt1_ick, gpio1_ick_parent_names, aes2_ick_ops);
3206
3207 static struct clk wdt2_fck;
3208
3209 static struct clk_hw_omap wdt2_fck_hw = {
3210         .hw = {
3211                 .clk = &wdt2_fck,
3212         },
3213         .ops            = &clkhwops_wait,
3214         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3215         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
3216         .clkdm_name     = "wkup_clkdm",
3217 };
3218
3219 DEFINE_STRUCT_CLK(wdt2_fck, gpio1_dbck_parent_names, aes2_ick_ops);
3220
3221 static struct clk wdt2_ick;
3222
3223 static struct clk_hw_omap wdt2_ick_hw = {
3224         .hw = {
3225                 .clk = &wdt2_ick,
3226         },
3227         .ops            = &clkhwops_iclk_wait,
3228         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
3229         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
3230         .clkdm_name     = "wkup_clkdm",
3231 };
3232
3233 DEFINE_STRUCT_CLK(wdt2_ick, gpio1_ick_parent_names, aes2_ick_ops);
3234
3235 static struct clk wdt3_fck;
3236
3237 static struct clk_hw_omap wdt3_fck_hw = {
3238         .hw = {
3239                 .clk = &wdt3_fck,
3240         },
3241         .ops            = &clkhwops_wait,
3242         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
3243         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
3244         .clkdm_name     = "per_clkdm",
3245 };
3246
3247 DEFINE_STRUCT_CLK(wdt3_fck, gpio2_dbck_parent_names, aes2_ick_ops);
3248
3249 static struct clk wdt3_ick;
3250
3251 static struct clk_hw_omap wdt3_ick_hw = {
3252         .hw = {
3253                 .clk = &wdt3_ick,
3254         },
3255         .ops            = &clkhwops_iclk_wait,
3256         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
3257         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
3258         .clkdm_name     = "per_clkdm",
3259 };
3260
3261 DEFINE_STRUCT_CLK(wdt3_ick, gpio2_ick_parent_names, aes2_ick_ops);
3262
3263 /*
3264  * clocks specific to omap3430es1
3265  */
3266 static struct omap_clk omap3430es1_clks[] = {
3267         CLK(NULL,       "gfx_l3_ck",    &gfx_l3_ck),
3268         CLK(NULL,       "gfx_l3_fck",   &gfx_l3_fck),
3269         CLK(NULL,       "gfx_l3_ick",   &gfx_l3_ick),
3270         CLK(NULL,       "gfx_cg1_ck",   &gfx_cg1_ck),
3271         CLK(NULL,       "gfx_cg2_ck",   &gfx_cg2_ck),
3272         CLK(NULL,       "d2d_26m_fck",  &d2d_26m_fck),
3273         CLK(NULL,       "fshostusb_fck", &fshostusb_fck),
3274         CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es1),
3275         CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es1),
3276         CLK("musb-omap2430",    "ick",  &hsotgusb_ick_3430es1),
3277         CLK(NULL,       "hsotgusb_ick", &hsotgusb_ick_3430es1),
3278         CLK(NULL,       "fac_ick",      &fac_ick),
3279         CLK(NULL,       "ssi_ick",      &ssi_ick_3430es1),
3280         CLK(NULL,       "usb_l4_ick",   &usb_l4_ick),
3281         CLK(NULL,       "dss1_alwon_fck",       &dss1_alwon_fck_3430es1),
3282         CLK("omapdss_dss",      "ick",          &dss_ick_3430es1),
3283         CLK(NULL,       "dss_ick",              &dss_ick_3430es1),
3284 };
3285
3286 /*
3287  * clocks specific to am35xx
3288  */
3289 static struct omap_clk am35xx_clks[] = {
3290         CLK(NULL,       "ipss_ick",     &ipss_ick),
3291         CLK(NULL,       "rmii_ck",      &rmii_ck),
3292         CLK(NULL,       "pclk_ck",      &pclk_ck),
3293         CLK(NULL,       "emac_ick",     &emac_ick),
3294         CLK(NULL,       "emac_fck",     &emac_fck),
3295         CLK("davinci_emac.0",   NULL,   &emac_ick),
3296         CLK("davinci_mdio.0",   NULL,   &emac_fck),
3297         CLK("vpfe-capture",     "master",       &vpfe_ick),
3298         CLK("vpfe-capture",     "slave",        &vpfe_fck),
3299         CLK(NULL,       "hsotgusb_ick",         &hsotgusb_ick_am35xx),
3300         CLK(NULL,       "hsotgusb_fck",         &hsotgusb_fck_am35xx),
3301         CLK(NULL,       "hecc_ck",      &hecc_ck),
3302         CLK(NULL,       "uart4_ick",    &uart4_ick_am35xx),
3303         CLK(NULL,       "uart4_fck",    &uart4_fck_am35xx),
3304 };
3305
3306 /*
3307  * clocks specific to omap36xx
3308  */
3309 static struct omap_clk omap36xx_clks[] = {
3310         CLK(NULL,       "omap_192m_alwon_fck", &omap_192m_alwon_fck),
3311         CLK(NULL,       "uart4_fck",    &uart4_fck),
3312 };
3313
3314 /*
3315  * clocks common to omap36xx omap34xx
3316  */
3317 static struct omap_clk omap34xx_omap36xx_clks[] = {
3318         CLK(NULL,       "aes1_ick",     &aes1_ick),
3319         CLK("omap_rng", "ick",          &rng_ick),
3320         CLK("omap3-rom-rng",    "ick",  &rng_ick),
3321         CLK(NULL,       "sha11_ick",    &sha11_ick),
3322         CLK(NULL,       "des1_ick",     &des1_ick),
3323         CLK(NULL,       "cam_mclk",     &cam_mclk),
3324         CLK(NULL,       "cam_ick",      &cam_ick),
3325         CLK(NULL,       "csi2_96m_fck", &csi2_96m_fck),
3326         CLK(NULL,       "security_l3_ick", &security_l3_ick),
3327         CLK(NULL,       "pka_ick",      &pka_ick),
3328         CLK(NULL,       "icr_ick",      &icr_ick),
3329         CLK("omap-aes", "ick",  &aes2_ick),
3330         CLK("omap-sham",        "ick",  &sha12_ick),
3331         CLK(NULL,       "des2_ick",     &des2_ick),
3332         CLK(NULL,       "mspro_ick",    &mspro_ick),
3333         CLK(NULL,       "mailboxes_ick", &mailboxes_ick),
3334         CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick),
3335         CLK(NULL,       "sr1_fck",      &sr1_fck),
3336         CLK(NULL,       "sr2_fck",      &sr2_fck),
3337         CLK(NULL,       "sr_l4_ick",    &sr_l4_ick),
3338         CLK(NULL,       "security_l4_ick2", &security_l4_ick2),
3339         CLK(NULL,       "wkup_l4_ick",  &wkup_l4_ick),
3340         CLK(NULL,       "dpll2_fck",    &dpll2_fck),
3341         CLK(NULL,       "iva2_ck",      &iva2_ck),
3342         CLK(NULL,       "modem_fck",    &modem_fck),
3343         CLK(NULL,       "sad2d_ick",    &sad2d_ick),
3344         CLK(NULL,       "mad2d_ick",    &mad2d_ick),
3345         CLK(NULL,       "mspro_fck",    &mspro_fck),
3346         CLK(NULL,       "dpll2_ck",     &dpll2_ck),
3347         CLK(NULL,       "dpll2_m2_ck",  &dpll2_m2_ck),
3348 };
3349
3350 /*
3351  * clocks common to omap36xx and omap3430es2plus
3352  */
3353 static struct omap_clk omap36xx_omap3430es2plus_clks[] = {
3354         CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es2),
3355         CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es2),
3356         CLK("musb-omap2430",    "ick",  &hsotgusb_ick_3430es2),
3357         CLK(NULL,       "hsotgusb_ick", &hsotgusb_ick_3430es2),
3358         CLK(NULL,       "ssi_ick",      &ssi_ick_3430es2),
3359         CLK(NULL,       "usim_fck",     &usim_fck),
3360         CLK(NULL,       "usim_ick",     &usim_ick),
3361 };
3362
3363 /*
3364  * clocks common to am35xx omap36xx and omap3430es2plus
3365  */
3366 static struct omap_clk omap36xx_am35xx_omap3430es2plus_clks[] = {
3367         CLK(NULL,       "virt_16_8m_ck", &virt_16_8m_ck),
3368         CLK(NULL,       "dpll5_ck",     &dpll5_ck),
3369         CLK(NULL,       "dpll5_m2_ck",  &dpll5_m2_ck),
3370         CLK(NULL,       "sgx_fck",      &sgx_fck),
3371         CLK(NULL,       "sgx_ick",      &sgx_ick),
3372         CLK(NULL,       "cpefuse_fck",  &cpefuse_fck),
3373         CLK(NULL,       "ts_fck",       &ts_fck),
3374         CLK(NULL,       "usbtll_fck",   &usbtll_fck),
3375         CLK(NULL,       "usbtll_ick",   &usbtll_ick),
3376         CLK("omap_hsmmc.2",     "ick",  &mmchs3_ick),
3377         CLK(NULL,       "mmchs3_ick",   &mmchs3_ick),
3378         CLK(NULL,       "mmchs3_fck",   &mmchs3_fck),
3379         CLK(NULL,       "dss1_alwon_fck",       &dss1_alwon_fck_3430es2),
3380         CLK("omapdss_dss",      "ick",          &dss_ick_3430es2),
3381         CLK(NULL,       "dss_ick",              &dss_ick_3430es2),
3382         CLK(NULL,       "usbhost_120m_fck", &usbhost_120m_fck),
3383         CLK(NULL,       "usbhost_48m_fck", &usbhost_48m_fck),
3384         CLK(NULL,       "usbhost_ick",  &usbhost_ick),
3385 };
3386
3387 /*
3388  * common clocks
3389  */
3390 static struct omap_clk omap3xxx_clks[] = {
3391         CLK(NULL,       "apb_pclk",     &dummy_apb_pclk),
3392         CLK(NULL,       "omap_32k_fck", &omap_32k_fck),
3393         CLK(NULL,       "virt_12m_ck",  &virt_12m_ck),
3394         CLK(NULL,       "virt_13m_ck",  &virt_13m_ck),
3395         CLK(NULL,       "virt_19200000_ck", &virt_19200000_ck),
3396         CLK(NULL,       "virt_26000000_ck", &virt_26000000_ck),
3397         CLK(NULL,       "virt_38_4m_ck", &virt_38_4m_ck),
3398         CLK(NULL,       "osc_sys_ck",   &osc_sys_ck),
3399         CLK("twl",      "fck",          &osc_sys_ck),
3400         CLK(NULL,       "sys_ck",       &sys_ck),
3401         CLK(NULL,       "omap_96m_alwon_fck", &omap_96m_alwon_fck),
3402         CLK("etb",      "emu_core_alwon_ck", &emu_core_alwon_ck),
3403         CLK(NULL,       "sys_altclk",   &sys_altclk),
3404         CLK(NULL,       "mcbsp_clks",   &mcbsp_clks),
3405         CLK(NULL,       "sys_clkout1",  &sys_clkout1),
3406         CLK(NULL,       "dpll1_ck",     &dpll1_ck),
3407         CLK(NULL,       "dpll1_x2_ck",  &dpll1_x2_ck),
3408         CLK(NULL,       "dpll1_x2m2_ck", &dpll1_x2m2_ck),
3409         CLK(NULL,       "dpll3_ck",     &dpll3_ck),
3410         CLK(NULL,       "core_ck",      &core_ck),
3411         CLK(NULL,       "dpll3_x2_ck",  &dpll3_x2_ck),
3412         CLK(NULL,       "dpll3_m2_ck",  &dpll3_m2_ck),
3413         CLK(NULL,       "dpll3_m2x2_ck", &dpll3_m2x2_ck),
3414         CLK(NULL,       "dpll3_m3_ck",  &dpll3_m3_ck),
3415         CLK(NULL,       "dpll3_m3x2_ck", &dpll3_m3x2_ck),
3416         CLK(NULL,       "dpll4_ck",     &dpll4_ck),
3417         CLK(NULL,       "dpll4_x2_ck",  &dpll4_x2_ck),
3418         CLK(NULL,       "omap_96m_fck", &omap_96m_fck),
3419         CLK(NULL,       "cm_96m_fck",   &cm_96m_fck),
3420         CLK(NULL,       "omap_54m_fck", &omap_54m_fck),
3421         CLK(NULL,       "omap_48m_fck", &omap_48m_fck),
3422         CLK(NULL,       "omap_12m_fck", &omap_12m_fck),
3423         CLK(NULL,       "dpll4_m2_ck",  &dpll4_m2_ck),
3424         CLK(NULL,       "dpll4_m2x2_ck", &dpll4_m2x2_ck),
3425         CLK(NULL,       "dpll4_m3_ck",  &dpll4_m3_ck),
3426         CLK(NULL,       "dpll4_m3x2_ck", &dpll4_m3x2_ck),
3427         CLK(NULL,       "dpll4_m4_ck",  &dpll4_m4_ck),
3428         CLK(NULL,       "dpll4_m4x2_ck", &dpll4_m4x2_ck),
3429         CLK(NULL,       "dpll4_m5_ck",  &dpll4_m5_ck),
3430         CLK(NULL,       "dpll4_m5x2_ck", &dpll4_m5x2_ck),
3431         CLK(NULL,       "dpll4_m6_ck",  &dpll4_m6_ck),
3432         CLK(NULL,       "dpll4_m6x2_ck", &dpll4_m6x2_ck),
3433         CLK("etb",      "emu_per_alwon_ck", &emu_per_alwon_ck),
3434         CLK(NULL,       "clkout2_src_ck", &clkout2_src_ck),
3435         CLK(NULL,       "sys_clkout2",  &sys_clkout2),
3436         CLK(NULL,       "corex2_fck",   &corex2_fck),
3437         CLK(NULL,       "dpll1_fck",    &dpll1_fck),
3438         CLK(NULL,       "mpu_ck",       &mpu_ck),
3439         CLK(NULL,       "arm_fck",      &arm_fck),
3440         CLK("etb",      "emu_mpu_alwon_ck", &emu_mpu_alwon_ck),
3441         CLK(NULL,       "l3_ick",       &l3_ick),
3442         CLK(NULL,       "l4_ick",       &l4_ick),
3443         CLK(NULL,       "rm_ick",       &rm_ick),
3444         CLK(NULL,       "gpt10_fck",    &gpt10_fck),
3445         CLK(NULL,       "gpt11_fck",    &gpt11_fck),
3446         CLK(NULL,       "core_96m_fck", &core_96m_fck),
3447         CLK(NULL,       "mmchs2_fck",   &mmchs2_fck),
3448         CLK(NULL,       "mmchs1_fck",   &mmchs1_fck),
3449         CLK(NULL,       "i2c3_fck",     &i2c3_fck),
3450         CLK(NULL,       "i2c2_fck",     &i2c2_fck),
3451         CLK(NULL,       "i2c1_fck",     &i2c1_fck),
3452         CLK(NULL,       "mcbsp5_fck",   &mcbsp5_fck),
3453         CLK(NULL,       "mcbsp1_fck",   &mcbsp1_fck),
3454         CLK(NULL,       "core_48m_fck", &core_48m_fck),
3455         CLK(NULL,       "mcspi4_fck",   &mcspi4_fck),
3456         CLK(NULL,       "mcspi3_fck",   &mcspi3_fck),
3457         CLK(NULL,       "mcspi2_fck",   &mcspi2_fck),
3458         CLK(NULL,       "mcspi1_fck",   &mcspi1_fck),
3459         CLK(NULL,       "uart2_fck",    &uart2_fck),
3460         CLK(NULL,       "uart1_fck",    &uart1_fck),
3461         CLK(NULL,       "core_12m_fck", &core_12m_fck),
3462         CLK("omap_hdq.0",       "fck",  &hdq_fck),
3463         CLK(NULL,       "hdq_fck",      &hdq_fck),
3464         CLK(NULL,       "core_l3_ick",  &core_l3_ick),
3465         CLK(NULL,       "sdrc_ick",     &sdrc_ick),
3466         CLK(NULL,       "gpmc_fck",     &gpmc_fck),
3467         CLK(NULL,       "core_l4_ick",  &core_l4_ick),
3468         CLK("omap_hsmmc.1",     "ick",  &mmchs2_ick),
3469         CLK("omap_hsmmc.0",     "ick",  &mmchs1_ick),
3470         CLK(NULL,       "mmchs2_ick",   &mmchs2_ick),
3471         CLK(NULL,       "mmchs1_ick",   &mmchs1_ick),
3472         CLK("omap_hdq.0", "ick",        &hdq_ick),
3473         CLK(NULL,       "hdq_ick",      &hdq_ick),
3474         CLK("omap2_mcspi.4", "ick",     &mcspi4_ick),
3475         CLK("omap2_mcspi.3", "ick",     &mcspi3_ick),
3476         CLK("omap2_mcspi.2", "ick",     &mcspi2_ick),
3477         CLK("omap2_mcspi.1", "ick",     &mcspi1_ick),
3478         CLK(NULL,       "mcspi4_ick",   &mcspi4_ick),
3479         CLK(NULL,       "mcspi3_ick",   &mcspi3_ick),
3480         CLK(NULL,       "mcspi2_ick",   &mcspi2_ick),
3481         CLK(NULL,       "mcspi1_ick",   &mcspi1_ick),
3482         CLK("omap_i2c.3", "ick",        &i2c3_ick),
3483         CLK("omap_i2c.2", "ick",        &i2c2_ick),
3484         CLK("omap_i2c.1", "ick",        &i2c1_ick),
3485         CLK(NULL,       "i2c3_ick",     &i2c3_ick),
3486         CLK(NULL,       "i2c2_ick",     &i2c2_ick),
3487         CLK(NULL,       "i2c1_ick",     &i2c1_ick),
3488         CLK(NULL,       "uart2_ick",    &uart2_ick),
3489         CLK(NULL,       "uart1_ick",    &uart1_ick),
3490         CLK(NULL,       "gpt11_ick",    &gpt11_ick),
3491         CLK(NULL,       "gpt10_ick",    &gpt10_ick),
3492         CLK("omap-mcbsp.5", "ick",      &mcbsp5_ick),
3493         CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick),
3494         CLK(NULL,       "mcbsp5_ick",   &mcbsp5_ick),
3495         CLK(NULL,       "mcbsp1_ick",   &mcbsp1_ick),
3496         CLK(NULL,       "omapctrl_ick", &omapctrl_ick),
3497         CLK(NULL,       "dss_tv_fck",   &dss_tv_fck),
3498         CLK(NULL,       "dss_96m_fck",  &dss_96m_fck),
3499         CLK(NULL,       "dss2_alwon_fck",       &dss2_alwon_fck),
3500         CLK(NULL,       "init_60m_fclk",        &dummy_ck),
3501         CLK(NULL,       "gpt1_fck",     &gpt1_fck),
3502         CLK(NULL,       "aes2_ick",     &aes2_ick),
3503         CLK(NULL,       "wkup_32k_fck", &wkup_32k_fck),
3504         CLK(NULL,       "gpio1_dbck",   &gpio1_dbck),
3505         CLK(NULL,       "sha12_ick",    &sha12_ick),
3506         CLK(NULL,       "wdt2_fck",             &wdt2_fck),
3507         CLK("omap_wdt", "ick",          &wdt2_ick),
3508         CLK(NULL,       "wdt2_ick",     &wdt2_ick),
3509         CLK(NULL,       "wdt1_ick",     &wdt1_ick),
3510         CLK(NULL,       "gpio1_ick",    &gpio1_ick),
3511         CLK(NULL,       "omap_32ksync_ick", &omap_32ksync_ick),
3512         CLK(NULL,       "gpt12_ick",    &gpt12_ick),
3513         CLK(NULL,       "gpt1_ick",     &gpt1_ick),
3514         CLK(NULL,       "per_96m_fck",  &per_96m_fck),
3515         CLK(NULL,       "per_48m_fck",  &per_48m_fck),
3516         CLK(NULL,       "uart3_fck",    &uart3_fck),
3517         CLK(NULL,       "gpt2_fck",     &gpt2_fck),
3518         CLK(NULL,       "gpt3_fck",     &gpt3_fck),
3519         CLK(NULL,       "gpt4_fck",     &gpt4_fck),
3520         CLK(NULL,       "gpt5_fck",     &gpt5_fck),
3521         CLK(NULL,       "gpt6_fck",     &gpt6_fck),
3522         CLK(NULL,       "gpt7_fck",     &gpt7_fck),
3523         CLK(NULL,       "gpt8_fck",     &gpt8_fck),
3524         CLK(NULL,       "gpt9_fck",     &gpt9_fck),
3525         CLK(NULL,       "per_32k_alwon_fck", &per_32k_alwon_fck),
3526         CLK(NULL,       "gpio6_dbck",   &gpio6_dbck),
3527         CLK(NULL,       "gpio5_dbck",   &gpio5_dbck),
3528         CLK(NULL,       "gpio4_dbck",   &gpio4_dbck),
3529         CLK(NULL,       "gpio3_dbck",   &gpio3_dbck),
3530         CLK(NULL,       "gpio2_dbck",   &gpio2_dbck),
3531         CLK(NULL,       "wdt3_fck",     &wdt3_fck),
3532         CLK(NULL,       "per_l4_ick",   &per_l4_ick),
3533         CLK(NULL,       "gpio6_ick",    &gpio6_ick),
3534         CLK(NULL,       "gpio5_ick",    &gpio5_ick),
3535         CLK(NULL,       "gpio4_ick",    &gpio4_ick),
3536         CLK(NULL,       "gpio3_ick",    &gpio3_ick),
3537         CLK(NULL,       "gpio2_ick",    &gpio2_ick),
3538         CLK(NULL,       "wdt3_ick",     &wdt3_ick),
3539         CLK(NULL,       "uart3_ick",    &uart3_ick),
3540         CLK(NULL,       "uart4_ick",    &uart4_ick),
3541         CLK(NULL,       "gpt9_ick",     &gpt9_ick),
3542         CLK(NULL,       "gpt8_ick",     &gpt8_ick),
3543         CLK(NULL,       "gpt7_ick",     &gpt7_ick),
3544         CLK(NULL,       "gpt6_ick",     &gpt6_ick),
3545         CLK(NULL,       "gpt5_ick",     &gpt5_ick),
3546         CLK(NULL,       "gpt4_ick",     &gpt4_ick),
3547         CLK(NULL,       "gpt3_ick",     &gpt3_ick),
3548         CLK(NULL,       "gpt2_ick",     &gpt2_ick),
3549         CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick),
3550         CLK("omap-mcbsp.3", "ick",      &mcbsp3_ick),
3551         CLK("omap-mcbsp.4", "ick",      &mcbsp4_ick),
3552         CLK(NULL,       "mcbsp4_ick",   &mcbsp2_ick),
3553         CLK(NULL,       "mcbsp3_ick",   &mcbsp3_ick),
3554         CLK(NULL,       "mcbsp2_ick",   &mcbsp4_ick),
3555         CLK(NULL,       "mcbsp2_fck",   &mcbsp2_fck),
3556         CLK(NULL,       "mcbsp3_fck",   &mcbsp3_fck),
3557         CLK(NULL,       "mcbsp4_fck",   &mcbsp4_fck),
3558         CLK("etb",      "emu_src_ck",   &emu_src_ck),
3559         CLK(NULL,       "emu_src_ck",   &emu_src_ck),
3560         CLK(NULL,       "pclk_fck",     &pclk_fck),
3561         CLK(NULL,       "pclkx2_fck",   &pclkx2_fck),
3562         CLK(NULL,       "atclk_fck",    &atclk_fck),
3563         CLK(NULL,       "traceclk_src_fck", &traceclk_src_fck),
3564         CLK(NULL,       "traceclk_fck", &traceclk_fck),
3565         CLK(NULL,       "secure_32k_fck", &secure_32k_fck),
3566         CLK(NULL,       "gpt12_fck",    &gpt12_fck),
3567         CLK(NULL,       "wdt1_fck",     &wdt1_fck),
3568         CLK(NULL,       "timer_32k_ck", &omap_32k_fck),
3569         CLK(NULL,       "timer_sys_ck", &sys_ck),
3570         CLK(NULL,       "cpufreq_ck",   &dpll1_ck),
3571 };
3572
3573 static const char *enable_init_clks[] = {
3574         "sdrc_ick",
3575         "gpmc_fck",
3576         "omapctrl_ick",
3577 };
3578
3579 int __init omap3xxx_clk_init(void)
3580 {
3581         if (omap3_has_192mhz_clk())
3582                 omap_96m_alwon_fck = omap_96m_alwon_fck_3630;
3583
3584         if (cpu_is_omap3630()) {
3585                 dpll3_m3x2_ck = dpll3_m3x2_ck_3630;
3586                 dpll4_m2x2_ck = dpll4_m2x2_ck_3630;
3587                 dpll4_m3x2_ck = dpll4_m3x2_ck_3630;
3588                 dpll4_m4x2_ck = dpll4_m4x2_ck_3630;
3589                 dpll4_m5x2_ck = dpll4_m5x2_ck_3630;
3590                 dpll4_m6x2_ck = dpll4_m6x2_ck_3630;
3591         }
3592
3593         /*
3594          * XXX This type of dynamic rewriting of the clock tree is
3595          * deprecated and should be revised soon.
3596          */
3597         if (cpu_is_omap3630())
3598                 dpll4_dd = dpll4_dd_3630;
3599         else
3600                 dpll4_dd = dpll4_dd_34xx;
3601
3602
3603         /*
3604          * 3505 must be tested before 3517, since 3517 returns true
3605          * for both AM3517 chips and AM3517 family chips, which
3606          * includes 3505.  Unfortunately there's no obvious family
3607          * test for 3517/3505 :-(
3608          */
3609         if (soc_is_am35xx()) {
3610                 cpu_mask = RATE_IN_34XX;
3611                 omap_clocks_register(am35xx_clks, ARRAY_SIZE(am35xx_clks));
3612                 omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks,
3613                                      ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks));
3614                 omap_clocks_register(omap3xxx_clks, ARRAY_SIZE(omap3xxx_clks));
3615         } else if (cpu_is_omap3630()) {
3616                 cpu_mask = (RATE_IN_34XX | RATE_IN_36XX);
3617                 omap_clocks_register(omap36xx_clks, ARRAY_SIZE(omap36xx_clks));
3618                 omap_clocks_register(omap36xx_omap3430es2plus_clks,
3619                                      ARRAY_SIZE(omap36xx_omap3430es2plus_clks));
3620                 omap_clocks_register(omap34xx_omap36xx_clks,
3621                                      ARRAY_SIZE(omap34xx_omap36xx_clks));
3622                 omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks,
3623                                      ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks));
3624                 omap_clocks_register(omap3xxx_clks, ARRAY_SIZE(omap3xxx_clks));
3625         } else if (soc_is_am33xx()) {
3626                 cpu_mask = RATE_IN_AM33XX;
3627         } else if (cpu_is_ti814x()) {
3628                 cpu_mask = RATE_IN_TI814X;
3629         } else if (cpu_is_omap34xx()) {
3630                 if (omap_rev() == OMAP3430_REV_ES1_0) {
3631                         cpu_mask = RATE_IN_3430ES1;
3632                         omap_clocks_register(omap3430es1_clks,
3633                                              ARRAY_SIZE(omap3430es1_clks));
3634                         omap_clocks_register(omap34xx_omap36xx_clks,
3635                                              ARRAY_SIZE(omap34xx_omap36xx_clks));
3636                         omap_clocks_register(omap3xxx_clks,
3637                                              ARRAY_SIZE(omap3xxx_clks));
3638                 } else {
3639                         /*
3640                          * Assume that anything that we haven't matched yet
3641                          * has 3430ES2-type clocks.
3642                          */
3643                         cpu_mask = RATE_IN_3430ES2PLUS;
3644                         omap_clocks_register(omap34xx_omap36xx_clks,
3645                                              ARRAY_SIZE(omap34xx_omap36xx_clks));
3646                         omap_clocks_register(omap36xx_omap3430es2plus_clks,
3647                                              ARRAY_SIZE(omap36xx_omap3430es2plus_clks));
3648                         omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks,
3649                                              ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks));
3650                         omap_clocks_register(omap3xxx_clks,
3651                                              ARRAY_SIZE(omap3xxx_clks));
3652                 }
3653         } else {
3654                 WARN(1, "clock: could not identify OMAP3 variant\n");
3655         }
3656
3657                 omap2_clk_disable_autoidle_all();
3658
3659         omap2_clk_enable_init_clocks(enable_init_clks,
3660                                      ARRAY_SIZE(enable_init_clks));
3661
3662         pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
3663                 (clk_get_rate(&osc_sys_ck) / 1000000),
3664                 (clk_get_rate(&osc_sys_ck) / 100000) % 10,
3665                 (clk_get_rate(&core_ck) / 1000000),
3666                 (clk_get_rate(&arm_fck) / 1000000));
3667
3668         /*
3669          * Lock DPLL5 -- here only until other device init code can
3670          * handle this
3671          */
3672         if (!cpu_is_ti81xx() && (omap_rev() >= OMAP3430_REV_ES2_0))
3673                 omap3_clk_lock_dpll5();
3674
3675         /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
3676         sdrc_ick_p = clk_get(NULL, "sdrc_ick");
3677         arm_fck_p = clk_get(NULL, "arm_fck");
3678
3679         return 0;
3680 }