arch/arm/mach-exynos/pm.c

   1 /*
   2  * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * EXYNOS - Power Management support
   6  *
   7  * Based on arch/arm/mach-s3c2410/pm.c
   8  * Copyright (c) 2006 Simtec Electronics
   9  *      Ben Dooks <ben@simtec.co.uk>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14 */
  15
  16 #include <linux/init.h>
  17 #include <linux/suspend.h>
  18 #include <linux/syscore_ops.h>
  19 #include <linux/io.h>
  20 #include <linux/err.h>
  21 #include <linux/clk.h>
  22
  23 #include <asm/cacheflush.h>
  24 #include <asm/hardware/cache-l2x0.h>
  25 #include <asm/smp_scu.h>
  26
  27 #include <plat/cpu.h>
  28 #include <plat/pm.h>
  29 #include <plat/pll.h>
  30 #include <plat/regs-srom.h>
  31
  32 #include <mach/map.h>
  33 #include <mach/pm-core.h>
  34
  35 #include "common.h"
  36 #include "regs-pmu.h"
  37
  38 static struct sleep_save exynos5_sys_save[] = {
  39         SAVE_ITEM(EXYNOS5_SYS_I2C_CFG),
  40 };
  41
  42 static struct sleep_save exynos_core_save[] = {
  43         /* SROM side */
  44         SAVE_ITEM(S5P_SROM_BW),
  45         SAVE_ITEM(S5P_SROM_BC0),
  46         SAVE_ITEM(S5P_SROM_BC1),
  47         SAVE_ITEM(S5P_SROM_BC2),
  48         SAVE_ITEM(S5P_SROM_BC3),
  49 };
  50
  51
  52 /* For Cortex-A9 Diagnostic and Power control register */
  53 static unsigned int save_arm_register[2];
  54
  55 static int exynos_cpu_suspend(unsigned long arg)
  56 {
  57 #ifdef CONFIG_CACHE_L2X0
  58         outer_flush_all();
  59 #endif
  60
  61         if (soc_is_exynos5250())
  62                 flush_cache_all();
  63
  64         /* issue the standby signal into the pm unit. */
  65         cpu_do_idle();
  66
  67         pr_info("Failed to suspend the system\n");
  68         return 1; /* Aborting suspend */
  69 }
  70
  71 static void exynos_pm_prepare(void)
  72 {
  73         unsigned int tmp;
  74
  75         s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
  76
  77         if (soc_is_exynos5250()) {
  78                 s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save));
  79                 /* Disable USE_RETENTION of JPEG_MEM_OPTION */
  80                 tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION);
  81                 tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
  82                 __raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
  83         }
  84
  85         /* Set value of power down register for sleep mode */
  86
  87         exynos_sys_powerdown_conf(SYS_SLEEP);
  88         __raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
  89
  90         /* ensure at least INFORM0 has the resume address */
  91
  92         __raw_writel(virt_to_phys(s3c_cpu_resume), S5P_INFORM0);
  93 }
  94
  95 static int exynos_pm_add(struct device *dev, struct subsys_interface *sif)
  96 {
  97         pm_cpu_prep = exynos_pm_prepare;
  98         pm_cpu_sleep = exynos_cpu_suspend;
  99
 100         return 0;
 101 }
 102
 103 static struct subsys_interface exynos_pm_interface = {
 104         .name           = "exynos_pm",
 105         .subsys         = &exynos_subsys,
 106         .add_dev        = exynos_pm_add,
 107 };
 108
 109 static __init int exynos_pm_drvinit(void)
 110 {
 111         unsigned int tmp;
 112
 113         if (soc_is_exynos5440())
 114                 return 0;
 115
 116         s3c_pm_init();
 117
 118         /* All wakeup disable */
 119
 120         tmp = __raw_readl(S5P_WAKEUP_MASK);
 121         tmp |= ((0xFF << 8) | (0x1F << 1));
 122         __raw_writel(tmp, S5P_WAKEUP_MASK);
 123
 124         return subsys_interface_register(&exynos_pm_interface);
 125 }
 126 arch_initcall(exynos_pm_drvinit);
 127
 128 static int exynos_pm_suspend(void)
 129 {
 130         unsigned long tmp;
 131
 132         /* Setting Central Sequence Register for power down mode */
 133
 134         tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
 135         tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
 136         __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
 137
 138         /* Setting SEQ_OPTION register */
 139
 140         tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);
 141         __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
 142
 143         if (!soc_is_exynos5250()) {
 144                 /* Save Power control register */
 145                 asm ("mrc p15, 0, %0, c15, c0, 0"
 146                      : "=r" (tmp) : : "cc");
 147                 save_arm_register[0] = tmp;
 148
 149                 /* Save Diagnostic register */
 150                 asm ("mrc p15, 0, %0, c15, c0, 1"
 151                      : "=r" (tmp) : : "cc");
 152                 save_arm_register[1] = tmp;
 153         }
 154
 155         return 0;
 156 }
 157
 158 static void exynos_pm_resume(void)
 159 {
 160         unsigned long tmp;
 161
 162         /*
 163          * If PMU failed while entering sleep mode, WFI will be
 164          * ignored by PMU and then exiting cpu_do_idle().
 165          * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
 166          * in this situation.
 167          */
 168         tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
 169         if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
 170                 tmp |= S5P_CENTRAL_LOWPWR_CFG;
 171                 __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
 172                 /* clear the wakeup state register */
 173                 __raw_writel(0x0, S5P_WAKEUP_STAT);
 174                 /* No need to perform below restore code */
 175                 goto early_wakeup;
 176         }
 177         if (!soc_is_exynos5250()) {
 178                 /* Restore Power control register */
 179                 tmp = save_arm_register[0];
 180                 asm volatile ("mcr p15, 0, %0, c15, c0, 0"
 181                               : : "r" (tmp)
 182                               : "cc");
 183
 184                 /* Restore Diagnostic register */
 185                 tmp = save_arm_register[1];
 186                 asm volatile ("mcr p15, 0, %0, c15, c0, 1"
 187                               : : "r" (tmp)
 188                               : "cc");
 189         }
 190
 191         /* For release retention */
 192
 193         __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
 194         __raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
 195         __raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
 196         __raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
 197         __raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
 198         __raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
 199         __raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
 200
 201         if (soc_is_exynos5250())
 202                 s3c_pm_do_restore(exynos5_sys_save,
 203                         ARRAY_SIZE(exynos5_sys_save));
 204
 205         s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
 206
 207         if (IS_ENABLED(CONFIG_SMP) && !soc_is_exynos5250())
 208                 scu_enable(S5P_VA_SCU);
 209
 210 early_wakeup:
 211
 212         /* Clear SLEEP mode set in INFORM1 */
 213         __raw_writel(0x0, S5P_INFORM1);
 214
 215         return;
 216 }
 217
 218 static struct syscore_ops exynos_pm_syscore_ops = {
 219         .suspend        = exynos_pm_suspend,
 220         .resume         = exynos_pm_resume,
 221 };
 222
 223 static __init int exynos_pm_syscore_init(void)
 224 {
 225         if (soc_is_exynos5440())
 226                 return 0;
 227
 228         register_syscore_ops(&exynos_pm_syscore_ops);
 229         return 0;
 230 }
 231 arch_initcall(exynos_pm_syscore_init);