arch/arm/mach-exynos/pm.c

   1 /*
   2  * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * EXYNOS - Power Management support
   6  *
   7  * Based on arch/arm/mach-s3c2410/pm.c
   8  * Copyright (c) 2006 Simtec Electronics
   9  *      Ben Dooks <ben@simtec.co.uk>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14 */
  15
  16 #include <linux/init.h>
  17 #include <linux/suspend.h>
  18 #include <linux/syscore_ops.h>
  19 #include <linux/io.h>
  20 #include <linux/err.h>
  21 #include <linux/clk.h>
  22
  23 #include <asm/cacheflush.h>
  24 #include <asm/hardware/cache-l2x0.h>
  25 #include <asm/smp_scu.h>
  26
  27 #include <plat/cpu.h>
  28 #include <plat/pm.h>
  29 #include <plat/pll.h>
  30 #include <plat/regs-srom.h>
  31
  32 #include <mach/map.h>
  33 #include <mach/pm-core.h>
  34
  35 #include "common.h"
  36 #include "regs-pmu.h"
  37
  38 #define EXYNOS4_EPLL_LOCK                       (S5P_VA_CMU + 0x0C010)
  39 #define EXYNOS4_VPLL_LOCK                       (S5P_VA_CMU + 0x0C020)
  40
  41 #define EXYNOS4_EPLL_CON0                       (S5P_VA_CMU + 0x0C110)
  42 #define EXYNOS4_EPLL_CON1                       (S5P_VA_CMU + 0x0C114)
  43 #define EXYNOS4_VPLL_CON0                       (S5P_VA_CMU + 0x0C120)
  44 #define EXYNOS4_VPLL_CON1                       (S5P_VA_CMU + 0x0C124)
  45
  46 #define EXYNOS4_CLKSRC_MASK_TOP                 (S5P_VA_CMU + 0x0C310)
  47 #define EXYNOS4_CLKSRC_MASK_CAM                 (S5P_VA_CMU + 0x0C320)
  48 #define EXYNOS4_CLKSRC_MASK_TV                  (S5P_VA_CMU + 0x0C324)
  49 #define EXYNOS4_CLKSRC_MASK_LCD0                (S5P_VA_CMU + 0x0C334)
  50 #define EXYNOS4_CLKSRC_MASK_MAUDIO              (S5P_VA_CMU + 0x0C33C)
  51 #define EXYNOS4_CLKSRC_MASK_FSYS                (S5P_VA_CMU + 0x0C340)
  52 #define EXYNOS4_CLKSRC_MASK_PERIL0              (S5P_VA_CMU + 0x0C350)
  53 #define EXYNOS4_CLKSRC_MASK_PERIL1              (S5P_VA_CMU + 0x0C354)
  54
  55 #define EXYNOS4_CLKSRC_MASK_DMC                 (S5P_VA_CMU + 0x10300)
  56
  57 #define EXYNOS4_EPLLCON0_LOCKED_SHIFT           (29)
  58 #define EXYNOS4_VPLLCON0_LOCKED_SHIFT           (29)
  59
  60 #define EXYNOS4210_CLKSRC_MASK_LCD1             (S5P_VA_CMU + 0x0C338)
  61
  62 static const struct sleep_save exynos4_set_clksrc[] = {
  63         { .reg = EXYNOS4_CLKSRC_MASK_TOP                , .val = 0x00000001, },
  64         { .reg = EXYNOS4_CLKSRC_MASK_CAM                , .val = 0x11111111, },
  65         { .reg = EXYNOS4_CLKSRC_MASK_TV                 , .val = 0x00000111, },
  66         { .reg = EXYNOS4_CLKSRC_MASK_LCD0               , .val = 0x00001111, },
  67         { .reg = EXYNOS4_CLKSRC_MASK_MAUDIO             , .val = 0x00000001, },
  68         { .reg = EXYNOS4_CLKSRC_MASK_FSYS               , .val = 0x01011111, },
  69         { .reg = EXYNOS4_CLKSRC_MASK_PERIL0             , .val = 0x01111111, },
  70         { .reg = EXYNOS4_CLKSRC_MASK_PERIL1             , .val = 0x01110111, },
  71         { .reg = EXYNOS4_CLKSRC_MASK_DMC                , .val = 0x00010000, },
  72 };
  73
  74 static const struct sleep_save exynos4210_set_clksrc[] = {
  75         { .reg = EXYNOS4210_CLKSRC_MASK_LCD1            , .val = 0x00001111, },
  76 };
  77
  78 static struct sleep_save exynos4_epll_save[] = {
  79         SAVE_ITEM(EXYNOS4_EPLL_CON0),
  80         SAVE_ITEM(EXYNOS4_EPLL_CON1),
  81 };
  82
  83 static struct sleep_save exynos4_vpll_save[] = {
  84         SAVE_ITEM(EXYNOS4_VPLL_CON0),
  85         SAVE_ITEM(EXYNOS4_VPLL_CON1),
  86 };
  87
  88 static struct sleep_save exynos5_sys_save[] = {
  89         SAVE_ITEM(EXYNOS5_SYS_I2C_CFG),
  90 };
  91
  92 static struct sleep_save exynos_core_save[] = {
  93         /* SROM side */
  94         SAVE_ITEM(S5P_SROM_BW),
  95         SAVE_ITEM(S5P_SROM_BC0),
  96         SAVE_ITEM(S5P_SROM_BC1),
  97         SAVE_ITEM(S5P_SROM_BC2),
  98         SAVE_ITEM(S5P_SROM_BC3),
  99 };
 100
 101
 102 /* For Cortex-A9 Diagnostic and Power control register */
 103 static unsigned int save_arm_register[2];
 104
 105 static int exynos_cpu_suspend(unsigned long arg)
 106 {
 107 #ifdef CONFIG_CACHE_L2X0
 108         outer_flush_all();
 109 #endif
 110
 111         if (soc_is_exynos5250())
 112                 flush_cache_all();
 113
 114         /* issue the standby signal into the pm unit. */
 115         cpu_do_idle();
 116
 117         pr_info("Failed to suspend the system\n");
 118         return 1; /* Aborting suspend */
 119 }
 120
 121 static void exynos_pm_prepare(void)
 122 {
 123         unsigned int tmp;
 124
 125         s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
 126
 127         if (!soc_is_exynos5250()) {
 128                 s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save));
 129                 s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save));
 130         } else {
 131                 s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save));
 132                 /* Disable USE_RETENTION of JPEG_MEM_OPTION */
 133                 tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION);
 134                 tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
 135                 __raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
 136         }
 137
 138         /* Set value of power down register for sleep mode */
 139
 140         exynos_sys_powerdown_conf(SYS_SLEEP);
 141         __raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
 142
 143         /* ensure at least INFORM0 has the resume address */
 144
 145         __raw_writel(virt_to_phys(s3c_cpu_resume), S5P_INFORM0);
 146
 147         /* Before enter central sequence mode, clock src register have to set */
 148
 149         if (!soc_is_exynos5250())
 150                 s3c_pm_do_restore_core(exynos4_set_clksrc, ARRAY_SIZE(exynos4_set_clksrc));
 151
 152         if (soc_is_exynos4210())
 153                 s3c_pm_do_restore_core(exynos4210_set_clksrc, ARRAY_SIZE(exynos4210_set_clksrc));
 154
 155 }
 156
 157 static int exynos_pm_add(struct device *dev, struct subsys_interface *sif)
 158 {
 159         pm_cpu_prep = exynos_pm_prepare;
 160         pm_cpu_sleep = exynos_cpu_suspend;
 161
 162         return 0;
 163 }
 164
 165 static unsigned long pll_base_rate;
 166
 167 static void exynos4_restore_pll(void)
 168 {
 169         unsigned long pll_con, locktime, lockcnt;
 170         unsigned long pll_in_rate;
 171         unsigned int p_div, epll_wait = 0, vpll_wait = 0;
 172
 173         if (pll_base_rate == 0)
 174                 return;
 175
 176         pll_in_rate = pll_base_rate;
 177
 178         /* EPLL */
 179         pll_con = exynos4_epll_save[0].val;
 180
 181         if (pll_con & (1 << 31)) {
 182                 pll_con &= (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT);
 183                 p_div = (pll_con >> PLL46XX_PDIV_SHIFT);
 184
 185                 pll_in_rate /= 1000000;
 186
 187                 locktime = (3000 / pll_in_rate) * p_div;
 188                 lockcnt = locktime * 10000 / (10000 / pll_in_rate);
 189
 190                 __raw_writel(lockcnt, EXYNOS4_EPLL_LOCK);
 191
 192                 s3c_pm_do_restore_core(exynos4_epll_save,
 193                                         ARRAY_SIZE(exynos4_epll_save));
 194                 epll_wait = 1;
 195         }
 196
 197         pll_in_rate = pll_base_rate;
 198
 199         /* VPLL */
 200         pll_con = exynos4_vpll_save[0].val;
 201
 202         if (pll_con & (1 << 31)) {
 203                 pll_in_rate /= 1000000;
 204                 /* 750us */
 205                 locktime = 750;
 206                 lockcnt = locktime * 10000 / (10000 / pll_in_rate);
 207
 208                 __raw_writel(lockcnt, EXYNOS4_VPLL_LOCK);
 209
 210                 s3c_pm_do_restore_core(exynos4_vpll_save,
 211                                         ARRAY_SIZE(exynos4_vpll_save));
 212                 vpll_wait = 1;
 213         }
 214
 215         /* Wait PLL locking */
 216
 217         do {
 218                 if (epll_wait) {
 219                         pll_con = __raw_readl(EXYNOS4_EPLL_CON0);
 220                         if (pll_con & (1 << EXYNOS4_EPLLCON0_LOCKED_SHIFT))
 221                                 epll_wait = 0;
 222                 }
 223
 224                 if (vpll_wait) {
 225                         pll_con = __raw_readl(EXYNOS4_VPLL_CON0);
 226                         if (pll_con & (1 << EXYNOS4_VPLLCON0_LOCKED_SHIFT))
 227                                 vpll_wait = 0;
 228                 }
 229         } while (epll_wait || vpll_wait);
 230 }
 231
 232 static struct subsys_interface exynos_pm_interface = {
 233         .name           = "exynos_pm",
 234         .subsys         = &exynos_subsys,
 235         .add_dev        = exynos_pm_add,
 236 };
 237
 238 static __init int exynos_pm_drvinit(void)
 239 {
 240         struct clk *pll_base;
 241         unsigned int tmp;
 242
 243         if (soc_is_exynos5440())
 244                 return 0;
 245
 246         s3c_pm_init();
 247
 248         /* All wakeup disable */
 249
 250         tmp = __raw_readl(S5P_WAKEUP_MASK);
 251         tmp |= ((0xFF << 8) | (0x1F << 1));
 252         __raw_writel(tmp, S5P_WAKEUP_MASK);
 253
 254         if (!soc_is_exynos5250()) {
 255                 pll_base = clk_get(NULL, "xtal");
 256
 257                 if (!IS_ERR(pll_base)) {
 258                         pll_base_rate = clk_get_rate(pll_base);
 259                         clk_put(pll_base);
 260                 }
 261         }
 262
 263         return subsys_interface_register(&exynos_pm_interface);
 264 }
 265 arch_initcall(exynos_pm_drvinit);
 266
 267 static int exynos_pm_suspend(void)
 268 {
 269         unsigned long tmp;
 270
 271         /* Setting Central Sequence Register for power down mode */
 272
 273         tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
 274         tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
 275         __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
 276
 277         /* Setting SEQ_OPTION register */
 278
 279         tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);
 280         __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
 281
 282         if (!soc_is_exynos5250()) {
 283                 /* Save Power control register */
 284                 asm ("mrc p15, 0, %0, c15, c0, 0"
 285                      : "=r" (tmp) : : "cc");
 286                 save_arm_register[0] = tmp;
 287
 288                 /* Save Diagnostic register */
 289                 asm ("mrc p15, 0, %0, c15, c0, 1"
 290                      : "=r" (tmp) : : "cc");
 291                 save_arm_register[1] = tmp;
 292         }
 293
 294         return 0;
 295 }
 296
 297 static void exynos_pm_resume(void)
 298 {
 299         unsigned long tmp;
 300
 301         /*
 302          * If PMU failed while entering sleep mode, WFI will be
 303          * ignored by PMU and then exiting cpu_do_idle().
 304          * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
 305          * in this situation.
 306          */
 307         tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
 308         if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
 309                 tmp |= S5P_CENTRAL_LOWPWR_CFG;
 310                 __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
 311                 /* clear the wakeup state register */
 312                 __raw_writel(0x0, S5P_WAKEUP_STAT);
 313                 /* No need to perform below restore code */
 314                 goto early_wakeup;
 315         }
 316         if (!soc_is_exynos5250()) {
 317                 /* Restore Power control register */
 318                 tmp = save_arm_register[0];
 319                 asm volatile ("mcr p15, 0, %0, c15, c0, 0"
 320                               : : "r" (tmp)
 321                               : "cc");
 322
 323                 /* Restore Diagnostic register */
 324                 tmp = save_arm_register[1];
 325                 asm volatile ("mcr p15, 0, %0, c15, c0, 1"
 326                               : : "r" (tmp)
 327                               : "cc");
 328         }
 329
 330         /* For release retention */
 331
 332         __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
 333         __raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
 334         __raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
 335         __raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
 336         __raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
 337         __raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
 338         __raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
 339
 340         if (soc_is_exynos5250())
 341                 s3c_pm_do_restore(exynos5_sys_save,
 342                         ARRAY_SIZE(exynos5_sys_save));
 343
 344         s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
 345
 346         if (!soc_is_exynos5250()) {
 347                 exynos4_restore_pll();
 348
 349 #ifdef CONFIG_SMP
 350                 scu_enable(S5P_VA_SCU);
 351 #endif
 352         }
 353
 354 early_wakeup:
 355
 356         /* Clear SLEEP mode set in INFORM1 */
 357         __raw_writel(0x0, S5P_INFORM1);
 358
 359         return;
 360 }
 361
 362 static struct syscore_ops exynos_pm_syscore_ops = {
 363         .suspend        = exynos_pm_suspend,
 364         .resume         = exynos_pm_resume,
 365 };
 366
 367 static __init int exynos_pm_syscore_init(void)
 368 {
 369         if (soc_is_exynos5440())
 370                 return 0;
 371
 372         register_syscore_ops(&exynos_pm_syscore_ops);
 373         return 0;
 374 }
 375 arch_initcall(exynos_pm_syscore_init);