2 * arch/arm/mach-at91/at91sam9rl.c
4 * Copyright (C) 2005 SAN People
5 * Copyright (C) 2007 Atmel Corporation
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file COPYING in the main directory of this archive for
12 #include <linux/module.h>
13 #include <linux/clk/at91_pmc.h>
15 #include <asm/proc-fns.h>
17 #include <asm/mach/arch.h>
18 #include <asm/mach/map.h>
19 #include <asm/system_misc.h>
21 #include <mach/at91_dbgu.h>
22 #include <mach/at91sam9rl.h>
23 #include <mach/hardware.h>
26 #include "at91_rstc.h"
33 /* --------------------------------------------------------------------
35 * -------------------------------------------------------------------- */
38 * The peripheral clocks.
40 static struct clk pioA_clk = {
42 .pmc_mask = 1 << AT91SAM9RL_ID_PIOA,
43 .type = CLK_TYPE_PERIPHERAL,
45 static struct clk pioB_clk = {
47 .pmc_mask = 1 << AT91SAM9RL_ID_PIOB,
48 .type = CLK_TYPE_PERIPHERAL,
50 static struct clk pioC_clk = {
52 .pmc_mask = 1 << AT91SAM9RL_ID_PIOC,
53 .type = CLK_TYPE_PERIPHERAL,
55 static struct clk pioD_clk = {
57 .pmc_mask = 1 << AT91SAM9RL_ID_PIOD,
58 .type = CLK_TYPE_PERIPHERAL,
60 static struct clk usart0_clk = {
62 .pmc_mask = 1 << AT91SAM9RL_ID_US0,
63 .type = CLK_TYPE_PERIPHERAL,
65 static struct clk usart1_clk = {
67 .pmc_mask = 1 << AT91SAM9RL_ID_US1,
68 .type = CLK_TYPE_PERIPHERAL,
70 static struct clk usart2_clk = {
72 .pmc_mask = 1 << AT91SAM9RL_ID_US2,
73 .type = CLK_TYPE_PERIPHERAL,
75 static struct clk usart3_clk = {
77 .pmc_mask = 1 << AT91SAM9RL_ID_US3,
78 .type = CLK_TYPE_PERIPHERAL,
80 static struct clk mmc_clk = {
82 .pmc_mask = 1 << AT91SAM9RL_ID_MCI,
83 .type = CLK_TYPE_PERIPHERAL,
85 static struct clk twi0_clk = {
87 .pmc_mask = 1 << AT91SAM9RL_ID_TWI0,
88 .type = CLK_TYPE_PERIPHERAL,
90 static struct clk twi1_clk = {
92 .pmc_mask = 1 << AT91SAM9RL_ID_TWI1,
93 .type = CLK_TYPE_PERIPHERAL,
95 static struct clk spi_clk = {
97 .pmc_mask = 1 << AT91SAM9RL_ID_SPI,
98 .type = CLK_TYPE_PERIPHERAL,
100 static struct clk ssc0_clk = {
102 .pmc_mask = 1 << AT91SAM9RL_ID_SSC0,
103 .type = CLK_TYPE_PERIPHERAL,
105 static struct clk ssc1_clk = {
107 .pmc_mask = 1 << AT91SAM9RL_ID_SSC1,
108 .type = CLK_TYPE_PERIPHERAL,
110 static struct clk tc0_clk = {
112 .pmc_mask = 1 << AT91SAM9RL_ID_TC0,
113 .type = CLK_TYPE_PERIPHERAL,
115 static struct clk tc1_clk = {
117 .pmc_mask = 1 << AT91SAM9RL_ID_TC1,
118 .type = CLK_TYPE_PERIPHERAL,
120 static struct clk tc2_clk = {
122 .pmc_mask = 1 << AT91SAM9RL_ID_TC2,
123 .type = CLK_TYPE_PERIPHERAL,
125 static struct clk pwm_clk = {
127 .pmc_mask = 1 << AT91SAM9RL_ID_PWMC,
128 .type = CLK_TYPE_PERIPHERAL,
130 static struct clk tsc_clk = {
132 .pmc_mask = 1 << AT91SAM9RL_ID_TSC,
133 .type = CLK_TYPE_PERIPHERAL,
135 static struct clk dma_clk = {
137 .pmc_mask = 1 << AT91SAM9RL_ID_DMA,
138 .type = CLK_TYPE_PERIPHERAL,
140 static struct clk udphs_clk = {
142 .pmc_mask = 1 << AT91SAM9RL_ID_UDPHS,
143 .type = CLK_TYPE_PERIPHERAL,
145 static struct clk lcdc_clk = {
147 .pmc_mask = 1 << AT91SAM9RL_ID_LCDC,
148 .type = CLK_TYPE_PERIPHERAL,
150 static struct clk ac97_clk = {
152 .pmc_mask = 1 << AT91SAM9RL_ID_AC97C,
153 .type = CLK_TYPE_PERIPHERAL,
156 static struct clk *periph_clocks[] __initdata = {
183 static struct clk_lookup periph_clocks_lookups[] = {
184 CLKDEV_CON_DEV_ID("hclk", "at91sam9rl-lcdfb.0", &lcdc_clk),
185 CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
186 CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
187 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
188 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
189 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
190 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
191 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
192 CLKDEV_CON_DEV_ID("pclk", "fffc0000.ssc", &ssc0_clk),
193 CLKDEV_CON_DEV_ID("pclk", "fffc4000.ssc", &ssc1_clk),
194 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.0", &twi0_clk),
195 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.1", &twi1_clk),
196 CLKDEV_CON_ID("pioA", &pioA_clk),
197 CLKDEV_CON_ID("pioB", &pioB_clk),
198 CLKDEV_CON_ID("pioC", &pioC_clk),
199 CLKDEV_CON_ID("pioD", &pioD_clk),
202 static struct clk_lookup usart_clocks_lookups[] = {
203 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
204 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
205 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
206 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
207 CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
211 * The two programmable clocks.
212 * You must configure pin multiplexing to bring these signals out.
214 static struct clk pck0 = {
216 .pmc_mask = AT91_PMC_PCK0,
217 .type = CLK_TYPE_PROGRAMMABLE,
220 static struct clk pck1 = {
222 .pmc_mask = AT91_PMC_PCK1,
223 .type = CLK_TYPE_PROGRAMMABLE,
227 static void __init at91sam9rl_register_clocks(void)
231 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
232 clk_register(periph_clocks[i]);
234 clkdev_add_table(periph_clocks_lookups,
235 ARRAY_SIZE(periph_clocks_lookups));
236 clkdev_add_table(usart_clocks_lookups,
237 ARRAY_SIZE(usart_clocks_lookups));
243 /* --------------------------------------------------------------------
245 * -------------------------------------------------------------------- */
247 static struct at91_gpio_bank at91sam9rl_gpio[] __initdata = {
249 .id = AT91SAM9RL_ID_PIOA,
250 .regbase = AT91SAM9RL_BASE_PIOA,
252 .id = AT91SAM9RL_ID_PIOB,
253 .regbase = AT91SAM9RL_BASE_PIOB,
255 .id = AT91SAM9RL_ID_PIOC,
256 .regbase = AT91SAM9RL_BASE_PIOC,
258 .id = AT91SAM9RL_ID_PIOD,
259 .regbase = AT91SAM9RL_BASE_PIOD,
263 /* --------------------------------------------------------------------
264 * AT91SAM9RL processor initialization
265 * -------------------------------------------------------------------- */
267 static void __init at91sam9rl_map_io(void)
269 unsigned long sram_size;
271 switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) {
272 case AT91_CIDR_SRAMSIZ_32K:
273 sram_size = 2 * SZ_16K;
275 case AT91_CIDR_SRAMSIZ_16K:
281 at91_init_sram(0, AT91SAM9RL_SRAM_BASE, sram_size);
284 static void __init at91sam9rl_ioremap_registers(void)
286 at91_ioremap_shdwc(AT91SAM9RL_BASE_SHDWC);
287 at91_ioremap_rstc(AT91SAM9RL_BASE_RSTC);
288 at91_ioremap_ramc(0, AT91SAM9RL_BASE_SDRAMC, 512);
289 at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT);
290 at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC);
291 at91_ioremap_matrix(AT91SAM9RL_BASE_MATRIX);
292 at91_pm_set_standby(at91sam9_sdram_standby);
295 static void __init at91sam9rl_initialize(void)
297 arm_pm_idle = at91sam9_idle;
298 arm_pm_restart = at91sam9_alt_restart;
300 at91_sysirq_mask_rtc(AT91SAM9RL_BASE_RTC);
301 at91_sysirq_mask_rtt(AT91SAM9RL_BASE_RTT);
303 /* Register GPIO subsystem */
304 at91_gpio_init(at91sam9rl_gpio, 4);
307 /* --------------------------------------------------------------------
308 * Interrupt initialization
309 * -------------------------------------------------------------------- */
312 * The default interrupt priority levels (0 = lowest, 7 = highest).
314 static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = {
315 7, /* Advanced Interrupt Controller */
316 7, /* System Peripherals */
317 1, /* Parallel IO Controller A */
318 1, /* Parallel IO Controller B */
319 1, /* Parallel IO Controller C */
320 1, /* Parallel IO Controller D */
325 0, /* Multimedia Card Interface */
326 6, /* Two-Wire Interface 0 */
327 6, /* Two-Wire Interface 1 */
328 5, /* Serial Peripheral Interface */
329 4, /* Serial Synchronous Controller 0 */
330 4, /* Serial Synchronous Controller 1 */
331 0, /* Timer Counter 0 */
332 0, /* Timer Counter 1 */
333 0, /* Timer Counter 2 */
335 0, /* Touch Screen Controller */
336 0, /* DMA Controller */
337 2, /* USB Device High speed port */
338 2, /* LCD Controller */
339 6, /* AC97 Controller */
346 0, /* Advanced Interrupt Controller */
349 AT91_SOC_START(at91sam9rl)
350 .map_io = at91sam9rl_map_io,
351 .default_irq_priority = at91sam9rl_default_irq_priority,
352 .extern_irq = (1 << AT91SAM9RL_ID_IRQ0),
353 .ioremap_registers = at91sam9rl_ioremap_registers,
354 .register_clocks = at91sam9rl_register_clocks,
355 .init = at91sam9rl_initialize,