arch/arm/mach-at91/at91sam9rl.c

   1 /*
   2  * arch/arm/mach-at91/at91sam9rl.c
   3  *
   4  *  Copyright (C) 2005 SAN People
   5  *  Copyright (C) 2007 Atmel Corporation
   6  *
   7  * This file is subject to the terms and conditions of the GNU General Public
   8  * License.  See the file COPYING in the main directory of this archive for
   9  * more details.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/clk/at91_pmc.h>
  14
  15 #include <asm/proc-fns.h>
  16 #include <asm/irq.h>
  17 #include <asm/mach/arch.h>
  18 #include <asm/mach/map.h>
  19 #include <asm/system_misc.h>
  20 #include <mach/cpu.h>
  21 #include <mach/at91_dbgu.h>
  22 #include <mach/at91sam9rl.h>
  23 #include <mach/hardware.h>
  24
  25 #include "at91_aic.h"
  26 #include "at91_rstc.h"
  27 #include "soc.h"
  28 #include "generic.h"
  29 #include "sam9_smc.h"
  30 #include "pm.h"
  31
  32 /* --------------------------------------------------------------------
  33  *  Clocks
  34  * -------------------------------------------------------------------- */
  35 #if defined(CONFIG_OLD_CLK_AT91)
  36 #include "clock.h"
  37
  38 /*
  39  * The peripheral clocks.
  40  */
  41 static struct clk pioA_clk = {
  42         .name           = "pioA_clk",
  43         .pmc_mask       = 1 << AT91SAM9RL_ID_PIOA,
  44         .type           = CLK_TYPE_PERIPHERAL,
  45 };
  46 static struct clk pioB_clk = {
  47         .name           = "pioB_clk",
  48         .pmc_mask       = 1 << AT91SAM9RL_ID_PIOB,
  49         .type           = CLK_TYPE_PERIPHERAL,
  50 };
  51 static struct clk pioC_clk = {
  52         .name           = "pioC_clk",
  53         .pmc_mask       = 1 << AT91SAM9RL_ID_PIOC,
  54         .type           = CLK_TYPE_PERIPHERAL,
  55 };
  56 static struct clk pioD_clk = {
  57         .name           = "pioD_clk",
  58         .pmc_mask       = 1 << AT91SAM9RL_ID_PIOD,
  59         .type           = CLK_TYPE_PERIPHERAL,
  60 };
  61 static struct clk usart0_clk = {
  62         .name           = "usart0_clk",
  63         .pmc_mask       = 1 << AT91SAM9RL_ID_US0,
  64         .type           = CLK_TYPE_PERIPHERAL,
  65 };
  66 static struct clk usart1_clk = {
  67         .name           = "usart1_clk",
  68         .pmc_mask       = 1 << AT91SAM9RL_ID_US1,
  69         .type           = CLK_TYPE_PERIPHERAL,
  70 };
  71 static struct clk usart2_clk = {
  72         .name           = "usart2_clk",
  73         .pmc_mask       = 1 << AT91SAM9RL_ID_US2,
  74         .type           = CLK_TYPE_PERIPHERAL,
  75 };
  76 static struct clk usart3_clk = {
  77         .name           = "usart3_clk",
  78         .pmc_mask       = 1 << AT91SAM9RL_ID_US3,
  79         .type           = CLK_TYPE_PERIPHERAL,
  80 };
  81 static struct clk mmc_clk = {
  82         .name           = "mci_clk",
  83         .pmc_mask       = 1 << AT91SAM9RL_ID_MCI,
  84         .type           = CLK_TYPE_PERIPHERAL,
  85 };
  86 static struct clk twi0_clk = {
  87         .name           = "twi0_clk",
  88         .pmc_mask       = 1 << AT91SAM9RL_ID_TWI0,
  89         .type           = CLK_TYPE_PERIPHERAL,
  90 };
  91 static struct clk twi1_clk = {
  92         .name           = "twi1_clk",
  93         .pmc_mask       = 1 << AT91SAM9RL_ID_TWI1,
  94         .type           = CLK_TYPE_PERIPHERAL,
  95 };
  96 static struct clk spi_clk = {
  97         .name           = "spi_clk",
  98         .pmc_mask       = 1 << AT91SAM9RL_ID_SPI,
  99         .type           = CLK_TYPE_PERIPHERAL,
 100 };
 101 static struct clk ssc0_clk = {
 102         .name           = "ssc0_clk",
 103         .pmc_mask       = 1 << AT91SAM9RL_ID_SSC0,
 104         .type           = CLK_TYPE_PERIPHERAL,
 105 };
 106 static struct clk ssc1_clk = {
 107         .name           = "ssc1_clk",
 108         .pmc_mask       = 1 << AT91SAM9RL_ID_SSC1,
 109         .type           = CLK_TYPE_PERIPHERAL,
 110 };
 111 static struct clk tc0_clk = {
 112         .name           = "tc0_clk",
 113         .pmc_mask       = 1 << AT91SAM9RL_ID_TC0,
 114         .type           = CLK_TYPE_PERIPHERAL,
 115 };
 116 static struct clk tc1_clk = {
 117         .name           = "tc1_clk",
 118         .pmc_mask       = 1 << AT91SAM9RL_ID_TC1,
 119         .type           = CLK_TYPE_PERIPHERAL,
 120 };
 121 static struct clk tc2_clk = {
 122         .name           = "tc2_clk",
 123         .pmc_mask       = 1 << AT91SAM9RL_ID_TC2,
 124         .type           = CLK_TYPE_PERIPHERAL,
 125 };
 126 static struct clk pwm_clk = {
 127         .name           = "pwm_clk",
 128         .pmc_mask       = 1 << AT91SAM9RL_ID_PWMC,
 129         .type           = CLK_TYPE_PERIPHERAL,
 130 };
 131 static struct clk tsc_clk = {
 132         .name           = "tsc_clk",
 133         .pmc_mask       = 1 << AT91SAM9RL_ID_TSC,
 134         .type           = CLK_TYPE_PERIPHERAL,
 135 };
 136 static struct clk dma_clk = {
 137         .name           = "dma_clk",
 138         .pmc_mask       = 1 << AT91SAM9RL_ID_DMA,
 139         .type           = CLK_TYPE_PERIPHERAL,
 140 };
 141 static struct clk udphs_clk = {
 142         .name           = "udphs_clk",
 143         .pmc_mask       = 1 << AT91SAM9RL_ID_UDPHS,
 144         .type           = CLK_TYPE_PERIPHERAL,
 145 };
 146 static struct clk lcdc_clk = {
 147         .name           = "lcdc_clk",
 148         .pmc_mask       = 1 << AT91SAM9RL_ID_LCDC,
 149         .type           = CLK_TYPE_PERIPHERAL,
 150 };
 151 static struct clk ac97_clk = {
 152         .name           = "ac97_clk",
 153         .pmc_mask       = 1 << AT91SAM9RL_ID_AC97C,
 154         .type           = CLK_TYPE_PERIPHERAL,
 155 };
 156
 157 static struct clk *periph_clocks[] __initdata = {
 158         &pioA_clk,
 159         &pioB_clk,
 160         &pioC_clk,
 161         &pioD_clk,
 162         &usart0_clk,
 163         &usart1_clk,
 164         &usart2_clk,
 165         &usart3_clk,
 166         &mmc_clk,
 167         &twi0_clk,
 168         &twi1_clk,
 169         &spi_clk,
 170         &ssc0_clk,
 171         &ssc1_clk,
 172         &tc0_clk,
 173         &tc1_clk,
 174         &tc2_clk,
 175         &pwm_clk,
 176         &tsc_clk,
 177         &dma_clk,
 178         &udphs_clk,
 179         &lcdc_clk,
 180         &ac97_clk,
 181         // irq0
 182 };
 183
 184 static struct clk_lookup periph_clocks_lookups[] = {
 185         CLKDEV_CON_DEV_ID("hclk", "at91sam9rl-lcdfb.0", &lcdc_clk),
 186         CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
 187         CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
 188         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
 189         CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
 190         CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
 191         CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
 192         CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
 193         CLKDEV_CON_DEV_ID("pclk", "fffc0000.ssc", &ssc0_clk),
 194         CLKDEV_CON_DEV_ID("pclk", "fffc4000.ssc", &ssc1_clk),
 195         CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.0", &twi0_clk),
 196         CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.1", &twi1_clk),
 197         CLKDEV_CON_ID("pioA", &pioA_clk),
 198         CLKDEV_CON_ID("pioB", &pioB_clk),
 199         CLKDEV_CON_ID("pioC", &pioC_clk),
 200         CLKDEV_CON_ID("pioD", &pioD_clk),
 201         /* more lookup table for DT entries */
 202         CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
 203         CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk),
 204         CLKDEV_CON_DEV_ID("usart", "ffffb400.serial", &usart1_clk),
 205         CLKDEV_CON_DEV_ID("usart", "ffffb800.serial", &usart2_clk),
 206         CLKDEV_CON_DEV_ID("usart", "ffffbc00.serial", &usart3_clk),
 207         CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
 208         CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
 209         CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
 210         CLKDEV_CON_DEV_ID("mci_clk", "fffa4000.mmc", &mmc_clk),
 211         CLKDEV_CON_DEV_ID(NULL, "fffa8000.i2c", &twi0_clk),
 212         CLKDEV_CON_DEV_ID(NULL, "fffac000.i2c", &twi1_clk),
 213         CLKDEV_CON_DEV_ID(NULL, "fffc8000.pwm", &pwm_clk),
 214         CLKDEV_CON_DEV_ID(NULL, "ffffc800.pwm", &pwm_clk),
 215         CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
 216         CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
 217         CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk),
 218         CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioD_clk),
 219 };
 220
 221 static struct clk_lookup usart_clocks_lookups[] = {
 222         CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
 223         CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
 224         CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
 225         CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
 226         CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
 227 };
 228
 229 /*
 230  * The two programmable clocks.
 231  * You must configure pin multiplexing to bring these signals out.
 232  */
 233 static struct clk pck0 = {
 234         .name           = "pck0",
 235         .pmc_mask       = AT91_PMC_PCK0,
 236         .type           = CLK_TYPE_PROGRAMMABLE,
 237         .id             = 0,
 238 };
 239 static struct clk pck1 = {
 240         .name           = "pck1",
 241         .pmc_mask       = AT91_PMC_PCK1,
 242         .type           = CLK_TYPE_PROGRAMMABLE,
 243         .id             = 1,
 244 };
 245
 246 static void __init at91sam9rl_register_clocks(void)
 247 {
 248         int i;
 249
 250         for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
 251                 clk_register(periph_clocks[i]);
 252
 253         clkdev_add_table(periph_clocks_lookups,
 254                          ARRAY_SIZE(periph_clocks_lookups));
 255         clkdev_add_table(usart_clocks_lookups,
 256                          ARRAY_SIZE(usart_clocks_lookups));
 257
 258         clk_register(&pck0);
 259         clk_register(&pck1);
 260 }
 261 #endif
 262
 263 /* --------------------------------------------------------------------
 264  *  GPIO
 265  * -------------------------------------------------------------------- */
 266
 267 static struct at91_gpio_bank at91sam9rl_gpio[] __initdata = {
 268         {
 269                 .id             = AT91SAM9RL_ID_PIOA,
 270                 .regbase        = AT91SAM9RL_BASE_PIOA,
 271         }, {
 272                 .id             = AT91SAM9RL_ID_PIOB,
 273                 .regbase        = AT91SAM9RL_BASE_PIOB,
 274         }, {
 275                 .id             = AT91SAM9RL_ID_PIOC,
 276                 .regbase        = AT91SAM9RL_BASE_PIOC,
 277         }, {
 278                 .id             = AT91SAM9RL_ID_PIOD,
 279                 .regbase        = AT91SAM9RL_BASE_PIOD,
 280         }
 281 };
 282
 283 /* --------------------------------------------------------------------
 284  *  AT91SAM9RL processor initialization
 285  * -------------------------------------------------------------------- */
 286
 287 static void __init at91sam9rl_map_io(void)
 288 {
 289         unsigned long sram_size;
 290
 291         switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) {
 292                 case AT91_CIDR_SRAMSIZ_32K:
 293                         sram_size = 2 * SZ_16K;
 294                         break;
 295                 case AT91_CIDR_SRAMSIZ_16K:
 296                 default:
 297                         sram_size = SZ_16K;
 298         }
 299
 300         /* Map SRAM */
 301         at91_init_sram(0, AT91SAM9RL_SRAM_BASE, sram_size);
 302 }
 303
 304 static void __init at91sam9rl_ioremap_registers(void)
 305 {
 306         at91_ioremap_shdwc(AT91SAM9RL_BASE_SHDWC);
 307         at91_ioremap_rstc(AT91SAM9RL_BASE_RSTC);
 308         at91_ioremap_ramc(0, AT91SAM9RL_BASE_SDRAMC, 512);
 309         at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT);
 310         at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC);
 311         at91_ioremap_matrix(AT91SAM9RL_BASE_MATRIX);
 312         at91_pm_set_standby(at91sam9_sdram_standby);
 313 }
 314
 315 static void __init at91sam9rl_initialize(void)
 316 {
 317         arm_pm_idle = at91sam9_idle;
 318         arm_pm_restart = at91sam9_alt_restart;
 319
 320         at91_sysirq_mask_rtc(AT91SAM9RL_BASE_RTC);
 321         at91_sysirq_mask_rtt(AT91SAM9RL_BASE_RTT);
 322
 323         /* Register GPIO subsystem */
 324         at91_gpio_init(at91sam9rl_gpio, 4);
 325 }
 326
 327 /* --------------------------------------------------------------------
 328  *  Interrupt initialization
 329  * -------------------------------------------------------------------- */
 330
 331 /*
 332  * The default interrupt priority levels (0 = lowest, 7 = highest).
 333  */
 334 static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = {
 335         7,      /* Advanced Interrupt Controller */
 336         7,      /* System Peripherals */
 337         1,      /* Parallel IO Controller A */
 338         1,      /* Parallel IO Controller B */
 339         1,      /* Parallel IO Controller C */
 340         1,      /* Parallel IO Controller D */
 341         5,      /* USART 0 */
 342         5,      /* USART 1 */
 343         5,      /* USART 2 */
 344         5,      /* USART 3 */
 345         0,      /* Multimedia Card Interface */
 346         6,      /* Two-Wire Interface 0 */
 347         6,      /* Two-Wire Interface 1 */
 348         5,      /* Serial Peripheral Interface */
 349         4,      /* Serial Synchronous Controller 0 */
 350         4,      /* Serial Synchronous Controller 1 */
 351         0,      /* Timer Counter 0 */
 352         0,      /* Timer Counter 1 */
 353         0,      /* Timer Counter 2 */
 354         0,
 355         0,      /* Touch Screen Controller */
 356         0,      /* DMA Controller */
 357         2,      /* USB Device High speed port */
 358         2,      /* LCD Controller */
 359         6,      /* AC97 Controller */
 360         0,
 361         0,
 362         0,
 363         0,
 364         0,
 365         0,
 366         0,      /* Advanced Interrupt Controller */
 367 };
 368
 369 AT91_SOC_START(at91sam9rl)
 370         .map_io = at91sam9rl_map_io,
 371         .default_irq_priority = at91sam9rl_default_irq_priority,
 372         .extern_irq = (1 << AT91SAM9RL_ID_IRQ0),
 373         .ioremap_registers = at91sam9rl_ioremap_registers,
 374 #if defined(CONFIG_OLD_CLK_AT91)
 375         .register_clocks = at91sam9rl_register_clocks,
 376 #endif
 377         .init = at91sam9rl_initialize,
 378 AT91_SOC_END