arch/arm/mach-at91/at91sam9261.c

   1 /*
   2  * arch/arm/mach-at91/at91sam9261.c
   3  *
   4  *  Copyright (C) 2005 SAN People
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/clk/at91_pmc.h>
  15
  16 #include <asm/proc-fns.h>
  17 #include <asm/irq.h>
  18 #include <asm/mach/arch.h>
  19 #include <asm/mach/map.h>
  20 #include <asm/system_misc.h>
  21 #include <mach/cpu.h>
  22 #include <mach/at91sam9261.h>
  23 #include <mach/hardware.h>
  24
  25 #include "at91_aic.h"
  26 #include "at91_rstc.h"
  27 #include "soc.h"
  28 #include "generic.h"
  29 #include "clock.h"
  30 #include "sam9_smc.h"
  31 #include "pm.h"
  32
  33 /* --------------------------------------------------------------------
  34  *  Clocks
  35  * -------------------------------------------------------------------- */
  36
  37 /*
  38  * The peripheral clocks.
  39  */
  40 static struct clk pioA_clk = {
  41         .name           = "pioA_clk",
  42         .pmc_mask       = 1 << AT91SAM9261_ID_PIOA,
  43         .type           = CLK_TYPE_PERIPHERAL,
  44 };
  45 static struct clk pioB_clk = {
  46         .name           = "pioB_clk",
  47         .pmc_mask       = 1 << AT91SAM9261_ID_PIOB,
  48         .type           = CLK_TYPE_PERIPHERAL,
  49 };
  50 static struct clk pioC_clk = {
  51         .name           = "pioC_clk",
  52         .pmc_mask       = 1 << AT91SAM9261_ID_PIOC,
  53         .type           = CLK_TYPE_PERIPHERAL,
  54 };
  55 static struct clk usart0_clk = {
  56         .name           = "usart0_clk",
  57         .pmc_mask       = 1 << AT91SAM9261_ID_US0,
  58         .type           = CLK_TYPE_PERIPHERAL,
  59 };
  60 static struct clk usart1_clk = {
  61         .name           = "usart1_clk",
  62         .pmc_mask       = 1 << AT91SAM9261_ID_US1,
  63         .type           = CLK_TYPE_PERIPHERAL,
  64 };
  65 static struct clk usart2_clk = {
  66         .name           = "usart2_clk",
  67         .pmc_mask       = 1 << AT91SAM9261_ID_US2,
  68         .type           = CLK_TYPE_PERIPHERAL,
  69 };
  70 static struct clk mmc_clk = {
  71         .name           = "mci_clk",
  72         .pmc_mask       = 1 << AT91SAM9261_ID_MCI,
  73         .type           = CLK_TYPE_PERIPHERAL,
  74 };
  75 static struct clk udc_clk = {
  76         .name           = "udc_clk",
  77         .pmc_mask       = 1 << AT91SAM9261_ID_UDP,
  78         .type           = CLK_TYPE_PERIPHERAL,
  79 };
  80 static struct clk twi_clk = {
  81         .name           = "twi_clk",
  82         .pmc_mask       = 1 << AT91SAM9261_ID_TWI,
  83         .type           = CLK_TYPE_PERIPHERAL,
  84 };
  85 static struct clk spi0_clk = {
  86         .name           = "spi0_clk",
  87         .pmc_mask       = 1 << AT91SAM9261_ID_SPI0,
  88         .type           = CLK_TYPE_PERIPHERAL,
  89 };
  90 static struct clk spi1_clk = {
  91         .name           = "spi1_clk",
  92         .pmc_mask       = 1 << AT91SAM9261_ID_SPI1,
  93         .type           = CLK_TYPE_PERIPHERAL,
  94 };
  95 static struct clk ssc0_clk = {
  96         .name           = "ssc0_clk",
  97         .pmc_mask       = 1 << AT91SAM9261_ID_SSC0,
  98         .type           = CLK_TYPE_PERIPHERAL,
  99 };
 100 static struct clk ssc1_clk = {
 101         .name           = "ssc1_clk",
 102         .pmc_mask       = 1 << AT91SAM9261_ID_SSC1,
 103         .type           = CLK_TYPE_PERIPHERAL,
 104 };
 105 static struct clk ssc2_clk = {
 106         .name           = "ssc2_clk",
 107         .pmc_mask       = 1 << AT91SAM9261_ID_SSC2,
 108         .type           = CLK_TYPE_PERIPHERAL,
 109 };
 110 static struct clk tc0_clk = {
 111         .name           = "tc0_clk",
 112         .pmc_mask       = 1 << AT91SAM9261_ID_TC0,
 113         .type           = CLK_TYPE_PERIPHERAL,
 114 };
 115 static struct clk tc1_clk = {
 116         .name           = "tc1_clk",
 117         .pmc_mask       = 1 << AT91SAM9261_ID_TC1,
 118         .type           = CLK_TYPE_PERIPHERAL,
 119 };
 120 static struct clk tc2_clk = {
 121         .name           = "tc2_clk",
 122         .pmc_mask       = 1 << AT91SAM9261_ID_TC2,
 123         .type           = CLK_TYPE_PERIPHERAL,
 124 };
 125 static struct clk ohci_clk = {
 126         .name           = "ohci_clk",
 127         .pmc_mask       = 1 << AT91SAM9261_ID_UHP,
 128         .type           = CLK_TYPE_PERIPHERAL,
 129 };
 130 static struct clk lcdc_clk = {
 131         .name           = "lcdc_clk",
 132         .pmc_mask       = 1 << AT91SAM9261_ID_LCDC,
 133         .type           = CLK_TYPE_PERIPHERAL,
 134 };
 135
 136 /* HClocks */
 137 static struct clk hck0 = {
 138         .name           = "hck0",
 139         .pmc_mask       = AT91_PMC_HCK0,
 140         .type           = CLK_TYPE_SYSTEM,
 141         .id             = 0,
 142 };
 143 static struct clk hck1 = {
 144         .name           = "hck1",
 145         .pmc_mask       = AT91_PMC_HCK1,
 146         .type           = CLK_TYPE_SYSTEM,
 147         .id             = 1,
 148 };
 149
 150 static struct clk *periph_clocks[] __initdata = {
 151         &pioA_clk,
 152         &pioB_clk,
 153         &pioC_clk,
 154         &usart0_clk,
 155         &usart1_clk,
 156         &usart2_clk,
 157         &mmc_clk,
 158         &udc_clk,
 159         &twi_clk,
 160         &spi0_clk,
 161         &spi1_clk,
 162         &ssc0_clk,
 163         &ssc1_clk,
 164         &ssc2_clk,
 165         &tc0_clk,
 166         &tc1_clk,
 167         &tc2_clk,
 168         &ohci_clk,
 169         &lcdc_clk,
 170         // irq0 .. irq2
 171 };
 172
 173 static struct clk_lookup periph_clocks_lookups[] = {
 174         CLKDEV_CON_DEV_ID("hclk", "at91sam9261-lcdfb.0", &hck1),
 175         CLKDEV_CON_DEV_ID("hclk", "at91sam9g10-lcdfb.0", &hck1),
 176         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
 177         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
 178         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
 179         CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
 180         CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
 181         CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
 182         CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
 183         CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.2", &ssc2_clk),
 184         CLKDEV_CON_DEV_ID("pclk", "fffbc000.ssc", &ssc0_clk),
 185         CLKDEV_CON_DEV_ID("pclk", "fffc0000.ssc", &ssc1_clk),
 186         CLKDEV_CON_DEV_ID("pclk", "fffc4000.ssc", &ssc2_clk),
 187         CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &hck0),
 188         CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9261.0", &twi_clk),
 189         CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.0", &twi_clk),
 190         CLKDEV_CON_ID("pioA", &pioA_clk),
 191         CLKDEV_CON_ID("pioB", &pioB_clk),
 192         CLKDEV_CON_ID("pioC", &pioC_clk),
 193 };
 194
 195 static struct clk_lookup usart_clocks_lookups[] = {
 196         CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
 197         CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
 198         CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
 199         CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
 200 };
 201
 202 /*
 203  * The four programmable clocks.
 204  * You must configure pin multiplexing to bring these signals out.
 205  */
 206 static struct clk pck0 = {
 207         .name           = "pck0",
 208         .pmc_mask       = AT91_PMC_PCK0,
 209         .type           = CLK_TYPE_PROGRAMMABLE,
 210         .id             = 0,
 211 };
 212 static struct clk pck1 = {
 213         .name           = "pck1",
 214         .pmc_mask       = AT91_PMC_PCK1,
 215         .type           = CLK_TYPE_PROGRAMMABLE,
 216         .id             = 1,
 217 };
 218 static struct clk pck2 = {
 219         .name           = "pck2",
 220         .pmc_mask       = AT91_PMC_PCK2,
 221         .type           = CLK_TYPE_PROGRAMMABLE,
 222         .id             = 2,
 223 };
 224 static struct clk pck3 = {
 225         .name           = "pck3",
 226         .pmc_mask       = AT91_PMC_PCK3,
 227         .type           = CLK_TYPE_PROGRAMMABLE,
 228         .id             = 3,
 229 };
 230
 231 static void __init at91sam9261_register_clocks(void)
 232 {
 233         int i;
 234
 235         for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
 236                 clk_register(periph_clocks[i]);
 237
 238         clkdev_add_table(periph_clocks_lookups,
 239                          ARRAY_SIZE(periph_clocks_lookups));
 240         clkdev_add_table(usart_clocks_lookups,
 241                          ARRAY_SIZE(usart_clocks_lookups));
 242
 243         clk_register(&pck0);
 244         clk_register(&pck1);
 245         clk_register(&pck2);
 246         clk_register(&pck3);
 247
 248         clk_register(&hck0);
 249         clk_register(&hck1);
 250 }
 251
 252 /* --------------------------------------------------------------------
 253  *  GPIO
 254  * -------------------------------------------------------------------- */
 255
 256 static struct at91_gpio_bank at91sam9261_gpio[] __initdata = {
 257         {
 258                 .id             = AT91SAM9261_ID_PIOA,
 259                 .regbase        = AT91SAM9261_BASE_PIOA,
 260         }, {
 261                 .id             = AT91SAM9261_ID_PIOB,
 262                 .regbase        = AT91SAM9261_BASE_PIOB,
 263         }, {
 264                 .id             = AT91SAM9261_ID_PIOC,
 265                 .regbase        = AT91SAM9261_BASE_PIOC,
 266         }
 267 };
 268
 269 /* --------------------------------------------------------------------
 270  *  AT91SAM9261 processor initialization
 271  * -------------------------------------------------------------------- */
 272
 273 static void __init at91sam9261_map_io(void)
 274 {
 275         if (cpu_is_at91sam9g10())
 276                 at91_init_sram(0, AT91SAM9G10_SRAM_BASE, AT91SAM9G10_SRAM_SIZE);
 277         else
 278                 at91_init_sram(0, AT91SAM9261_SRAM_BASE, AT91SAM9261_SRAM_SIZE);
 279 }
 280
 281 static void __init at91sam9261_ioremap_registers(void)
 282 {
 283         at91_ioremap_shdwc(AT91SAM9261_BASE_SHDWC);
 284         at91_ioremap_rstc(AT91SAM9261_BASE_RSTC);
 285         at91_ioremap_ramc(0, AT91SAM9261_BASE_SDRAMC, 512);
 286         at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT);
 287         at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC);
 288         at91_ioremap_matrix(AT91SAM9261_BASE_MATRIX);
 289         at91_pm_set_standby(at91sam9_sdram_standby);
 290 }
 291
 292 static void __init at91sam9261_initialize(void)
 293 {
 294         arm_pm_idle = at91sam9_idle;
 295         arm_pm_restart = at91sam9_alt_restart;
 296
 297         at91_sysirq_mask_rtt(AT91SAM9261_BASE_RTT);
 298
 299         /* Register GPIO subsystem */
 300         at91_gpio_init(at91sam9261_gpio, 3);
 301 }
 302
 303 /* --------------------------------------------------------------------
 304  *  Interrupt initialization
 305  * -------------------------------------------------------------------- */
 306
 307 /*
 308  * The default interrupt priority levels (0 = lowest, 7 = highest).
 309  */
 310 static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = {
 311         7,      /* Advanced Interrupt Controller */
 312         7,      /* System Peripherals */
 313         1,      /* Parallel IO Controller A */
 314         1,      /* Parallel IO Controller B */
 315         1,      /* Parallel IO Controller C */
 316         0,
 317         5,      /* USART 0 */
 318         5,      /* USART 1 */
 319         5,      /* USART 2 */
 320         0,      /* Multimedia Card Interface */
 321         2,      /* USB Device Port */
 322         6,      /* Two-Wire Interface */
 323         5,      /* Serial Peripheral Interface 0 */
 324         5,      /* Serial Peripheral Interface 1 */
 325         4,      /* Serial Synchronous Controller 0 */
 326         4,      /* Serial Synchronous Controller 1 */
 327         4,      /* Serial Synchronous Controller 2 */
 328         0,      /* Timer Counter 0 */
 329         0,      /* Timer Counter 1 */
 330         0,      /* Timer Counter 2 */
 331         2,      /* USB Host port */
 332         3,      /* LCD Controller */
 333         0,
 334         0,
 335         0,
 336         0,
 337         0,
 338         0,
 339         0,
 340         0,      /* Advanced Interrupt Controller */
 341         0,      /* Advanced Interrupt Controller */
 342         0,      /* Advanced Interrupt Controller */
 343 };
 344
 345 AT91_SOC_START(at91sam9261)
 346         .map_io = at91sam9261_map_io,
 347         .default_irq_priority = at91sam9261_default_irq_priority,
 348         .extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
 349                     | (1 << AT91SAM9261_ID_IRQ2),
 350         .ioremap_registers = at91sam9261_ioremap_registers,
 351         .register_clocks = at91sam9261_register_clocks,
 352         .init = at91sam9261_initialize,
 353 AT91_SOC_END