arch/arm/boot/dts/vf610-twr.dts

   1 /*
   2  * Copyright 2013 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9
  10 /dts-v1/;
  11 #include "vf610.dtsi"
  12
  13 / {
  14         model = "VF610 Tower Board";
  15         compatible = "fsl,vf610-twr", "fsl,vf610";
  16
  17         chosen {
  18                 bootargs = "console=ttyLP1,115200";
  19         };
  20
  21         memory {
  22                 reg = <0x80000000 0x8000000>;
  23         };
  24
  25         clocks {
  26                 audio_ext {
  27                         compatible = "fixed-clock";
  28                         clock-frequency = <24576000>;
  29                 };
  30
  31                 enet_ext {
  32                         compatible = "fixed-clock";
  33                         clock-frequency = <50000000>;
  34                 };
  35         };
  36
  37         regulators {
  38                 compatible = "simple-bus";
  39                 #address-cells = <1>;
  40                 #size-cells = <0>;
  41
  42                 reg_3p3v: regulator@0 {
  43                         compatible = "regulator-fixed";
  44                         reg = <0>;
  45                         regulator-name = "3P3V";
  46                         regulator-min-microvolt = <3300000>;
  47                         regulator-max-microvolt = <3300000>;
  48                         regulator-always-on;
  49                 };
  50
  51                 reg_vcc_3v3_mcu: regulator@1 {
  52                         compatible = "regulator-fixed";
  53                         reg = <1>;
  54                         regulator-name = "vcc_3v3_mcu";
  55                         regulator-min-microvolt = <3300000>;
  56                         regulator-max-microvolt = <3300000>;
  57                 };
  58         };
  59
  60         sound {
  61                 compatible = "simple-audio-card";
  62                 simple-audio-card,format = "i2s";
  63                 simple-audio-card,widgets =
  64                         "Microphone", "Microphone Jack",
  65                         "Headphone", "Headphone Jack",
  66                         "Speaker", "Speaker Ext",
  67                         "Line", "Line In Jack";
  68                 simple-audio-card,routing =
  69                         "MIC_IN", "Microphone Jack",
  70                         "Microphone Jack", "Mic Bias",
  71                         "LINE_IN", "Line In Jack",
  72                         "Headphone Jack", "HP_OUT",
  73                         "Speaker Ext", "LINE_OUT";
  74
  75                 simple-audio-card,cpu {
  76                         sound-dai = <&sai2>;
  77                         master-clkdir-out;
  78                         frame-master;
  79                         bitclock-master;
  80                 };
  81
  82                 simple-audio-card,codec {
  83                         sound-dai = <&codec>;
  84                         frame-master;
  85                         bitclock-master;
  86                 };
  87         };
  88 };
  89
  90 &adc0 {
  91         pinctrl-names = "default";
  92         pinctrl-0 = <&pinctrl_adc0_ad5>;
  93         vref-supply = <&reg_vcc_3v3_mcu>;
  94         status = "okay";
  95 };
  96
  97 &dspi0 {
  98         bus-num = <0>;
  99         pinctrl-names = "default";
 100         pinctrl-0 = <&pinctrl_dspi0>;
 101         status = "okay";
 102
 103         sflash: at26df081a@0 {
 104                 #address-cells = <1>;
 105                 #size-cells = <1>;
 106                 compatible = "atmel,at26df081a";
 107                 spi-max-frequency = <16000000>;
 108                 spi-cpol;
 109                 spi-cpha;
 110                 reg = <0>;
 111         };
 112 };
 113
 114 &fec0 {
 115         phy-mode = "rmii";
 116         pinctrl-names = "default";
 117         pinctrl-0 = <&pinctrl_fec0>;
 118         status = "okay";
 119 };
 120
 121 &fec1 {
 122         phy-mode = "rmii";
 123         pinctrl-names = "default";
 124         pinctrl-0 = <&pinctrl_fec1>;
 125         status = "okay";
 126 };
 127
 128 &i2c0 {
 129         clock-frequency = <100000>;
 130         pinctrl-names = "default";
 131         pinctrl-0 = <&pinctrl_i2c0>;
 132         status = "okay";
 133
 134         codec: sgtl5000@0a {
 135                #sound-dai-cells = <0>;
 136                compatible = "fsl,sgtl5000";
 137                reg = <0x0a>;
 138                VDDA-supply = <&reg_3p3v>;
 139                VDDIO-supply = <&reg_3p3v>;
 140                clocks = <&clks VF610_CLK_SAI2>;
 141        };
 142 };
 143
 144 &iomuxc {
 145         vf610-twr {
 146                 pinctrl_adc0_ad5: adc0ad5grp {
 147                         fsl,pins = <
 148                                 VF610_PAD_PTC30__ADC0_SE5               0xa1
 149                         >;
 150                 };
 151
 152                 pinctrl_dspi0: dspi0grp {
 153                         fsl,pins = <
 154                                 VF610_PAD_PTB19__DSPI0_CS0              0x1182
 155                                 VF610_PAD_PTB20__DSPI0_SIN              0x1181
 156                                 VF610_PAD_PTB21__DSPI0_SOUT             0x1182
 157                                 VF610_PAD_PTB22__DSPI0_SCK              0x1182
 158                         >;
 159                 };
 160
 161                 pinctrl_fec0: fec0grp {
 162                         fsl,pins = <
 163                                 VF610_PAD_PTA6__RMII_CLKIN              0x30d1
 164                                 VF610_PAD_PTC0__ENET_RMII0_MDC          0x30d3
 165                                 VF610_PAD_PTC1__ENET_RMII0_MDIO         0x30d1
 166                                 VF610_PAD_PTC2__ENET_RMII0_CRS          0x30d1
 167                                 VF610_PAD_PTC3__ENET_RMII0_RXD1         0x30d1
 168                                 VF610_PAD_PTC4__ENET_RMII0_RXD0         0x30d1
 169                                 VF610_PAD_PTC5__ENET_RMII0_RXER         0x30d1
 170                                 VF610_PAD_PTC6__ENET_RMII0_TXD1         0x30d2
 171                                 VF610_PAD_PTC7__ENET_RMII0_TXD0         0x30d2
 172                                 VF610_PAD_PTC8__ENET_RMII0_TXEN         0x30d2
 173                         >;
 174                 };
 175
 176                 pinctrl_fec1: fec1grp {
 177                         fsl,pins = <
 178                                 VF610_PAD_PTC9__ENET_RMII1_MDC          0x30d2
 179                                 VF610_PAD_PTC10__ENET_RMII1_MDIO        0x30d3
 180                                 VF610_PAD_PTC11__ENET_RMII1_CRS         0x30d1
 181                                 VF610_PAD_PTC12__ENET_RMII_RXD1         0x30d1
 182                                 VF610_PAD_PTC13__ENET_RMII1_RXD0        0x30d1
 183                                 VF610_PAD_PTC14__ENET_RMII1_RXER        0x30d1
 184                                 VF610_PAD_PTC15__ENET_RMII1_TXD1        0x30d2
 185                                 VF610_PAD_PTC16__ENET_RMII1_TXD0        0x30d2
 186                                 VF610_PAD_PTC17__ENET_RMII1_TXEN        0x30d2
 187                         >;
 188                 };
 189
 190                 pinctrl_i2c0: i2c0grp {
 191                         fsl,pins = <
 192                                 VF610_PAD_PTB14__I2C0_SCL               0x30d3
 193                                 VF610_PAD_PTB15__I2C0_SDA               0x30d3
 194                         >;
 195                 };
 196
 197                 pinctrl_sai2: sai2grp {
 198                         fsl,pins = <
 199                                 VF610_PAD_PTA16__SAI2_TX_BCLK           0x02ed
 200                                 VF610_PAD_PTA18__SAI2_TX_DATA           0x02ee
 201                                 VF610_PAD_PTA19__SAI2_TX_SYNC           0x02ed
 202                                 VF610_PAD_PTA21__SAI2_RX_BCLK           0x02ed
 203                                 VF610_PAD_PTA22__SAI2_RX_DATA           0x02ed
 204                                 VF610_PAD_PTA23__SAI2_RX_SYNC           0x02ed
 205                                 VF610_PAD_PTB18__EXT_AUDIO_MCLK         0x02ed
 206                         >;
 207                 };
 208
 209                 pinctrl_uart1: uart1grp {
 210                         fsl,pins = <
 211                                 VF610_PAD_PTB4__UART1_TX                0x21a2
 212                                 VF610_PAD_PTB5__UART1_RX                0x21a1
 213                         >;
 214                 };
 215         };
 216 };
 217
 218 &sai2 {
 219         #sound-dai-cells = <0>;
 220         pinctrl-names = "default";
 221         pinctrl-0 = <&pinctrl_sai2>;
 222         status = "okay";
 223 };
 224
 225 &uart1 {
 226         pinctrl-names = "default";
 227         pinctrl-0 = <&pinctrl_uart1>;
 228         status = "okay";
 229 };