arch/arm/boot/dts/stih416-pinctrl.dtsi

   1
   2 /*
   3  * Copyright (C) 2013 STMicroelectronics Limited.
   4  * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * publishhed by the Free Software Foundation.
   9  */
  10 #include "st-pincfg.h"
  11 / {
  12
  13         aliases {
  14                 gpio0   = &PIO0;
  15                 gpio1   = &PIO1;
  16                 gpio2   = &PIO2;
  17                 gpio3   = &PIO3;
  18                 gpio4   = &PIO4;
  19                 gpio5   = &PIO40;
  20                 gpio6   = &PIO5;
  21                 gpio7   = &PIO6;
  22                 gpio8   = &PIO7;
  23                 gpio9   = &PIO8;
  24                 gpio10  = &PIO9;
  25                 gpio11  = &PIO10;
  26                 gpio12  = &PIO11;
  27                 gpio13  = &PIO12;
  28                 gpio14  = &PIO30;
  29                 gpio15  = &PIO31;
  30                 gpio16  = &PIO13;
  31                 gpio17  = &PIO14;
  32                 gpio18  = &PIO15;
  33                 gpio19  = &PIO16;
  34                 gpio20  = &PIO17;
  35                 gpio21  = &PIO18;
  36                 gpio22  = &PIO100;
  37                 gpio23  = &PIO101;
  38                 gpio24  = &PIO102;
  39                 gpio25  = &PIO103;
  40                 gpio26  = &PIO104;
  41                 gpio27  = &PIO105;
  42                 gpio28  = &PIO106;
  43                 gpio29  = &PIO107;
  44         };
  45
  46         soc {
  47                 pin-controller-sbc {
  48                         #address-cells  = <1>;
  49                         #size-cells     = <1>;
  50                         compatible      = "st,stih416-sbc-pinctrl";
  51                         st,syscfg       = <&syscfg_sbc>;
  52                         ranges          = <0 0xfe610000 0x6000>;
  53
  54                         PIO0: gpio@fe610000 {
  55                                 gpio-controller;
  56                                 #gpio-cells = <1>;
  57                                 reg             = <0 0x100>;
  58                                 st,bank-name    = "PIO0";
  59                         };
  60                         PIO1: gpio@fe611000 {
  61                                 gpio-controller;
  62                                 #gpio-cells     = <1>;
  63                                 reg             = <0x1000 0x100>;
  64                                 st,bank-name    = "PIO1";
  65                         };
  66                         PIO2: gpio@fe612000 {
  67                                 gpio-controller;
  68                                 #gpio-cells     = <1>;
  69                                 reg             = <0x2000 0x100>;
  70                                 st,bank-name    = "PIO2";
  71                         };
  72                         PIO3: gpio@fe613000 {
  73                                 gpio-controller;
  74                                 #gpio-cells     = <1>;
  75                                 reg             = <0x3000 0x100>;
  76                                 st,bank-name    = "PIO3";
  77                         };
  78                         PIO4: gpio@fe614000 {
  79                                 gpio-controller;
  80                                 #gpio-cells     = <1>;
  81                                 reg             = <0x4000 0x100>;
  82                                 st,bank-name    = "PIO4";
  83                         };
  84                         PIO40: gpio@fe615000 {
  85                                 gpio-controller;
  86                                 #gpio-cells     = <1>;
  87                                 reg             = <0x5000 0x100>;
  88                                 st,bank-name    = "PIO40";
  89                                 st,retime-pin-mask = <0x7f>;
  90                         };
  91
  92                         sbc_serial1 {
  93                                 pinctrl_sbc_serial1: sbc_serial1 {
  94                                         st,pins {
  95                                                 tx      = <&PIO2 6 ALT3 OUT>;
  96                                                 rx      = <&PIO2 7 ALT3 IN>;
  97                                         };
  98                                 };
  99                         };
 100
 101                         sbc_i2c0 {
 102                                 pinctrl_sbc_i2c0_default: sbc_i2c0-default {
 103                                         st,pins {
 104                                                 sda = <&PIO4 6 ALT1 BIDIR>;
 105                                                 scl = <&PIO4 5 ALT1 BIDIR>;
 106                                         };
 107                                 };
 108                         };
 109
 110                         sbc_i2c1 {
 111                                 pinctrl_sbc_i2c1_default: sbc_i2c1-default {
 112                                         st,pins {
 113                                                 sda = <&PIO3 2 ALT2 BIDIR>;
 114                                                 scl = <&PIO3 1 ALT2 BIDIR>;
 115                                         };
 116                                 };
 117                         };
 118                 };
 119
 120                 pin-controller-front {
 121                         #address-cells  = <1>;
 122                         #size-cells     = <1>;
 123                         compatible      = "st,stih416-front-pinctrl";
 124                         st,syscfg       = <&syscfg_front>;
 125                         ranges          = <0 0xfee00000 0x10000>;
 126
 127                         PIO5: gpio@fee00000 {
 128                                 gpio-controller;
 129                                 #gpio-cells     = <1>;
 130                                 reg             = <0 0x100>;
 131                                 st,bank-name    = "PIO5";
 132                         };
 133                         PIO6: gpio@fee01000 {
 134                                 gpio-controller;
 135                                 #gpio-cells     = <1>;
 136                                 reg             = <0x1000 0x100>;
 137                                 st,bank-name    = "PIO6";
 138                         };
 139                         PIO7: gpio@fee02000 {
 140                                 gpio-controller;
 141                                 #gpio-cells     = <1>;
 142                                 reg             = <0x2000 0x100>;
 143                                 st,bank-name    = "PIO7";
 144                         };
 145                         PIO8: gpio@fee03000 {
 146                                 gpio-controller;
 147                                 #gpio-cells     = <1>;
 148                                 reg             = <0x3000 0x100>;
 149                                 st,bank-name    = "PIO8";
 150                         };
 151                         PIO9: gpio@fee04000 {
 152                                 gpio-controller;
 153                                 #gpio-cells     = <1>;
 154                                 reg             = <0x4000 0x100>;
 155                                 st,bank-name    = "PIO9";
 156                         };
 157                         PIO10: gpio@fee05000 {
 158                                 gpio-controller;
 159                                 #gpio-cells     = <1>;
 160                                 reg             = <0x5000 0x100>;
 161                                 st,bank-name    = "PIO10";
 162                         };
 163                         PIO11: gpio@fee06000 {
 164                                 gpio-controller;
 165                                 #gpio-cells     = <1>;
 166                                 reg             = <0x6000 0x100>;
 167                                 st,bank-name    = "PIO11";
 168                         };
 169                         PIO12: gpio@fee07000 {
 170                                 gpio-controller;
 171                                 #gpio-cells     = <1>;
 172                                 reg             = <0x7000 0x100>;
 173                                 st,bank-name    = "PIO12";
 174                         };
 175                         PIO30: gpio@fee08000 {
 176                                 gpio-controller;
 177                                 #gpio-cells     = <1>;
 178                                 reg             = <0x8000 0x100>;
 179                                 st,bank-name    = "PIO30";
 180                         };
 181                         PIO31: gpio@fee09000 {
 182                                 gpio-controller;
 183                                 #gpio-cells     = <1>;
 184                                 reg             = <0x9000 0x100>;
 185                                 st,bank-name    = "PIO31";
 186                         };
 187
 188                         serial2-oe {
 189                                 pinctrl_serial2_oe: serial2-1 {
 190                                         st,pins {
 191                                                 output-enable   = <&PIO11 3 ALT2 OUT>;
 192                                         };
 193                                 };
 194                         };
 195
 196                         i2c0 {
 197                                 pinctrl_i2c0_default: i2c0-default {
 198                                         st,pins {
 199                                                 sda = <&PIO9 3 ALT1 BIDIR>;
 200                                                 scl = <&PIO9 2 ALT1 BIDIR>;
 201                                         };
 202                                 };
 203                         };
 204
 205                         i2c1 {
 206                                 pinctrl_i2c1_default: i2c1-default {
 207                                         st,pins {
 208                                                 sda = <&PIO12 1 ALT1 BIDIR>;
 209                                                 scl = <&PIO12 0 ALT1 BIDIR>;
 210                                         };
 211                                 };
 212                         };
 213                 };
 214
 215                 pin-controller-rear {
 216                         #address-cells  = <1>;
 217                         #size-cells     = <1>;
 218                         compatible      = "st,stih416-rear-pinctrl";
 219                         st,syscfg       = <&syscfg_rear>;
 220                         ranges          = <0 0xfe820000 0x6000>;
 221
 222                         PIO13: gpio@fe820000 {
 223                                 gpio-controller;
 224                                 #gpio-cells     = <1>;
 225                                 reg             = <0 0x100>;
 226                                 st,bank-name    = "PIO13";
 227                         };
 228                         PIO14: gpio@fe821000 {
 229                                 gpio-controller;
 230                                 #gpio-cells     = <1>;
 231                                 reg             = <0x1000 0x100>;
 232                                 st,bank-name    = "PIO14";
 233                         };
 234                         PIO15: gpio@fe822000 {
 235                                 gpio-controller;
 236                                 #gpio-cells     = <1>;
 237                                 reg             = <0x2000 0x100>;
 238                                 st,bank-name    = "PIO15";
 239                         };
 240                         PIO16: gpio@fe823000 {
 241                                 gpio-controller;
 242                                 #gpio-cells     = <1>;
 243                                 reg             = <0x3000 0x100>;
 244                                 st,bank-name    = "PIO16";
 245                         };
 246                         PIO17: gpio@fe824000 {
 247                                 gpio-controller;
 248                                 #gpio-cells     = <1>;
 249                                 reg             = <0x4000 0x100>;
 250                                 st,bank-name    = "PIO17";
 251                         };
 252                         PIO18: gpio@fe825000 {
 253                                 gpio-controller;
 254                                 #gpio-cells     = <1>;
 255                                 reg             = <0x5000 0x100>;
 256                                 st,bank-name    = "PIO18";
 257                                 st,retime-pin-mask = <0xf>;
 258                         };
 259
 260                         serial2 {
 261                                 pinctrl_serial2: serial2-0 {
 262                                         st,pins {
 263                                                 tx      = <&PIO17 4 ALT2 OUT>;
 264                                                 rx      = <&PIO17 5 ALT2 IN>;
 265                                         };
 266                                 };
 267                         };
 268                 };
 269
 270                 pin-controller-fvdp-fe {
 271                         #address-cells  = <1>;
 272                         #size-cells     = <1>;
 273                         compatible      = "st,stih416-fvdp-fe-pinctrl";
 274                         st,syscfg       = <&syscfg_fvdp_fe>;
 275                         ranges          = <0 0xfd6b0000 0x3000>;
 276
 277                         PIO100: gpio@fd6b0000 {
 278                                 gpio-controller;
 279                                 #gpio-cells     = <1>;
 280                                 reg             = <0 0x100>;
 281                                 st,bank-name    = "PIO100";
 282                         };
 283                         PIO101: gpio@fd6b1000 {
 284                                 gpio-controller;
 285                                 #gpio-cells     = <1>;
 286                                 reg             = <0x1000 0x100>;
 287                                 st,bank-name    = "PIO101";
 288                         };
 289                         PIO102: gpio@fd6b2000 {
 290                                 gpio-controller;
 291                                 #gpio-cells     = <1>;
 292                                 reg             = <0x2000 0x100>;
 293                                 st,bank-name    = "PIO102";
 294                         };
 295                 };
 296
 297                 pin-controller-fvdp-lite {
 298                         #address-cells  = <1>;
 299                         #size-cells     = <1>;
 300                         compatible      = "st,stih416-fvdp-lite-pinctrl";
 301                         st,syscfg               = <&syscfg_fvdp_lite>;
 302                         ranges                  = <0 0xfd330000 0x5000>;
 303
 304                         PIO103: gpio@fd330000 {
 305                                 gpio-controller;
 306                                 #gpio-cells     = <1>;
 307                                 reg             = <0 0x100>;
 308                                 st,bank-name    = "PIO103";
 309                         };
 310                         PIO104: gpio@fd331000 {
 311                                 gpio-controller;
 312                                 #gpio-cells     = <1>;
 313                                 reg             = <0x1000 0x100>;
 314                                 st,bank-name    = "PIO104";
 315                         };
 316                         PIO105: gpio@fd332000 {
 317                                 gpio-controller;
 318                                 #gpio-cells     = <1>;
 319                                 reg             = <0x2000 0x100>;
 320                                 st,bank-name    = "PIO105";
 321                         };
 322                         PIO106: gpio@fd333000 {
 323                                 gpio-controller;
 324                                 #gpio-cells     = <1>;
 325                                 reg             = <0x3000 0x100>;
 326                                 st,bank-name    = "PIO106";
 327                         };
 328
 329                         PIO107: gpio@fd334000 {
 330                                 gpio-controller;
 331                                 #gpio-cells     = <1>;
 332                                 reg             = <0x4000 0x100>;
 333                                 st,bank-name    = "PIO107";
 334                                 st,retime-pin-mask = <0xf>;
 335                         };
 336                 };
 337         };
 338 };