arch/arm/boot/dts/stih416-pinctrl.dtsi

   1
   2 /*
   3  * Copyright (C) 2013 STMicroelectronics Limited.
   4  * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * publishhed by the Free Software Foundation.
   9  */
  10 #include "st-pincfg.h"
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12 / {
  13
  14         aliases {
  15                 gpio0   = &PIO0;
  16                 gpio1   = &PIO1;
  17                 gpio2   = &PIO2;
  18                 gpio3   = &PIO3;
  19                 gpio4   = &PIO4;
  20                 gpio5   = &PIO40;
  21                 gpio6   = &PIO5;
  22                 gpio7   = &PIO6;
  23                 gpio8   = &PIO7;
  24                 gpio9   = &PIO8;
  25                 gpio10  = &PIO9;
  26                 gpio11  = &PIO10;
  27                 gpio12  = &PIO11;
  28                 gpio13  = &PIO12;
  29                 gpio14  = &PIO30;
  30                 gpio15  = &PIO31;
  31                 gpio16  = &PIO13;
  32                 gpio17  = &PIO14;
  33                 gpio18  = &PIO15;
  34                 gpio19  = &PIO16;
  35                 gpio20  = &PIO17;
  36                 gpio21  = &PIO18;
  37                 gpio22  = &PIO100;
  38                 gpio23  = &PIO101;
  39                 gpio24  = &PIO102;
  40                 gpio25  = &PIO103;
  41                 gpio26  = &PIO104;
  42                 gpio27  = &PIO105;
  43                 gpio28  = &PIO106;
  44                 gpio29  = &PIO107;
  45         };
  46
  47         soc {
  48                 pin-controller-sbc {
  49                         #address-cells  = <1>;
  50                         #size-cells     = <1>;
  51                         compatible      = "st,stih416-sbc-pinctrl";
  52                         st,syscfg       = <&syscfg_sbc>;
  53                         reg             = <0xfe61f080 0x4>;
  54                         reg-names       = "irqmux";
  55                         interrupts      = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
  56                         interrupts-names = "irqmux";
  57                         ranges          = <0 0xfe610000 0x6000>;
  58
  59                         PIO0: gpio@fe610000 {
  60                                 gpio-controller;
  61                                 #gpio-cells = <1>;
  62                                 interrupt-controller;
  63                                 #interrupt-cells = <2>;
  64                                 reg             = <0 0x100>;
  65                                 st,bank-name    = "PIO0";
  66                         };
  67                         PIO1: gpio@fe611000 {
  68                                 gpio-controller;
  69                                 #gpio-cells     = <1>;
  70                                 interrupt-controller;
  71                                 #interrupt-cells = <2>;
  72                                 reg             = <0x1000 0x100>;
  73                                 st,bank-name    = "PIO1";
  74                         };
  75                         PIO2: gpio@fe612000 {
  76                                 gpio-controller;
  77                                 #gpio-cells     = <1>;
  78                                 interrupt-controller;
  79                                 #interrupt-cells = <2>;
  80                                 reg             = <0x2000 0x100>;
  81                                 st,bank-name    = "PIO2";
  82                         };
  83                         PIO3: gpio@fe613000 {
  84                                 gpio-controller;
  85                                 #gpio-cells     = <1>;
  86                                 interrupt-controller;
  87                                 #interrupt-cells = <2>;
  88                                 reg             = <0x3000 0x100>;
  89                                 st,bank-name    = "PIO3";
  90                         };
  91                         PIO4: gpio@fe614000 {
  92                                 gpio-controller;
  93                                 #gpio-cells     = <1>;
  94                                 interrupt-controller;
  95                                 #interrupt-cells = <2>;
  96                                 reg             = <0x4000 0x100>;
  97                                 st,bank-name    = "PIO4";
  98                         };
  99                         PIO40: gpio@fe615000 {
 100                                 gpio-controller;
 101                                 #gpio-cells     = <1>;
 102                                 interrupt-controller;
 103                                 #interrupt-cells = <2>;
 104                                 reg             = <0x5000 0x100>;
 105                                 st,bank-name    = "PIO40";
 106                                 st,retime-pin-mask = <0x7f>;
 107                         };
 108
 109                         rc{
 110                                 pinctrl_ir: ir0 {
 111                                         st,pins {
 112                                                 ir = <&PIO4 0 ALT2 IN>;
 113                                         };
 114                                 };
 115                         };
 116                         sbc_serial1 {
 117                                 pinctrl_sbc_serial1: sbc_serial1 {
 118                                         st,pins {
 119                                                 tx      = <&PIO2 6 ALT3 OUT>;
 120                                                 rx      = <&PIO2 7 ALT3 IN>;
 121                                         };
 122                                 };
 123                         };
 124
 125                         sbc_i2c0 {
 126                                 pinctrl_sbc_i2c0_default: sbc_i2c0-default {
 127                                         st,pins {
 128                                                 sda = <&PIO4 6 ALT1 BIDIR>;
 129                                                 scl = <&PIO4 5 ALT1 BIDIR>;
 130                                         };
 131                                 };
 132                         };
 133
 134                         sbc_i2c1 {
 135                                 pinctrl_sbc_i2c1_default: sbc_i2c1-default {
 136                                         st,pins {
 137                                                 sda = <&PIO3 2 ALT2 BIDIR>;
 138                                                 scl = <&PIO3 1 ALT2 BIDIR>;
 139                                         };
 140                                 };
 141                         };
 142
 143                         gmac1 {
 144                                 pinctrl_mii1: mii1 {
 145                                         st,pins {
 146                                                 txd0 = <&PIO0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
 147                                                 txd1 = <&PIO0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
 148                                                 txd2 = <&PIO0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
 149                                                 txd3 = <&PIO0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
 150                                                 txer = <&PIO0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
 151                                                 txen = <&PIO0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
 152                                                 txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>;
 153                                                 col =   <&PIO0 7 ALT1 IN BYPASS 1000>;
 154
 155                                                 mdio =  <&PIO1 0 ALT1 OUT BYPASS 1500>;
 156                                                 mdc =   <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>;
 157                                                 crs =   <&PIO1 2 ALT1 IN BYPASS 1000>;
 158                                                 mdint = <&PIO1 3 ALT1 IN BYPASS 0>;
 159                                                 rxd0 =  <&PIO1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 160                                                 rxd1 =  <&PIO1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 161                                                 rxd2 =  <&PIO1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 162                                                 rxd3 =  <&PIO1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 163
 164                                                 rxdv =  <&PIO2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 165                                                 rx_er = <&PIO2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 166                                                 rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>;
 167                                                 phyclk = <&PIO2 3 ALT1 OUT NICLK 0 CLK_A>;
 168                                         };
 169                                 };
 170                                 pinctrl_rgmii1: rgmii1-0 {
 171                                         st,pins {
 172                                                 txd0 =  <&PIO0 0 ALT1 OUT DE_IO 500 CLK_A>;
 173                                                 txd1 =  <&PIO0 1 ALT1 OUT DE_IO 500 CLK_A>;
 174                                                 txd2 =  <&PIO0 2 ALT1 OUT DE_IO 500 CLK_A>;
 175                                                 txd3 =  <&PIO0 3 ALT1 OUT DE_IO 500 CLK_A>;
 176                                                 txen =  <&PIO0 5 ALT1 OUT DE_IO 0   CLK_A>;
 177                                                 txclk = <&PIO0 6 ALT1 IN  NICLK 0   CLK_A>;
 178
 179                                                 mdio = <&PIO1 0 ALT1 OUT BYPASS 0>;
 180                                                 mdc  = <&PIO1 1 ALT1 OUT NICLK  0 CLK_A>;
 181                                                 rxd0 = <&PIO1 4 ALT1 IN DE_IO 500 CLK_A>;
 182                                                 rxd1 = <&PIO1 5 ALT1 IN DE_IO 500 CLK_A>;
 183                                                 rxd2 = <&PIO1 6 ALT1 IN DE_IO 500 CLK_A>;
 184                                                 rxd3 = <&PIO1 7 ALT1 IN DE_IO 500 CLK_A>;
 185
 186                                                 rxdv   = <&PIO2 0 ALT1 IN  DE_IO 500 CLK_A>;
 187                                                 rxclk  = <&PIO2 2 ALT1 IN  NICLK 0   CLK_A>;
 188                                                 phyclk = <&PIO2 3 ALT4 OUT NICLK 0   CLK_B>;
 189
 190                                                 clk125= <&PIO3 7 ALT4 IN NICLK 0 CLK_A>;
 191                                         };
 192                                 };
 193                         };
 194                 };
 195
 196                 pin-controller-front {
 197                         #address-cells  = <1>;
 198                         #size-cells     = <1>;
 199                         compatible      = "st,stih416-front-pinctrl";
 200                         st,syscfg       = <&syscfg_front>;
 201                         reg             = <0xfee0f080 0x4>;
 202                         reg-names       = "irqmux";
 203                         interrupts      = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
 204                         interrupts-names = "irqmux";
 205                         ranges          = <0 0xfee00000 0x10000>;
 206
 207                         PIO5: gpio@fee00000 {
 208                                 gpio-controller;
 209                                 #gpio-cells     = <1>;
 210                                 interrupt-controller;
 211                                 #interrupt-cells = <2>;
 212                                 reg             = <0 0x100>;
 213                                 st,bank-name    = "PIO5";
 214                         };
 215                         PIO6: gpio@fee01000 {
 216                                 gpio-controller;
 217                                 #gpio-cells     = <1>;
 218                                 interrupt-controller;
 219                                 #interrupt-cells = <2>;
 220                                 reg             = <0x1000 0x100>;
 221                                 st,bank-name    = "PIO6";
 222                         };
 223                         PIO7: gpio@fee02000 {
 224                                 gpio-controller;
 225                                 #gpio-cells     = <1>;
 226                                 interrupt-controller;
 227                                 #interrupt-cells = <2>;
 228                                 reg             = <0x2000 0x100>;
 229                                 st,bank-name    = "PIO7";
 230                         };
 231                         PIO8: gpio@fee03000 {
 232                                 gpio-controller;
 233                                 #gpio-cells     = <1>;
 234                                 interrupt-controller;
 235                                 #interrupt-cells = <2>;
 236                                 reg             = <0x3000 0x100>;
 237                                 st,bank-name    = "PIO8";
 238                         };
 239                         PIO9: gpio@fee04000 {
 240                                 gpio-controller;
 241                                 #gpio-cells     = <1>;
 242                                 interrupt-controller;
 243                                 #interrupt-cells = <2>;
 244                                 reg             = <0x4000 0x100>;
 245                                 st,bank-name    = "PIO9";
 246                         };
 247                         PIO10: gpio@fee05000 {
 248                                 gpio-controller;
 249                                 #gpio-cells     = <1>;
 250                                 interrupt-controller;
 251                                 #interrupt-cells = <2>;
 252                                 reg             = <0x5000 0x100>;
 253                                 st,bank-name    = "PIO10";
 254                         };
 255                         PIO11: gpio@fee06000 {
 256                                 gpio-controller;
 257                                 #gpio-cells     = <1>;
 258                                 interrupt-controller;
 259                                 #interrupt-cells = <2>;
 260                                 reg             = <0x6000 0x100>;
 261                                 st,bank-name    = "PIO11";
 262                         };
 263                         PIO12: gpio@fee07000 {
 264                                 gpio-controller;
 265                                 #gpio-cells     = <1>;
 266                                 interrupt-controller;
 267                                 #interrupt-cells = <2>;
 268                                 reg             = <0x7000 0x100>;
 269                                 st,bank-name    = "PIO12";
 270                         };
 271                         PIO30: gpio@fee08000 {
 272                                 gpio-controller;
 273                                 #gpio-cells     = <1>;
 274                                 interrupt-controller;
 275                                 #interrupt-cells = <2>;
 276                                 reg             = <0x8000 0x100>;
 277                                 st,bank-name    = "PIO30";
 278                         };
 279                         PIO31: gpio@fee09000 {
 280                                 gpio-controller;
 281                                 #gpio-cells     = <1>;
 282                                 interrupt-controller;
 283                                 #interrupt-cells = <2>;
 284                                 reg             = <0x9000 0x100>;
 285                                 st,bank-name    = "PIO31";
 286                         };
 287
 288                         serial2-oe {
 289                                 pinctrl_serial2_oe: serial2-1 {
 290                                         st,pins {
 291                                                 output-enable   = <&PIO11 3 ALT2 OUT>;
 292                                         };
 293                                 };
 294                         };
 295
 296                         i2c0 {
 297                                 pinctrl_i2c0_default: i2c0-default {
 298                                         st,pins {
 299                                                 sda = <&PIO9 3 ALT1 BIDIR>;
 300                                                 scl = <&PIO9 2 ALT1 BIDIR>;
 301                                         };
 302                                 };
 303                         };
 304
 305                         i2c1 {
 306                                 pinctrl_i2c1_default: i2c1-default {
 307                                         st,pins {
 308                                                 sda = <&PIO12 1 ALT1 BIDIR>;
 309                                                 scl = <&PIO12 0 ALT1 BIDIR>;
 310                                         };
 311                                 };
 312                         };
 313                 };
 314
 315                 pin-controller-rear {
 316                         #address-cells  = <1>;
 317                         #size-cells     = <1>;
 318                         compatible      = "st,stih416-rear-pinctrl";
 319                         st,syscfg       = <&syscfg_rear>;
 320                         reg             = <0xfe82f080 0x4>;
 321                         reg-names       = "irqmux";
 322                         interrupts      = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 323                         interrupts-names = "irqmux";
 324                         ranges          = <0 0xfe820000 0x6000>;
 325
 326                         PIO13: gpio@fe820000 {
 327                                 gpio-controller;
 328                                 #gpio-cells     = <1>;
 329                                 interrupt-controller;
 330                                 #interrupt-cells = <2>;
 331                                 reg             = <0 0x100>;
 332                                 st,bank-name    = "PIO13";
 333                         };
 334                         PIO14: gpio@fe821000 {
 335                                 gpio-controller;
 336                                 #gpio-cells     = <1>;
 337                                 interrupt-controller;
 338                                 #interrupt-cells = <2>;
 339                                 reg             = <0x1000 0x100>;
 340                                 st,bank-name    = "PIO14";
 341                         };
 342                         PIO15: gpio@fe822000 {
 343                                 gpio-controller;
 344                                 #gpio-cells     = <1>;
 345                                 interrupt-controller;
 346                                 #interrupt-cells = <2>;
 347                                 reg             = <0x2000 0x100>;
 348                                 st,bank-name    = "PIO15";
 349                         };
 350                         PIO16: gpio@fe823000 {
 351                                 gpio-controller;
 352                                 #gpio-cells     = <1>;
 353                                 interrupt-controller;
 354                                 #interrupt-cells = <2>;
 355                                 reg             = <0x3000 0x100>;
 356                                 st,bank-name    = "PIO16";
 357                         };
 358                         PIO17: gpio@fe824000 {
 359                                 gpio-controller;
 360                                 #gpio-cells     = <1>;
 361                                 interrupt-controller;
 362                                 #interrupt-cells = <2>;
 363                                 reg             = <0x4000 0x100>;
 364                                 st,bank-name    = "PIO17";
 365                         };
 366                         PIO18: gpio@fe825000 {
 367                                 gpio-controller;
 368                                 #gpio-cells     = <1>;
 369                                 interrupt-controller;
 370                                 #interrupt-cells = <2>;
 371                                 reg             = <0x5000 0x100>;
 372                                 st,bank-name    = "PIO18";
 373                                 st,retime-pin-mask = <0xf>;
 374                         };
 375
 376                         serial2 {
 377                                 pinctrl_serial2: serial2-0 {
 378                                         st,pins {
 379                                                 tx      = <&PIO17 4 ALT2 OUT>;
 380                                                 rx      = <&PIO17 5 ALT2 IN>;
 381                                         };
 382                                 };
 383                         };
 384
 385                         gmac0 {
 386                                 pinctrl_mii0: mii0 {
 387                                         st,pins {
 388                                                 mdint = <&PIO13 6 ALT2 IN  BYPASS      0>;
 389                                                 txen =  <&PIO13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
 390                                                 txd0 =  <&PIO14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
 391                                                 txd1 =  <&PIO14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
 392                                                 txd2 =  <&PIO14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
 393                                                 txd3 =  <&PIO14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
 394
 395                                                 txclk = <&PIO15 0 ALT2 IN  NICLK       0 CLK_A>;
 396                                                 txer =  <&PIO15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
 397                                                 crs = <&PIO15 2 ALT2 IN  BYPASS 1000>;
 398                                                 col = <&PIO15 3 ALT2 IN  BYPASS 1000>;
 399                                                 mdio= <&PIO15 4 ALT2 OUT BYPASS 1500>;
 400                                                 mdc = <&PIO15 5 ALT2 OUT NICLK  0    CLK_B>;
 401
 402                                                 rxd0 =  <&PIO16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
 403                                                 rxd1 =  <&PIO16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>;
 404                                                 rxd2 =  <&PIO16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
 405                                                 rxd3 =  <&PIO16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>;
 406                                                 rxdv =  <&PIO15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>;
 407                                                 rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>;
 408                                                 rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>;
 409                                                 phyclk = <&PIO13 5 ALT2 OUT NICLK 0 CLK_B>;
 410                                         };
 411                                 };
 412
 413                                 pinctrl_gmii0: gmii0 {
 414                                         st,pins {
 415                                                 };
 416                                 };
 417                                 pinctrl_rgmii0: rgmii0 {
 418                                         st,pins {
 419                                                  phyclk = <&PIO13  5 ALT4 OUT NICLK 0 CLK_B>;
 420                                                  txen = <&PIO13 7 ALT2 OUT DE_IO 0 CLK_A>;
 421                                                  txd0  = <&PIO14 0 ALT2 OUT DE_IO 500 CLK_A>;
 422                                                  txd1  = <&PIO14 1 ALT2 OUT DE_IO 500 CLK_A>;
 423                                                  txd2  = <&PIO14 2 ALT2 OUT DE_IO 500 CLK_B>;
 424                                                  txd3  = <&PIO14 3 ALT2 OUT DE_IO 500 CLK_B>;
 425                                                  txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>;
 426
 427                                                  mdio = <&PIO15 4 ALT2 OUT BYPASS 0>;
 428                                                  mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>;
 429
 430                                                  rxdv = <&PIO15 6 ALT2 IN DE_IO 500 CLK_A>;
 431                                                  rxd0 =<&PIO16 0 ALT2 IN DE_IO  500 CLK_A>;
 432                                                  rxd1 =<&PIO16 1 ALT2 IN DE_IO  500 CLK_A>;
 433                                                  rxd2 =<&PIO16 2 ALT2 IN DE_IO  500 CLK_A>;
 434                                                  rxd3  =<&PIO16 3 ALT2 IN DE_IO 500 CLK_A>;
 435                                                  rxclk =<&PIO17 0 ALT2 IN NICLK 0 CLK_A>;
 436
 437                                                  clk125=<&PIO17 6 ALT1 IN NICLK 0 CLK_A>;
 438                                         };
 439                                 };
 440                         };
 441                 };
 442
 443                 pin-controller-fvdp-fe {
 444                         #address-cells  = <1>;
 445                         #size-cells     = <1>;
 446                         compatible      = "st,stih416-fvdp-fe-pinctrl";
 447                         st,syscfg       = <&syscfg_fvdp_fe>;
 448                         reg             = <0xfd6bf080 0x4>;
 449                         reg-names       = "irqmux";
 450                         interrupts      = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 451                         interrupts-names = "irqmux";
 452                         ranges          = <0 0xfd6b0000 0x3000>;
 453
 454                         PIO100: gpio@fd6b0000 {
 455                                 gpio-controller;
 456                                 #gpio-cells     = <1>;
 457                                 interrupt-controller;
 458                                 #interrupt-cells = <2>;
 459                                 reg             = <0 0x100>;
 460                                 st,bank-name    = "PIO100";
 461                         };
 462                         PIO101: gpio@fd6b1000 {
 463                                 gpio-controller;
 464                                 #gpio-cells     = <1>;
 465                                 interrupt-controller;
 466                                 #interrupt-cells = <2>;
 467                                 reg             = <0x1000 0x100>;
 468                                 st,bank-name    = "PIO101";
 469                         };
 470                         PIO102: gpio@fd6b2000 {
 471                                 gpio-controller;
 472                                 #gpio-cells     = <1>;
 473                                 interrupt-controller;
 474                                 #interrupt-cells = <2>;
 475                                 reg             = <0x2000 0x100>;
 476                                 st,bank-name    = "PIO102";
 477                         };
 478                 };
 479
 480                 pin-controller-fvdp-lite {
 481                         #address-cells  = <1>;
 482                         #size-cells     = <1>;
 483                         compatible      = "st,stih416-fvdp-lite-pinctrl";
 484                         st,syscfg               = <&syscfg_fvdp_lite>;
 485                         reg             = <0xfd33f080 0x4>;
 486                         reg-names       = "irqmux";
 487                         interrupts      = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 488                         interrupts-names = "irqmux";
 489                         ranges                  = <0 0xfd330000 0x5000>;
 490
 491                         PIO103: gpio@fd330000 {
 492                                 gpio-controller;
 493                                 #gpio-cells     = <1>;
 494                                 interrupt-controller;
 495                                 #interrupt-cells = <2>;
 496                                 reg             = <0 0x100>;
 497                                 st,bank-name    = "PIO103";
 498                         };
 499                         PIO104: gpio@fd331000 {
 500                                 gpio-controller;
 501                                 #gpio-cells     = <1>;
 502                                 interrupt-controller;
 503                                 #interrupt-cells = <2>;
 504                                 reg             = <0x1000 0x100>;
 505                                 st,bank-name    = "PIO104";
 506                         };
 507                         PIO105: gpio@fd332000 {
 508                                 gpio-controller;
 509                                 #gpio-cells     = <1>;
 510                                 interrupt-controller;
 511                                 #interrupt-cells = <2>;
 512                                 reg             = <0x2000 0x100>;
 513                                 st,bank-name    = "PIO105";
 514                         };
 515                         PIO106: gpio@fd333000 {
 516                                 gpio-controller;
 517                                 #gpio-cells     = <1>;
 518                                 interrupt-controller;
 519                                 #interrupt-cells = <2>;
 520                                 reg             = <0x3000 0x100>;
 521                                 st,bank-name    = "PIO106";
 522                         };
 523
 524                         PIO107: gpio@fd334000 {
 525                                 gpio-controller;
 526                                 #gpio-cells     = <1>;
 527                                 interrupt-controller;
 528                                 #interrupt-cells = <2>;
 529                                 reg             = <0x4000 0x100>;
 530                                 st,bank-name    = "PIO107";
 531                                 st,retime-pin-mask = <0xf>;
 532                         };
 533                 };
 534         };
 535 };