arch/arm/boot/dts/qcom-msm8974.dtsi

   1 /dts-v1/;
   2
   3 #include "skeleton.dtsi"
   4
   5 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
   6
   7 / {
   8         model = "Qualcomm MSM8974";
   9         compatible = "qcom,msm8974";
  10         interrupt-parent = <&intc>;
  11
  12         soc: soc {
  13                 #address-cells = <1>;
  14                 #size-cells = <1>;
  15                 ranges;
  16                 compatible = "simple-bus";
  17
  18                 intc: interrupt-controller@f9000000 {
  19                         compatible = "qcom,msm-qgic2";
  20                         interrupt-controller;
  21                         #interrupt-cells = <3>;
  22                         reg = <0xf9000000 0x1000>,
  23                               <0xf9002000 0x1000>;
  24                 };
  25
  26                 timer {
  27                         compatible = "arm,armv7-timer";
  28                         interrupts = <1 2 0xf08>,
  29                                      <1 3 0xf08>,
  30                                      <1 4 0xf08>,
  31                                      <1 1 0xf08>;
  32                         clock-frequency = <19200000>;
  33                 };
  34
  35                 timer@f9020000 {
  36                         #address-cells = <1>;
  37                         #size-cells = <1>;
  38                         ranges;
  39                         compatible = "arm,armv7-timer-mem";
  40                         reg = <0xf9020000 0x1000>;
  41                         clock-frequency = <19200000>;
  42
  43                         frame@f9021000 {
  44                                 frame-number = <0>;
  45                                 interrupts = <0 8 0x4>,
  46                                              <0 7 0x4>;
  47                                 reg = <0xf9021000 0x1000>,
  48                                       <0xf9022000 0x1000>;
  49                         };
  50
  51                         frame@f9023000 {
  52                                 frame-number = <1>;
  53                                 interrupts = <0 9 0x4>;
  54                                 reg = <0xf9023000 0x1000>;
  55                                 status = "disabled";
  56                         };
  57
  58                         frame@f9024000 {
  59                                 frame-number = <2>;
  60                                 interrupts = <0 10 0x4>;
  61                                 reg = <0xf9024000 0x1000>;
  62                                 status = "disabled";
  63                         };
  64
  65                         frame@f9025000 {
  66                                 frame-number = <3>;
  67                                 interrupts = <0 11 0x4>;
  68                                 reg = <0xf9025000 0x1000>;
  69                                 status = "disabled";
  70                         };
  71
  72                         frame@f9026000 {
  73                                 frame-number = <4>;
  74                                 interrupts = <0 12 0x4>;
  75                                 reg = <0xf9026000 0x1000>;
  76                                 status = "disabled";
  77                         };
  78
  79                         frame@f9027000 {
  80                                 frame-number = <5>;
  81                                 interrupts = <0 13 0x4>;
  82                                 reg = <0xf9027000 0x1000>;
  83                                 status = "disabled";
  84                         };
  85
  86                         frame@f9028000 {
  87                                 frame-number = <6>;
  88                                 interrupts = <0 14 0x4>;
  89                                 reg = <0xf9028000 0x1000>;
  90                                 status = "disabled";
  91                         };
  92                 };
  93
  94                 restart@fc4ab000 {
  95                         compatible = "qcom,pshold";
  96                         reg = <0xfc4ab000 0x4>;
  97                 };
  98
  99                 gcc: clock-controller@fc400000 {
 100                         compatible = "qcom,gcc-msm8974";
 101                         #clock-cells = <1>;
 102                         #reset-cells = <1>;
 103                         reg = <0xfc400000 0x4000>;
 104                 };
 105
 106                 mmcc: clock-controller@fd8c0000 {
 107                         compatible = "qcom,mmcc-msm8974";
 108                         #clock-cells = <1>;
 109                         #reset-cells = <1>;
 110                         reg = <0xfd8c0000 0x6000>;
 111                 };
 112
 113                 serial@f991e000 {
 114                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 115                         reg = <0xf991e000 0x1000>;
 116                         interrupts = <0 108 0x0>;
 117                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 118                         clock-names = "core", "iface";
 119                 };
 120         };
 121 };