arch/arm/boot/dts/keystone-clocks.dtsi

   1 /*
   2  * Device Tree Source for Keystone 2 clock tree
   3  *
   4  * Copyright (C) 2013 Texas Instruments, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 clocks {
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14         ranges;
  15
  16         mainpllclk: mainpllclk@2310110 {
  17                 #clock-cells = <0>;
  18                 compatible = "ti,keystone,main-pll-clock";
  19                 clocks = <&refclksys>;
  20                 reg = <0x02620350 4>, <0x02310110 4>;
  21                 reg-names = "control", "multiplier";
  22                 fixed-postdiv = <2>;
  23         };
  24
  25         papllclk: papllclk@2620358 {
  26                 #clock-cells = <0>;
  27                 compatible = "ti,keystone,pll-clock";
  28                 clocks = <&refclkpass>;
  29                 clock-output-names = "pa-pll-clk";
  30                 reg = <0x02620358 4>;
  31                 reg-names = "control";
  32         };
  33
  34         ddr3apllclk: ddr3apllclk@2620360 {
  35                 #clock-cells = <0>;
  36                 compatible = "ti,keystone,pll-clock";
  37                 clocks = <&refclkddr3a>;
  38                 clock-output-names = "ddr-3a-pll-clk";
  39                 reg = <0x02620360 4>;
  40                 reg-names = "control";
  41         };
  42
  43         ddr3bpllclk: ddr3bpllclk@2620368 {
  44                 #clock-cells = <0>;
  45                 compatible = "ti,keystone,pll-clock";
  46                 clocks = <&refclkddr3b>;
  47                 clock-output-names = "ddr-3b-pll-clk";
  48                 reg = <0x02620368 4>;
  49                 reg-names = "control";
  50         };
  51
  52         armpllclk: armpllclk@2620370 {
  53                 #clock-cells = <0>;
  54                 compatible = "ti,keystone,pll-clock";
  55                 clocks = <&refclkarm>;
  56                 clock-output-names = "arm-pll-clk";
  57                 reg = <0x02620370 4>;
  58                 reg-names = "control";
  59         };
  60
  61         mainmuxclk: mainmuxclk@2310108 {
  62                 #clock-cells = <0>;
  63                 compatible = "ti,keystone,pll-mux-clock";
  64                 clocks = <&mainpllclk>, <&refclksys>;
  65                 reg = <0x02310108 4>;
  66                 bit-shift = <23>;
  67                 bit-mask = <1>;
  68                 clock-output-names = "mainmuxclk";
  69         };
  70
  71         chipclk1: chipclk1 {
  72                 #clock-cells = <0>;
  73                 compatible = "fixed-factor-clock";
  74                 clocks = <&mainmuxclk>;
  75                 clock-div = <1>;
  76                 clock-mult = <1>;
  77                 clock-output-names = "chipclk1";
  78         };
  79
  80         chipclk1rstiso: chipclk1rstiso {
  81                 #clock-cells = <0>;
  82                 compatible = "fixed-factor-clock";
  83                 clocks = <&mainmuxclk>;
  84                 clock-div = <1>;
  85                 clock-mult = <1>;
  86                 clock-output-names = "chipclk1rstiso";
  87         };
  88
  89         gemtraceclk: gemtraceclk@2310120 {
  90                 #clock-cells = <0>;
  91                 compatible = "ti,keystone,pll-divider-clock";
  92                 clocks = <&mainmuxclk>;
  93                 reg = <0x02310120 4>;
  94                 bit-shift = <0>;
  95                 bit-mask = <8>;
  96                 clock-output-names = "gemtraceclk";
  97         };
  98
  99         chipstmxptclk: chipstmxptclk {
 100                 #clock-cells = <0>;
 101                 compatible = "ti,keystone,pll-divider-clock";
 102                 clocks = <&mainmuxclk>;
 103                 reg = <0x02310164 4>;
 104                 bit-shift = <0>;
 105                 bit-mask = <8>;
 106                 clock-output-names = "chipstmxptclk";
 107         };
 108
 109         chipclk12: chipclk12 {
 110                 #clock-cells = <0>;
 111                 compatible = "fixed-factor-clock";
 112                 clocks = <&chipclk1>;
 113                 clock-div = <2>;
 114                 clock-mult = <1>;
 115                 clock-output-names = "chipclk12";
 116         };
 117
 118         chipclk13: chipclk13 {
 119                 #clock-cells = <0>;
 120                 compatible = "fixed-factor-clock";
 121                 clocks = <&chipclk1>;
 122                 clock-div = <3>;
 123                 clock-mult = <1>;
 124                 clock-output-names = "chipclk13";
 125         };
 126
 127         paclk13: paclk13 {
 128                 #clock-cells = <0>;
 129                 compatible = "fixed-factor-clock";
 130                 clocks = <&papllclk>;
 131                 clock-div = <3>;
 132                 clock-mult = <1>;
 133                 clock-output-names = "paclk13";
 134         };
 135
 136         chipclk14: chipclk14 {
 137                 #clock-cells = <0>;
 138                 compatible = "fixed-factor-clock";
 139                 clocks = <&chipclk1>;
 140                 clock-div = <4>;
 141                 clock-mult = <1>;
 142                 clock-output-names = "chipclk14";
 143         };
 144
 145         chipclk16: chipclk16 {
 146                 #clock-cells = <0>;
 147                 compatible = "fixed-factor-clock";
 148                 clocks = <&chipclk1>;
 149                 clock-div = <6>;
 150                 clock-mult = <1>;
 151                 clock-output-names = "chipclk16";
 152         };
 153
 154         chipclk112: chipclk112 {
 155                 #clock-cells = <0>;
 156                 compatible = "fixed-factor-clock";
 157                 clocks = <&chipclk1>;
 158                 clock-div = <12>;
 159                 clock-mult = <1>;
 160                 clock-output-names = "chipclk112";
 161         };
 162
 163         chipclk124: chipclk124 {
 164                 #clock-cells = <0>;
 165                 compatible = "fixed-factor-clock";
 166                 clocks = <&chipclk1>;
 167                 clock-div = <24>;
 168                 clock-mult = <1>;
 169                 clock-output-names = "chipclk114";
 170         };
 171
 172         chipclk1rstiso13: chipclk1rstiso13 {
 173                 #clock-cells = <0>;
 174                 compatible = "fixed-factor-clock";
 175                 clocks = <&chipclk1rstiso>;
 176                 clock-div = <3>;
 177                 clock-mult = <1>;
 178                 clock-output-names = "chipclk1rstiso13";
 179         };
 180
 181         chipclk1rstiso14: chipclk1rstiso14 {
 182                 #clock-cells = <0>;
 183                 compatible = "fixed-factor-clock";
 184                 clocks = <&chipclk1rstiso>;
 185                 clock-div = <4>;
 186                 clock-mult = <1>;
 187                 clock-output-names = "chipclk1rstiso14";
 188         };
 189
 190         chipclk1rstiso16: chipclk1rstiso16 {
 191                 #clock-cells = <0>;
 192                 compatible = "fixed-factor-clock";
 193                 clocks = <&chipclk1rstiso>;
 194                 clock-div = <6>;
 195                 clock-mult = <1>;
 196                 clock-output-names = "chipclk1rstiso16";
 197         };
 198
 199         chipclk1rstiso112: chipclk1rstiso112 {
 200                 #clock-cells = <0>;
 201                 compatible = "fixed-factor-clock";
 202                 clocks = <&chipclk1rstiso>;
 203                 clock-div = <12>;
 204                 clock-mult = <1>;
 205                 clock-output-names = "chipclk1rstiso112";
 206         };
 207
 208         clkmodrst0: clkmodrst0 {
 209                 #clock-cells = <0>;
 210                 compatible = "ti,keystone,psc-clock";
 211                 clocks = <&chipclk16>;
 212                 clock-output-names = "modrst0";
 213                 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
 214                 reg-names = "control", "domain";
 215                 domain-id = <0>;
 216         };
 217
 218
 219         clkusb: clkusb {
 220                 #clock-cells = <0>;
 221                 compatible = "ti,keystone,psc-clock";
 222                 clocks = <&chipclk16>;
 223                 clock-output-names = "usb";
 224                 reg = <0x02350008 0xb00>, <0x02350000 0x400>;
 225                 reg-names = "control", "domain";
 226                 domain-id = <0>;
 227         };
 228
 229         clkaemifspi: clkaemifspi {
 230                 #clock-cells = <0>;
 231                 compatible = "ti,keystone,psc-clock";
 232                 clocks = <&chipclk16>;
 233                 clock-output-names = "aemif-spi";
 234                 reg = <0x0235000c 0xb00>, <0x02350000 0x400>;
 235                 reg-names = "control", "domain";
 236                 domain-id = <0>;
 237         };
 238
 239
 240         clkdebugsstrc: clkdebugsstrc {
 241                 #clock-cells = <0>;
 242                 compatible = "ti,keystone,psc-clock";
 243                 clocks = <&chipclk13>;
 244                 clock-output-names = "debugss-trc";
 245                 reg = <0x02350014 0xb00>, <0x02350000 0x400>;
 246                 reg-names = "control", "domain";
 247                 domain-id = <0>;
 248         };
 249
 250         clktetbtrc: clktetbtrc {
 251                 #clock-cells = <0>;
 252                 compatible = "ti,keystone,psc-clock";
 253                 clocks = <&chipclk13>;
 254                 clock-output-names = "tetb-trc";
 255                 reg = <0x02350018 0xb00>, <0x02350004 0x400>;
 256                 reg-names = "control", "domain";
 257                 domain-id = <1>;
 258         };
 259
 260         clkpa: clkpa {
 261                 #clock-cells = <0>;
 262                 compatible = "ti,keystone,psc-clock";
 263                 clocks = <&chipclk16>;
 264                 clock-output-names = "pa";
 265                 reg = <0x0235001c 0xb00>, <0x02350008 0x400>;
 266                 reg-names = "control", "domain";
 267                 domain-id = <2>;
 268         };
 269
 270         clkcpgmac: clkcpgmac {
 271                 #clock-cells = <0>;
 272                 compatible = "ti,keystone,psc-clock";
 273                 clocks = <&clkpa>;
 274                 clock-output-names = "cpgmac";
 275                 reg = <0x02350020 0xb00>, <0x02350008 0x400>;
 276                 reg-names = "control", "domain";
 277                 domain-id = <2>;
 278         };
 279
 280         clksa: clksa {
 281                 #clock-cells = <0>;
 282                 compatible = "ti,keystone,psc-clock";
 283                 clocks = <&clkpa>;
 284                 clock-output-names = "sa";
 285                 reg = <0x02350024 0xb00>, <0x02350008 0x400>;
 286                 reg-names = "control", "domain";
 287                 domain-id = <2>;
 288         };
 289
 290         clkpcie: clkpcie {
 291                 #clock-cells = <0>;
 292                 compatible = "ti,keystone,psc-clock";
 293                 clocks = <&chipclk12>;
 294                 clock-output-names = "pcie";
 295                 reg = <0x02350028 0xb00>, <0x0235000c 0x400>;
 296                 reg-names = "control", "domain";
 297                 domain-id = <3>;
 298         };
 299
 300         clksrio: clksrio {
 301                 #clock-cells = <0>;
 302                 compatible = "ti,keystone,psc-clock";
 303                 clocks = <&chipclk1rstiso13>;
 304                 clock-output-names = "srio";
 305                 reg = <0x0235002c 0xb00>, <0x02350010 0x400>;
 306                 reg-names = "control", "domain";
 307                 domain-id = <4>;
 308         };
 309
 310         clkhyperlink0: clkhyperlink0 {
 311                 #clock-cells = <0>;
 312                 compatible = "ti,keystone,psc-clock";
 313                 clocks = <&chipclk12>;
 314                 clock-output-names = "hyperlink-0";
 315                 reg = <0x02350030 0xb00>, <0x02350014 0x400>;
 316                 reg-names = "control", "domain";
 317                 domain-id = <5>;
 318         };
 319
 320         clksr: clksr {
 321                 #clock-cells = <0>;
 322                 compatible = "ti,keystone,psc-clock";
 323                 clocks = <&chipclk1rstiso112>;
 324                 clock-output-names = "sr";
 325                 reg = <0x02350034 0xb00>, <0x02350018 0x400>;
 326                 reg-names = "control", "domain";
 327                 domain-id = <6>;
 328         };
 329
 330         clkmsmcsram: clkmsmcsram {
 331                 #clock-cells = <0>;
 332                 compatible = "ti,keystone,psc-clock";
 333                 clocks = <&chipclk1>;
 334                 clock-output-names = "msmcsram";
 335                 reg = <0x02350038 0xb00>, <0x0235001c 0x400>;
 336                 reg-names = "control", "domain";
 337                 domain-id = <7>;
 338         };
 339
 340         clkgem0: clkgem0 {
 341                 #clock-cells = <0>;
 342                 compatible = "ti,keystone,psc-clock";
 343                 clocks = <&chipclk1>;
 344                 clock-output-names = "gem0";
 345                 reg = <0x0235003c 0xb00>, <0x02350020 0x400>;
 346                 reg-names = "control", "domain";
 347                 domain-id = <8>;
 348         };
 349
 350         clkgem1: clkgem1 {
 351                 #clock-cells = <0>;
 352                 compatible = "ti,keystone,psc-clock";
 353                 clocks = <&chipclk1>;
 354                 clock-output-names = "gem1";
 355                 reg = <0x02350040 0xb00>, <0x02350024 0x400>;
 356                 reg-names = "control", "domain";
 357                 domain-id = <9>;
 358         };
 359
 360         clkgem2: clkgem2 {
 361                 #clock-cells = <0>;
 362                 compatible = "ti,keystone,psc-clock";
 363                 clocks = <&chipclk1>;
 364                 clock-output-names = "gem2";
 365                 reg = <0x02350044 0xb00>, <0x02350028 0x400>;
 366                 reg-names = "control", "domain";
 367                 domain-id = <10>;
 368         };
 369
 370         clkgem3: clkgem3 {
 371                 #clock-cells = <0>;
 372                 compatible = "ti,keystone,psc-clock";
 373                 clocks = <&chipclk1>;
 374                 clock-output-names = "gem3";
 375                 reg = <0x02350048 0xb00>, <0x0235002c 0x400>;
 376                 reg-names = "control", "domain";
 377                 domain-id = <11>;
 378         };
 379
 380         clkgem4: clkgem4 {
 381                 #clock-cells = <0>;
 382                 compatible = "ti,keystone,psc-clock";
 383                 clocks = <&chipclk1>;
 384                 clock-output-names = "gem4";
 385                 reg = <0x0235004c 0xb00>, <0x02350030 0x400>;
 386                 reg-names = "control", "domain";
 387                 domain-id = <12>;
 388         };
 389
 390         clkgem5: clkgem5 {
 391                 #clock-cells = <0>;
 392                 compatible = "ti,keystone,psc-clock";
 393                 clocks = <&chipclk1>;
 394                 clock-output-names = "gem5";
 395                 reg = <0x02350050 0xb00>, <0x02350034 0x400>;
 396                 reg-names = "control", "domain";
 397                 domain-id = <13>;
 398         };
 399
 400         clkgem6: clkgem6 {
 401                 #clock-cells = <0>;
 402                 compatible = "ti,keystone,psc-clock";
 403                 clocks = <&chipclk1>;
 404                 clock-output-names = "gem6";
 405                 reg = <0x02350054 0xb00>, <0x02350038 0x400>;
 406                 reg-names = "control", "domain";
 407                 domain-id = <14>;
 408         };
 409
 410         clkgem7: clkgem7 {
 411                 #clock-cells = <0>;
 412                 compatible = "ti,keystone,psc-clock";
 413                 clocks = <&chipclk1>;
 414                 clock-output-names = "gem7";
 415                 reg = <0x02350058 0xb00>, <0x0235003c 0x400>;
 416                 reg-names = "control", "domain";
 417                 domain-id = <15>;
 418         };
 419
 420         clkddr30: clkddr30 {
 421                 #clock-cells = <0>;
 422                 compatible = "ti,keystone,psc-clock";
 423                 clocks = <&chipclk12>;
 424                 clock-output-names = "ddr3-0";
 425                 reg = <0x0235005c 0xb00>, <0x02350040 0x400>;
 426                 reg-names = "control", "domain";
 427                 domain-id = <16>;
 428         };
 429
 430         clkddr31: clkddr31 {
 431                 #clock-cells = <0>;
 432                 compatible = "ti,keystone,psc-clock";
 433                 clocks = <&chipclk13>;
 434                 clock-output-names = "ddr3-1";
 435                 reg = <0x02350060 0xb00>, <0x02350040 0x400>;
 436                 reg-names = "control", "domain";
 437                 domain-id = <16>;
 438         };
 439
 440         clktac: clktac {
 441                 #clock-cells = <0>;
 442                 compatible = "ti,keystone,psc-clock";
 443                 clocks = <&chipclk13>;
 444                 clock-output-names = "tac";
 445                 reg = <0x02350064 0xb00>, <0x02350044 0x400>;
 446                 reg-names = "control", "domain";
 447                 domain-id = <17>;
 448         };
 449
 450         clkrac01: clktac01 {
 451                 #clock-cells = <0>;
 452                 compatible = "ti,keystone,psc-clock";
 453                 clocks = <&chipclk13>;
 454                 clock-output-names = "rac-01";
 455                 reg = <0x02350068 0xb00>, <0x02350044 0x400>;
 456                 reg-names = "control", "domain";
 457                 domain-id = <17>;
 458         };
 459
 460         clkrac23: clktac23 {
 461                 #clock-cells = <0>;
 462                 compatible = "ti,keystone,psc-clock";
 463                 clocks = <&chipclk13>;
 464                 clock-output-names = "rac-23";
 465                 reg = <0x0235006c 0xb00>, <0x02350048 0x400>;
 466                 reg-names = "control", "domain";
 467                 domain-id = <18>;
 468         };
 469
 470         clkfftc0: clkfftc0 {
 471                 #clock-cells = <0>;
 472                 compatible = "ti,keystone,psc-clock";
 473                 clocks = <&chipclk13>;
 474                 clock-output-names = "fftc-0";
 475                 reg = <0x02350070 0xb00>, <0x0235004c 0x400>;
 476                 reg-names = "control", "domain";
 477                 domain-id = <19>;
 478         };
 479
 480         clkfftc1: clkfftc1 {
 481                 #clock-cells = <0>;
 482                 compatible = "ti,keystone,psc-clock";
 483                 clocks = <&chipclk13>;
 484                 clock-output-names = "fftc-1";
 485                 reg = <0x02350074 0xb00>, <0x023504c0 0x400>;
 486                 reg-names = "control", "domain";
 487                 domain-id = <19>;
 488         };
 489
 490         clkfftc2: clkfftc2 {
 491                 #clock-cells = <0>;
 492                 compatible = "ti,keystone,psc-clock";
 493                 clocks = <&chipclk13>;
 494                 clock-output-names = "fftc-2";
 495                 reg = <0x02350078 0xb00>, <0x02350050 0x400>;
 496                 reg-names = "control", "domain";
 497                 domain-id = <20>;
 498         };
 499
 500         clkfftc3: clkfftc3 {
 501                 #clock-cells = <0>;
 502                 compatible = "ti,keystone,psc-clock";
 503                 clocks = <&chipclk13>;
 504                 clock-output-names = "fftc-3";
 505                 reg = <0x0235007c 0xb00>, <0x02350050 0x400>;
 506                 reg-names = "control", "domain";
 507                 domain-id = <20>;
 508         };
 509
 510         clkfftc4: clkfftc4 {
 511                 #clock-cells = <0>;
 512                 compatible = "ti,keystone,psc-clock";
 513                 clocks = <&chipclk13>;
 514                 clock-output-names = "fftc-4";
 515                 reg = <0x02350080 0xb00>, <0x02350050 0x400>;
 516                 reg-names = "control", "domain";
 517                 domain-id = <20>;
 518         };
 519
 520         clkfftc5: clkfftc5 {
 521                 #clock-cells = <0>;
 522                 compatible = "ti,keystone,psc-clock";
 523                 clocks = <&chipclk13>;
 524                 clock-output-names = "fftc-5";
 525                 reg = <0x02350084 0xb00>, <0x02350050 0x400>;
 526                 reg-names = "control", "domain";
 527                 domain-id = <20>;
 528         };
 529
 530         clkaif: clkaif {
 531                 #clock-cells = <0>;
 532                 compatible = "ti,keystone,psc-clock";
 533                 clocks = <&chipclk13>;
 534                 clock-output-names = "aif";
 535                 reg = <0x02350088 0xb00>, <0x02350054 0x400>;
 536                 reg-names = "control", "domain";
 537                 domain-id = <21>;
 538         };
 539
 540         clktcp3d0: clktcp3d0 {
 541                 #clock-cells = <0>;
 542                 compatible = "ti,keystone,psc-clock";
 543                 clocks = <&chipclk13>;
 544                 clock-output-names = "tcp3d-0";
 545                 reg = <0x0235008c 0xb00>, <0x02350058 0x400>;
 546                 reg-names = "control", "domain";
 547                 domain-id = <22>;
 548         };
 549
 550         clktcp3d1: clktcp3d1 {
 551                 #clock-cells = <0>;
 552                 compatible = "ti,keystone,psc-clock";
 553                 clocks = <&chipclk13>;
 554                 clock-output-names = "tcp3d-1";
 555                 reg = <0x02350090 0xb00>, <0x02350058 0x400>;
 556                 reg-names = "control", "domain";
 557                 domain-id = <22>;
 558         };
 559
 560         clktcp3d2: clktcp3d2 {
 561                 #clock-cells = <0>;
 562                 compatible = "ti,keystone,psc-clock";
 563                 clocks = <&chipclk13>;
 564                 clock-output-names = "tcp3d-2";
 565                 reg = <0x02350094 0xb00>, <0x0235005c 0x400>;
 566                 reg-names = "control", "domain";
 567                 domain-id = <23>;
 568         };
 569
 570         clktcp3d3: clktcp3d3 {
 571                 #clock-cells = <0>;
 572                 compatible = "ti,keystone,psc-clock";
 573                 clocks = <&chipclk13>;
 574                 clock-output-names = "tcp3d-3";
 575                 reg = <0x02350098 0xb00>, <0x0235005c 0x400>;
 576                 reg-names = "control", "domain";
 577                 domain-id = <23>;
 578         };
 579
 580         clkvcp0: clkvcp0 {
 581                 #clock-cells = <0>;
 582                 compatible = "ti,keystone,psc-clock";
 583                 clocks = <&chipclk13>;
 584                 clock-output-names = "vcp-0";
 585                 reg = <0x0235009c 0xb00>, <0x02350060 0x400>;
 586                 reg-names = "control", "domain";
 587                 domain-id = <24>;
 588         };
 589
 590         clkvcp1: clkvcp1 {
 591                 #clock-cells = <0>;
 592                 compatible = "ti,keystone,psc-clock";
 593                 clocks = <&chipclk13>;
 594                 clock-output-names = "vcp-1";
 595                 reg = <0x023500a0 0xb00>, <0x02350060 0x400>;
 596                 reg-names = "control", "domain";
 597                 domain-id = <24>;
 598         };
 599
 600         clkvcp2: clkvcp2 {
 601                 #clock-cells = <0>;
 602                 compatible = "ti,keystone,psc-clock";
 603                 clocks = <&chipclk13>;
 604                 clock-output-names = "vcp-2";
 605                 reg = <0x023500a4 0xb00>, <0x02350060 0x400>;
 606                 reg-names = "control", "domain";
 607                 domain-id = <24>;
 608         };
 609
 610         clkvcp3: clkvcp3 {
 611                 #clock-cells = <0>;
 612                 compatible = "ti,keystone,psc-clock";
 613                 clocks = <&chipclk13>;
 614                 clock-output-names = "vcp-3";
 615                 reg = <0x023500a8 0xb00>, <0x02350060 0x400>;
 616                 reg-names = "control", "domain";
 617                 domain-id = <24>;
 618         };
 619
 620         clkvcp4: clkvcp4 {
 621                 #clock-cells = <0>;
 622                 compatible = "ti,keystone,psc-clock";
 623                 clocks = <&chipclk13>;
 624                 clock-output-names = "vcp-4";
 625                 reg = <0x023500ac 0xb00>, <0x02350064 0x400>;
 626                 reg-names = "control", "domain";
 627                 domain-id = <25>;
 628         };
 629
 630         clkvcp5: clkvcp5 {
 631                 #clock-cells = <0>;
 632                 compatible = "ti,keystone,psc-clock";
 633                 clocks = <&chipclk13>;
 634                 clock-output-names = "vcp-5";
 635                 reg = <0x023500b0 0xb00>, <0x02350064 0x400>;
 636                 reg-names = "control", "domain";
 637                 domain-id = <25>;
 638         };
 639
 640         clkvcp6: clkvcp6 {
 641                 #clock-cells = <0>;
 642                 compatible = "ti,keystone,psc-clock";
 643                 clocks = <&chipclk13>;
 644                 clock-output-names = "vcp-6";
 645                 reg = <0x023500b4 0xb00>, <0x02350064 0x400>;
 646                 reg-names = "control", "domain";
 647                 domain-id = <25>;
 648         };
 649
 650         clkvcp7: clkvcp7 {
 651                 #clock-cells = <0>;
 652                 compatible = "ti,keystone,psc-clock";
 653                 clocks = <&chipclk13>;
 654                 clock-output-names = "vcp-7";
 655                 reg = <0x023500b8 0xb00>, <0x02350064 0x400>;
 656                 reg-names = "control", "domain";
 657                 domain-id = <25>;
 658         };
 659
 660         clkbcp: clkbcp {
 661                 #clock-cells = <0>;
 662                 compatible = "ti,keystone,psc-clock";
 663                 clocks = <&chipclk13>;
 664                 clock-output-names = "bcp";
 665                 reg = <0x023500bc 0xb00>, <0x02350068 0x400>;
 666                 reg-names = "control", "domain";
 667                 domain-id = <26>;
 668         };
 669
 670         clkdxb: clkdxb {
 671                 #clock-cells = <0>;
 672                 compatible = "ti,keystone,psc-clock";
 673                 clocks = <&chipclk13>;
 674                 clock-output-names = "dxb";
 675                 reg = <0x023500c0 0xb00>, <0x0235006c 0x400>;
 676                 reg-names = "control", "domain";
 677                 domain-id = <27>;
 678         };
 679
 680         clkhyperlink1: clkhyperlink1 {
 681                 #clock-cells = <0>;
 682                 compatible = "ti,keystone,psc-clock";
 683                 clocks = <&chipclk12>;
 684                 clock-output-names = "hyperlink-1";
 685                 reg = <0x023500c4 0xb00>, <0x02350070 0x400>;
 686                 reg-names = "control", "domain";
 687                 domain-id = <28>;
 688         };
 689
 690         clkxge: clkxge {
 691                 #clock-cells = <0>;
 692                 compatible = "ti,keystone,psc-clock";
 693                 clocks = <&chipclk13>;
 694                 clock-output-names = "xge";
 695                 reg = <0x023500c8 0xb00>, <0x02350074 0x400>;
 696                 reg-names = "control", "domain";
 697                 domain-id = <29>;
 698         };
 699
 700         clkwdtimer0: clkwdtimer0 {
 701                 #clock-cells = <0>;
 702                 compatible = "ti,keystone,psc-clock";
 703                 clocks = <&clkmodrst0>;
 704                 clock-output-names = "timer0";
 705                 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
 706                 reg-names = "control", "domain";
 707                 domain-id = <0>;
 708         };
 709
 710         clkwdtimer1: clkwdtimer1 {
 711                 #clock-cells = <0>;
 712                 compatible = "ti,keystone,psc-clock";
 713                 clocks = <&clkmodrst0>;
 714                 clock-output-names = "timer1";
 715                 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
 716                 reg-names = "control", "domain";
 717                 domain-id = <0>;
 718         };
 719
 720         clkwdtimer2: clkwdtimer2 {
 721                 #clock-cells = <0>;
 722                 compatible = "ti,keystone,psc-clock";
 723                 clocks = <&clkmodrst0>;
 724                 clock-output-names = "timer2";
 725                 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
 726                 reg-names = "control", "domain";
 727                 domain-id = <0>;
 728         };
 729
 730         clkwdtimer3: clkwdtimer3 {
 731                 #clock-cells = <0>;
 732                 compatible = "ti,keystone,psc-clock";
 733                 clocks = <&clkmodrst0>;
 734                 clock-output-names = "timer3";
 735                 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
 736                 reg-names = "control", "domain";
 737                 domain-id = <0>;
 738         };
 739
 740         clkuart0: clkuart0 {
 741                 #clock-cells = <0>;
 742                 compatible = "ti,keystone,psc-clock";
 743                 clocks = <&clkmodrst0>;
 744                 clock-output-names = "uart0";
 745                 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
 746                 reg-names = "control", "domain";
 747                 domain-id = <0>;
 748         };
 749
 750         clkuart1: clkuart1 {
 751                 #clock-cells = <0>;
 752                 compatible = "ti,keystone,psc-clock";
 753                 clocks = <&clkmodrst0>;
 754                 clock-output-names = "uart1";
 755                 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
 756                 reg-names = "control", "domain";
 757                 domain-id = <0>;
 758         };
 759
 760         clkaemif: clkaemif {
 761                 #clock-cells = <0>;
 762                 compatible = "ti,keystone,psc-clock";
 763                 clocks = <&clkaemifspi>;
 764                 clock-output-names = "aemif";
 765                 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
 766                 reg-names = "control", "domain";
 767                 domain-id = <0>;
 768         };
 769
 770         clkusim: clkusim {
 771                 #clock-cells = <0>;
 772                 compatible = "ti,keystone,psc-clock";
 773                 clocks = <&clkmodrst0>;
 774                 clock-output-names = "usim";
 775                 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
 776                 reg-names = "control", "domain";
 777                 domain-id = <0>;
 778         };
 779
 780         clki2c: clki2c {
 781                 #clock-cells = <0>;
 782                 compatible = "ti,keystone,psc-clock";
 783                 clocks = <&clkmodrst0>;
 784                 clock-output-names = "i2c";
 785                 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
 786                 reg-names = "control", "domain";
 787                 domain-id = <0>;
 788         };
 789
 790         clkspi: clkspi {
 791                 #clock-cells = <0>;
 792                 compatible = "ti,keystone,psc-clock";
 793                 clocks = <&clkaemifspi>;
 794                 clock-output-names = "spi";
 795                 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
 796                 reg-names = "control", "domain";
 797                 domain-id = <0>;
 798         };
 799
 800         clkgpio: clkgpio {
 801                 #clock-cells = <0>;
 802                 compatible = "ti,keystone,psc-clock";
 803                 clocks = <&clkmodrst0>;
 804                 clock-output-names = "gpio";
 805                 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
 806                 reg-names = "control", "domain";
 807                 domain-id = <0>;
 808         };
 809
 810         clkkeymgr: clkkeymgr {
 811                 #clock-cells = <0>;
 812                 compatible = "ti,keystone,psc-clock";
 813                 clocks = <&clkmodrst0>;
 814                 clock-output-names = "keymgr";
 815                 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
 816                 reg-names = "control", "domain";
 817                 domain-id = <0>;
 818         };
 819 };