arch/arm/boot/dts/imx6qdl-sabreauto.dtsi

   1 /*
   2  * Copyright 2012 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 / {
  14         memory {
  15                 reg = <0x10000000 0x80000000>;
  16         };
  17
  18         sound-spdif {
  19                 compatible = "fsl,imx-audio-spdif",
  20                            "fsl,imx-sabreauto-spdif";
  21                 model = "imx-spdif";
  22                 spdif-controller = <&spdif>;
  23                 spdif-in;
  24         };
  25
  26         backlight {
  27                 compatible = "pwm-backlight";
  28                 pwms = <&pwm3 0 5000000>;
  29                 brightness-levels = <0 4 8 16 32 64 128 255>;
  30                 default-brightness-level = <7>;
  31                 status = "okay";
  32         };
  33 };
  34
  35 &ecspi1 {
  36         fsl,spi-num-chipselects = <1>;
  37         cs-gpios = <&gpio3 19 0>;
  38         pinctrl-names = "default";
  39         pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
  40         status = "disabled"; /* pin conflict with WEIM NOR */
  41
  42         flash: m25p80@0 {
  43                 #address-cells = <1>;
  44                 #size-cells = <1>;
  45                 compatible = "st,m25p32";
  46                 spi-max-frequency = <20000000>;
  47                 reg = <0>;
  48         };
  49 };
  50
  51 &fec {
  52         pinctrl-names = "default";
  53         pinctrl-0 = <&pinctrl_enet>;
  54         phy-mode = "rgmii";
  55         interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
  56                               <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
  57         status = "okay";
  58 };
  59
  60 &gpmi {
  61         pinctrl-names = "default";
  62         pinctrl-0 = <&pinctrl_gpmi_nand>;
  63         status = "okay";
  64 };
  65
  66 &iomuxc {
  67         pinctrl-names = "default";
  68         pinctrl-0 = <&pinctrl_hog>;
  69
  70         imx6qdl-sabreauto {
  71                 pinctrl_hog: hoggrp {
  72                         fsl,pins = <
  73                                 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
  74                                 MX6QDL_PAD_SD2_DAT2__GPIO1_IO13  0x80000000
  75                                 MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059
  76                         >;
  77                 };
  78
  79                 pinctrl_ecspi1: ecspi1grp {
  80                         fsl,pins = <
  81                                 MX6QDL_PAD_EIM_D17__ECSPI1_MISO         0x100b1
  82                                 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI         0x100b1
  83                                 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK         0x100b1
  84                         >;
  85                 };
  86
  87                 pinctrl_ecspi1_cs: ecspi1cs {
  88                         fsl,pins = <
  89                                 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
  90                         >;
  91                 };
  92
  93                 pinctrl_enet: enetgrp {
  94                         fsl,pins = <
  95                                 MX6QDL_PAD_KEY_COL1__ENET_MDIO          0x1b0b0
  96                                 MX6QDL_PAD_KEY_COL2__ENET_MDC           0x1b0b0
  97                                 MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b0b0
  98                                 MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b0b0
  99                                 MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b0b0
 100                                 MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b0b0
 101                                 MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b0b0
 102                                 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
 103                                 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 104                                 MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
 105                                 MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
 106                                 MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
 107                                 MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
 108                                 MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
 109                                 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
 110                                 MX6QDL_PAD_GPIO_6__ENET_IRQ             0x000b1
 111                         >;
 112                 };
 113
 114                 pinctrl_gpmi_nand: gpminandgrp {
 115                         fsl,pins = <
 116                                 MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
 117                                 MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
 118                                 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
 119                                 MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
 120                                 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
 121                                 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B        0xb0b1
 122                                 MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
 123                                 MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
 124                                 MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
 125                                 MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
 126                                 MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
 127                                 MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
 128                                 MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
 129                                 MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
 130                                 MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
 131                                 MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
 132                                 MX6QDL_PAD_SD4_DAT0__NAND_DQS           0x00b1
 133                         >;
 134                 };
 135
 136                 pinctrl_pwm3: pwm1grp {
 137                         fsl,pins = <
 138                                 MX6QDL_PAD_SD4_DAT1__PWM3_OUT           0x1b0b1
 139                         >;
 140                 };
 141
 142                 pinctrl_spdif: spdifgrp {
 143                         fsl,pins = <
 144                                 MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
 145                         >;
 146                 };
 147
 148                 pinctrl_uart4: uart4grp {
 149                         fsl,pins = <
 150                                 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA      0x1b0b1
 151                                 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA      0x1b0b1
 152                         >;
 153                 };
 154
 155                 pinctrl_usdhc3: usdhc3grp {
 156                         fsl,pins = <
 157                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 158                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 159                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 160                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 161                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 162                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 163                                 MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x17059
 164                                 MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x17059
 165                                 MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x17059
 166                                 MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x17059
 167                         >;
 168                 };
 169
 170                 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
 171                         fsl,pins = <
 172                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170b9
 173                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100b9
 174                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170b9
 175                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170b9
 176                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170b9
 177                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170b9
 178                                 MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x170b9
 179                                 MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x170b9
 180                                 MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x170b9
 181                                 MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x170b9
 182                         >;
 183                 };
 184
 185                 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
 186                         fsl,pins = <
 187                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170f9
 188                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100f9
 189                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170f9
 190                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170f9
 191                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170f9
 192                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170f9
 193                                 MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x170f9
 194                                 MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x170f9
 195                                 MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x170f9
 196                                 MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x170f9
 197                         >;
 198                 };
 199
 200                 pinctrl_weim_cs0: weimcs0grp {
 201                         fsl,pins = <
 202                                 MX6QDL_PAD_EIM_CS0__EIM_CS0_B           0xb0b1
 203                         >;
 204                 };
 205
 206                 pinctrl_weim_nor: weimnorgrp {
 207                         fsl,pins = <
 208                                 MX6QDL_PAD_EIM_OE__EIM_OE_B             0xb0b1
 209                                 MX6QDL_PAD_EIM_RW__EIM_RW               0xb0b1
 210                                 MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B         0xb060
 211                                 MX6QDL_PAD_EIM_D16__EIM_DATA16          0x1b0b0
 212                                 MX6QDL_PAD_EIM_D17__EIM_DATA17          0x1b0b0
 213                                 MX6QDL_PAD_EIM_D18__EIM_DATA18          0x1b0b0
 214                                 MX6QDL_PAD_EIM_D19__EIM_DATA19          0x1b0b0
 215                                 MX6QDL_PAD_EIM_D20__EIM_DATA20          0x1b0b0
 216                                 MX6QDL_PAD_EIM_D21__EIM_DATA21          0x1b0b0
 217                                 MX6QDL_PAD_EIM_D22__EIM_DATA22          0x1b0b0
 218                                 MX6QDL_PAD_EIM_D23__EIM_DATA23          0x1b0b0
 219                                 MX6QDL_PAD_EIM_D24__EIM_DATA24          0x1b0b0
 220                                 MX6QDL_PAD_EIM_D25__EIM_DATA25          0x1b0b0
 221                                 MX6QDL_PAD_EIM_D26__EIM_DATA26          0x1b0b0
 222                                 MX6QDL_PAD_EIM_D27__EIM_DATA27          0x1b0b0
 223                                 MX6QDL_PAD_EIM_D28__EIM_DATA28          0x1b0b0
 224                                 MX6QDL_PAD_EIM_D29__EIM_DATA29          0x1b0b0
 225                                 MX6QDL_PAD_EIM_D30__EIM_DATA30          0x1b0b0
 226                                 MX6QDL_PAD_EIM_D31__EIM_DATA31          0x1b0b0
 227                                 MX6QDL_PAD_EIM_A23__EIM_ADDR23          0xb0b1
 228                                 MX6QDL_PAD_EIM_A22__EIM_ADDR22          0xb0b1
 229                                 MX6QDL_PAD_EIM_A21__EIM_ADDR21          0xb0b1
 230                                 MX6QDL_PAD_EIM_A20__EIM_ADDR20          0xb0b1
 231                                 MX6QDL_PAD_EIM_A19__EIM_ADDR19          0xb0b1
 232                                 MX6QDL_PAD_EIM_A18__EIM_ADDR18          0xb0b1
 233                                 MX6QDL_PAD_EIM_A17__EIM_ADDR17          0xb0b1
 234                                 MX6QDL_PAD_EIM_A16__EIM_ADDR16          0xb0b1
 235                                 MX6QDL_PAD_EIM_DA15__EIM_AD15           0xb0b1
 236                                 MX6QDL_PAD_EIM_DA14__EIM_AD14           0xb0b1
 237                                 MX6QDL_PAD_EIM_DA13__EIM_AD13           0xb0b1
 238                                 MX6QDL_PAD_EIM_DA12__EIM_AD12           0xb0b1
 239                                 MX6QDL_PAD_EIM_DA11__EIM_AD11           0xb0b1
 240                                 MX6QDL_PAD_EIM_DA10__EIM_AD10           0xb0b1
 241                                 MX6QDL_PAD_EIM_DA9__EIM_AD09            0xb0b1
 242                                 MX6QDL_PAD_EIM_DA8__EIM_AD08            0xb0b1
 243                                 MX6QDL_PAD_EIM_DA7__EIM_AD07            0xb0b1
 244                                 MX6QDL_PAD_EIM_DA6__EIM_AD06            0xb0b1
 245                                 MX6QDL_PAD_EIM_DA5__EIM_AD05            0xb0b1
 246                                 MX6QDL_PAD_EIM_DA4__EIM_AD04            0xb0b1
 247                                 MX6QDL_PAD_EIM_DA3__EIM_AD03            0xb0b1
 248                                 MX6QDL_PAD_EIM_DA2__EIM_AD02            0xb0b1
 249                                 MX6QDL_PAD_EIM_DA1__EIM_AD01            0xb0b1
 250                                 MX6QDL_PAD_EIM_DA0__EIM_AD00            0xb0b1
 251                         >;
 252                 };
 253         };
 254 };
 255
 256 &ldb {
 257         status = "okay";
 258
 259         lvds-channel@0 {
 260                 fsl,data-mapping = "spwg";
 261                 fsl,data-width = <18>;
 262                 status = "okay";
 263
 264                 display-timings {
 265                         native-mode = <&timing0>;
 266                         timing0: hsd100pxn1 {
 267                                 clock-frequency = <65000000>;
 268                                 hactive = <1024>;
 269                                 vactive = <768>;
 270                                 hback-porch = <220>;
 271                                 hfront-porch = <40>;
 272                                 vback-porch = <21>;
 273                                 vfront-porch = <7>;
 274                                 hsync-len = <60>;
 275                                 vsync-len = <10>;
 276                         };
 277                 };
 278         };
 279 };
 280
 281 &pwm3 {
 282         pinctrl-names = "default";
 283         pinctrl-0 = <&pinctrl_pwm3>;
 284         status = "okay";
 285 };
 286
 287 &spdif {
 288         pinctrl-names = "default";
 289         pinctrl-0 = <&pinctrl_spdif>;
 290         status = "okay";
 291 };
 292
 293 &uart4 {
 294         pinctrl-names = "default";
 295         pinctrl-0 = <&pinctrl_uart4>;
 296         status = "okay";
 297 };
 298
 299 &usdhc3 {
 300         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 301         pinctrl-0 = <&pinctrl_usdhc3>;
 302         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 303         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 304         cd-gpios = <&gpio6 15 0>;
 305         wp-gpios = <&gpio1 13 0>;
 306         status = "okay";
 307 };
 308
 309 &weim {
 310         pinctrl-names = "default";
 311         pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>;
 312         #address-cells = <2>;
 313         #size-cells = <1>;
 314         ranges = <0 0 0x08000000 0x08000000>;
 315         status = "disabled"; /* pin conflict with SPI NOR */
 316
 317         nor@0,0 {
 318                 compatible = "cfi-flash";
 319                 reg = <0 0 0x02000000>;
 320                 #address-cells = <1>;
 321                 #size-cells = <1>;
 322                 bank-width = <2>;
 323                 fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
 324                                 0x0000c000 0x1404a38e 0x00000000>;
 325         };
 326 };