Merge branch 'async-scsi-resume' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux.git] / arch / arm / boot / dts / imx51-eukrea-cpuimx51.dtsi
1 /*
2  * Copyright 2013 EukrĂ©a Electromatique <denis@eukrea.com>
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License
6  * as published by the Free Software Foundation; either version 2
7  * of the License, or (at your option) any later version.
8  * This program is distributed in the hope that it will be useful,
9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11  * GNU General Public License for more details.
12  *
13  * You should have received a copy of the GNU General Public License
14  * along with this program; if not, write to the Free Software
15  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
16  * MA 02110-1301, USA.
17  */
18
19 #include "imx51.dtsi"
20
21 / {
22         model = "Eukrea CPUIMX51";
23         compatible = "eukrea,cpuimx51", "fsl,imx51";
24
25         memory {
26                 reg = <0x90000000 0x10000000>; /* 256M */
27         };
28 };
29
30 &fec {
31         pinctrl-names = "default";
32         pinctrl-0 = <&pinctrl_fec>;
33         status = "okay";
34 };
35
36 &i2c1 {
37         pinctrl-names = "default";
38         pinctrl-0 = <&pinctrl_i2c1>;
39         status = "okay";
40
41         pcf8563@51 {
42                 compatible = "nxp,pcf8563";
43                 reg = <0x51>;
44         };
45 };
46
47 &iomuxc {
48         imx51-eukrea {
49                 pinctrl_tsc2007_1: tsc2007grp-1 {
50                         fsl,pins = <
51                                 MX51_PAD_GPIO_NAND__GPIO_NAND 0x1f5
52                                 MX51_PAD_NANDF_D8__GPIO4_0 0x1f5
53                         >;
54                 };
55
56                 pinctrl_fec: fecgrp {
57                         fsl,pins = <
58                                 MX51_PAD_DI_GP3__FEC_TX_ER              0x80000000
59                                 MX51_PAD_DI2_PIN4__FEC_CRS              0x80000000
60                                 MX51_PAD_DI2_PIN2__FEC_MDC              0x80000000
61                                 MX51_PAD_DI2_PIN3__FEC_MDIO             0x80000000
62                                 MX51_PAD_DI2_DISP_CLK__FEC_RDATA1       0x80000000
63                                 MX51_PAD_DI_GP4__FEC_RDATA2             0x80000000
64                                 MX51_PAD_DISP2_DAT0__FEC_RDATA3         0x80000000
65                                 MX51_PAD_DISP2_DAT1__FEC_RX_ER          0x80000000
66                                 MX51_PAD_DISP2_DAT6__FEC_TDATA1         0x80000000
67                                 MX51_PAD_DISP2_DAT7__FEC_TDATA2         0x80000000
68                                 MX51_PAD_DISP2_DAT8__FEC_TDATA3         0x80000000
69                                 MX51_PAD_DISP2_DAT9__FEC_TX_EN          0x80000000
70                                 MX51_PAD_DISP2_DAT10__FEC_COL           0x80000000
71                                 MX51_PAD_DISP2_DAT11__FEC_RX_CLK        0x80000000
72                                 MX51_PAD_DISP2_DAT12__FEC_RX_DV         0x80000000
73                                 MX51_PAD_DISP2_DAT13__FEC_TX_CLK        0x80000000
74                                 MX51_PAD_DISP2_DAT14__FEC_RDATA0        0x80000000
75                                 MX51_PAD_DISP2_DAT15__FEC_TDATA0        0x80000000
76                         >;
77                 };
78
79                 pinctrl_i2c1: i2c1grp {
80                         fsl,pins = <
81                                 MX51_PAD_SD2_CMD__I2C1_SCL              0x400001ed
82                                 MX51_PAD_SD2_CLK__I2C1_SDA              0x400001ed
83                         >;
84                 };
85         };
86 };
87
88 &nfc {
89         nand-bus-width = <8>;
90         nand-ecc-mode = "hw";
91         nand-on-flash-bbt;
92         status = "okay";
93 };