arch/arm/boot/dts/exynos5250.dtsi

   1 /*
   2  * SAMSUNG EXYNOS5250 SoC device tree source
   3  *
   4  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
   8  * EXYNOS5250 based board files can include this file and provide
   9  * values for board specfic bindings.
  10  *
  11  * Note: This file does not include device nodes for all the controllers in
  12  * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
  13  * additional nodes can be added to this file.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18 */
  19
  20 #include <dt-bindings/clock/exynos5250.h>
  21 #include "exynos5.dtsi"
  22 #include "exynos5250-pinctrl.dtsi"
  23
  24 #include <dt-bindings/clock/exynos-audss-clk.h>
  25
  26 / {
  27         compatible = "samsung,exynos5250", "samsung,exynos5";
  28
  29         aliases {
  30                 spi0 = &spi_0;
  31                 spi1 = &spi_1;
  32                 spi2 = &spi_2;
  33                 gsc0 = &gsc_0;
  34                 gsc1 = &gsc_1;
  35                 gsc2 = &gsc_2;
  36                 gsc3 = &gsc_3;
  37                 mshc0 = &mmc_0;
  38                 mshc1 = &mmc_1;
  39                 mshc2 = &mmc_2;
  40                 mshc3 = &mmc_3;
  41                 i2c0 = &i2c_0;
  42                 i2c1 = &i2c_1;
  43                 i2c2 = &i2c_2;
  44                 i2c3 = &i2c_3;
  45                 i2c4 = &i2c_4;
  46                 i2c5 = &i2c_5;
  47                 i2c6 = &i2c_6;
  48                 i2c7 = &i2c_7;
  49                 i2c8 = &i2c_8;
  50                 i2c9 = &i2c_9;
  51                 pinctrl0 = &pinctrl_0;
  52                 pinctrl1 = &pinctrl_1;
  53                 pinctrl2 = &pinctrl_2;
  54                 pinctrl3 = &pinctrl_3;
  55         };
  56
  57         cpus {
  58                 #address-cells = <1>;
  59                 #size-cells = <0>;
  60
  61                 cpu@0 {
  62                         device_type = "cpu";
  63                         compatible = "arm,cortex-a15";
  64                         reg = <0>;
  65                         clock-frequency = <1700000000>;
  66                 };
  67                 cpu@1 {
  68                         device_type = "cpu";
  69                         compatible = "arm,cortex-a15";
  70                         reg = <1>;
  71                         clock-frequency = <1700000000>;
  72                 };
  73         };
  74
  75         pd_gsc: gsc-power-domain@10044000 {
  76                 compatible = "samsung,exynos4210-pd";
  77                 reg = <0x10044000 0x20>;
  78         };
  79
  80         pd_mfc: mfc-power-domain@10044040 {
  81                 compatible = "samsung,exynos4210-pd";
  82                 reg = <0x10044040 0x20>;
  83         };
  84
  85         clock: clock-controller@10010000 {
  86                 compatible = "samsung,exynos5250-clock";
  87                 reg = <0x10010000 0x30000>;
  88                 #clock-cells = <1>;
  89         };
  90
  91         clock_audss: audss-clock-controller@3810000 {
  92                 compatible = "samsung,exynos5250-audss-clock";
  93                 reg = <0x03810000 0x0C>;
  94                 #clock-cells = <1>;
  95                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
  96                          <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>;
  97                 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
  98         };
  99
 100         timer {
 101                 compatible = "arm,armv7-timer";
 102                 interrupts = <1 13 0xf08>,
 103                              <1 14 0xf08>,
 104                              <1 11 0xf08>,
 105                              <1 10 0xf08>;
 106                 /* Unfortunately we need this since some versions of U-Boot
 107                  * on Exynos don't set the CNTFRQ register, so we need the
 108                  * value from DT.
 109                  */
 110                 clock-frequency = <24000000>;
 111         };
 112
 113         mct@101C0000 {
 114                 compatible = "samsung,exynos4210-mct";
 115                 reg = <0x101C0000 0x800>;
 116                 interrupt-controller;
 117                 #interrups-cells = <2>;
 118                 interrupt-parent = <&mct_map>;
 119                 interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
 120                              <4 0>, <5 0>;
 121                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
 122                 clock-names = "fin_pll", "mct";
 123
 124                 mct_map: mct-map {
 125                         #interrupt-cells = <2>;
 126                         #address-cells = <0>;
 127                         #size-cells = <0>;
 128                         interrupt-map = <0x0 0 &combiner 23 3>,
 129                                         <0x1 0 &combiner 23 4>,
 130                                         <0x2 0 &combiner 25 2>,
 131                                         <0x3 0 &combiner 25 3>,
 132                                         <0x4 0 &gic 0 120 0>,
 133                                         <0x5 0 &gic 0 121 0>;
 134                 };
 135         };
 136
 137         pmu {
 138                 compatible = "arm,cortex-a15-pmu";
 139                 interrupt-parent = <&combiner>;
 140                 interrupts = <1 2>, <22 4>;
 141         };
 142
 143         pinctrl_0: pinctrl@11400000 {
 144                 compatible = "samsung,exynos5250-pinctrl";
 145                 reg = <0x11400000 0x1000>;
 146                 interrupts = <0 46 0>;
 147
 148                 wakup_eint: wakeup-interrupt-controller {
 149                         compatible = "samsung,exynos4210-wakeup-eint";
 150                         interrupt-parent = <&gic>;
 151                         interrupts = <0 32 0>;
 152                 };
 153         };
 154
 155         pinctrl_1: pinctrl@13400000 {
 156                 compatible = "samsung,exynos5250-pinctrl";
 157                 reg = <0x13400000 0x1000>;
 158                 interrupts = <0 45 0>;
 159         };
 160
 161         pinctrl_2: pinctrl@10d10000 {
 162                 compatible = "samsung,exynos5250-pinctrl";
 163                 reg = <0x10d10000 0x1000>;
 164                 interrupts = <0 50 0>;
 165         };
 166
 167         pinctrl_3: pinctrl@03860000 {
 168                 compatible = "samsung,exynos5250-pinctrl";
 169                 reg = <0x03860000 0x1000>;
 170                 interrupts = <0 47 0>;
 171         };
 172
 173         pmu_system_controller: system-controller@10040000 {
 174                 compatible = "samsung,exynos5250-pmu", "syscon";
 175                 reg = <0x10040000 0x5000>;
 176         };
 177
 178         watchdog@101D0000 {
 179                 compatible = "samsung,exynos5250-wdt";
 180                 reg = <0x101D0000 0x100>;
 181                 interrupts = <0 42 0>;
 182                 clocks = <&clock CLK_WDT>;
 183                 clock-names = "watchdog";
 184                 samsung,syscon-phandle = <&pmu_system_controller>;
 185         };
 186
 187         g2d@10850000 {
 188                 compatible = "samsung,exynos5250-g2d";
 189                 reg = <0x10850000 0x1000>;
 190                 interrupts = <0 91 0>;
 191                 clocks = <&clock CLK_G2D>;
 192                 clock-names = "fimg2d";
 193         };
 194
 195         codec@11000000 {
 196                 compatible = "samsung,mfc-v6";
 197                 reg = <0x11000000 0x10000>;
 198                 interrupts = <0 96 0>;
 199                 samsung,power-domain = <&pd_mfc>;
 200                 clocks = <&clock CLK_MFC>;
 201                 clock-names = "mfc";
 202         };
 203
 204         rtc@101E0000 {
 205                 clocks = <&clock CLK_RTC>;
 206                 clock-names = "rtc";
 207                 status = "disabled";
 208         };
 209
 210         tmu@10060000 {
 211                 compatible = "samsung,exynos5250-tmu";
 212                 reg = <0x10060000 0x100>;
 213                 interrupts = <0 65 0>;
 214                 clocks = <&clock CLK_TMU>;
 215                 clock-names = "tmu_apbif";
 216         };
 217
 218         serial@12C00000 {
 219                 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
 220                 clock-names = "uart", "clk_uart_baud0";
 221         };
 222
 223         serial@12C10000 {
 224                 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
 225                 clock-names = "uart", "clk_uart_baud0";
 226         };
 227
 228         serial@12C20000 {
 229                 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
 230                 clock-names = "uart", "clk_uart_baud0";
 231         };
 232
 233         serial@12C30000 {
 234                 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
 235                 clock-names = "uart", "clk_uart_baud0";
 236         };
 237
 238         sata@122F0000 {
 239                 compatible = "snps,dwc-ahci";
 240                 samsung,sata-freq = <66>;
 241                 reg = <0x122F0000 0x1ff>;
 242                 interrupts = <0 115 0>;
 243                 clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
 244                 clock-names = "sata", "sclk_sata";
 245                 phys = <&sata_phy>;
 246                 phy-names = "sata-phy";
 247                 status = "disabled";
 248         };
 249
 250         sata_phy: sata-phy@12170000 {
 251                 compatible = "samsung,exynos5250-sata-phy";
 252                 reg = <0x12170000 0x1ff>;
 253                 clocks = <&clock 287>;
 254                 clock-names = "sata_phyctrl";
 255                 #phy-cells = <0>;
 256                 samsung,syscon-phandle = <&pmu_system_controller>;
 257                 status = "disabled";
 258         };
 259
 260         i2c_0: i2c@12C60000 {
 261                 compatible = "samsung,s3c2440-i2c";
 262                 reg = <0x12C60000 0x100>;
 263                 interrupts = <0 56 0>;
 264                 #address-cells = <1>;
 265                 #size-cells = <0>;
 266                 clocks = <&clock CLK_I2C0>;
 267                 clock-names = "i2c";
 268                 pinctrl-names = "default";
 269                 pinctrl-0 = <&i2c0_bus>;
 270                 status = "disabled";
 271         };
 272
 273         i2c_1: i2c@12C70000 {
 274                 compatible = "samsung,s3c2440-i2c";
 275                 reg = <0x12C70000 0x100>;
 276                 interrupts = <0 57 0>;
 277                 #address-cells = <1>;
 278                 #size-cells = <0>;
 279                 clocks = <&clock CLK_I2C1>;
 280                 clock-names = "i2c";
 281                 pinctrl-names = "default";
 282                 pinctrl-0 = <&i2c1_bus>;
 283                 status = "disabled";
 284         };
 285
 286         i2c_2: i2c@12C80000 {
 287                 compatible = "samsung,s3c2440-i2c";
 288                 reg = <0x12C80000 0x100>;
 289                 interrupts = <0 58 0>;
 290                 #address-cells = <1>;
 291                 #size-cells = <0>;
 292                 clocks = <&clock CLK_I2C2>;
 293                 clock-names = "i2c";
 294                 pinctrl-names = "default";
 295                 pinctrl-0 = <&i2c2_bus>;
 296                 status = "disabled";
 297         };
 298
 299         i2c_3: i2c@12C90000 {
 300                 compatible = "samsung,s3c2440-i2c";
 301                 reg = <0x12C90000 0x100>;
 302                 interrupts = <0 59 0>;
 303                 #address-cells = <1>;
 304                 #size-cells = <0>;
 305                 clocks = <&clock CLK_I2C3>;
 306                 clock-names = "i2c";
 307                 pinctrl-names = "default";
 308                 pinctrl-0 = <&i2c3_bus>;
 309                 status = "disabled";
 310         };
 311
 312         i2c_4: i2c@12CA0000 {
 313                 compatible = "samsung,s3c2440-i2c";
 314                 reg = <0x12CA0000 0x100>;
 315                 interrupts = <0 60 0>;
 316                 #address-cells = <1>;
 317                 #size-cells = <0>;
 318                 clocks = <&clock CLK_I2C4>;
 319                 clock-names = "i2c";
 320                 pinctrl-names = "default";
 321                 pinctrl-0 = <&i2c4_bus>;
 322                 status = "disabled";
 323         };
 324
 325         i2c_5: i2c@12CB0000 {
 326                 compatible = "samsung,s3c2440-i2c";
 327                 reg = <0x12CB0000 0x100>;
 328                 interrupts = <0 61 0>;
 329                 #address-cells = <1>;
 330                 #size-cells = <0>;
 331                 clocks = <&clock CLK_I2C5>;
 332                 clock-names = "i2c";
 333                 pinctrl-names = "default";
 334                 pinctrl-0 = <&i2c5_bus>;
 335                 status = "disabled";
 336         };
 337
 338         i2c_6: i2c@12CC0000 {
 339                 compatible = "samsung,s3c2440-i2c";
 340                 reg = <0x12CC0000 0x100>;
 341                 interrupts = <0 62 0>;
 342                 #address-cells = <1>;
 343                 #size-cells = <0>;
 344                 clocks = <&clock CLK_I2C6>;
 345                 clock-names = "i2c";
 346                 pinctrl-names = "default";
 347                 pinctrl-0 = <&i2c6_bus>;
 348                 status = "disabled";
 349         };
 350
 351         i2c_7: i2c@12CD0000 {
 352                 compatible = "samsung,s3c2440-i2c";
 353                 reg = <0x12CD0000 0x100>;
 354                 interrupts = <0 63 0>;
 355                 #address-cells = <1>;
 356                 #size-cells = <0>;
 357                 clocks = <&clock CLK_I2C7>;
 358                 clock-names = "i2c";
 359                 pinctrl-names = "default";
 360                 pinctrl-0 = <&i2c7_bus>;
 361                 status = "disabled";
 362         };
 363
 364         i2c_8: i2c@12CE0000 {
 365                 compatible = "samsung,s3c2440-hdmiphy-i2c";
 366                 reg = <0x12CE0000 0x1000>;
 367                 interrupts = <0 64 0>;
 368                 #address-cells = <1>;
 369                 #size-cells = <0>;
 370                 clocks = <&clock CLK_I2C_HDMI>;
 371                 clock-names = "i2c";
 372                 status = "disabled";
 373         };
 374
 375         i2c_9: i2c@121D0000 {
 376                 compatible = "samsung,exynos5-sata-phy-i2c";
 377                 reg = <0x121D0000 0x100>;
 378                 #address-cells = <1>;
 379                 #size-cells = <0>;
 380                 clocks = <&clock CLK_SATA_PHYI2C>;
 381                 clock-names = "i2c";
 382                 status = "disabled";
 383         };
 384
 385         spi_0: spi@12d20000 {
 386                 compatible = "samsung,exynos4210-spi";
 387                 status = "disabled";
 388                 reg = <0x12d20000 0x100>;
 389                 interrupts = <0 66 0>;
 390                 dmas = <&pdma0 5
 391                         &pdma0 4>;
 392                 dma-names = "tx", "rx";
 393                 #address-cells = <1>;
 394                 #size-cells = <0>;
 395                 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
 396                 clock-names = "spi", "spi_busclk0";
 397                 pinctrl-names = "default";
 398                 pinctrl-0 = <&spi0_bus>;
 399         };
 400
 401         spi_1: spi@12d30000 {
 402                 compatible = "samsung,exynos4210-spi";
 403                 status = "disabled";
 404                 reg = <0x12d30000 0x100>;
 405                 interrupts = <0 67 0>;
 406                 dmas = <&pdma1 5
 407                         &pdma1 4>;
 408                 dma-names = "tx", "rx";
 409                 #address-cells = <1>;
 410                 #size-cells = <0>;
 411                 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
 412                 clock-names = "spi", "spi_busclk0";
 413                 pinctrl-names = "default";
 414                 pinctrl-0 = <&spi1_bus>;
 415         };
 416
 417         spi_2: spi@12d40000 {
 418                 compatible = "samsung,exynos4210-spi";
 419                 status = "disabled";
 420                 reg = <0x12d40000 0x100>;
 421                 interrupts = <0 68 0>;
 422                 dmas = <&pdma0 7
 423                         &pdma0 6>;
 424                 dma-names = "tx", "rx";
 425                 #address-cells = <1>;
 426                 #size-cells = <0>;
 427                 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
 428                 clock-names = "spi", "spi_busclk0";
 429                 pinctrl-names = "default";
 430                 pinctrl-0 = <&spi2_bus>;
 431         };
 432
 433         mmc_0: mmc@12200000 {
 434                 compatible = "samsung,exynos5250-dw-mshc";
 435                 interrupts = <0 75 0>;
 436                 #address-cells = <1>;
 437                 #size-cells = <0>;
 438                 reg = <0x12200000 0x1000>;
 439                 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
 440                 clock-names = "biu", "ciu";
 441                 fifo-depth = <0x80>;
 442                 status = "disabled";
 443         };
 444
 445         mmc_1: mmc@12210000 {
 446                 compatible = "samsung,exynos5250-dw-mshc";
 447                 interrupts = <0 76 0>;
 448                 #address-cells = <1>;
 449                 #size-cells = <0>;
 450                 reg = <0x12210000 0x1000>;
 451                 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
 452                 clock-names = "biu", "ciu";
 453                 fifo-depth = <0x80>;
 454                 status = "disabled";
 455         };
 456
 457         mmc_2: mmc@12220000 {
 458                 compatible = "samsung,exynos5250-dw-mshc";
 459                 interrupts = <0 77 0>;
 460                 #address-cells = <1>;
 461                 #size-cells = <0>;
 462                 reg = <0x12220000 0x1000>;
 463                 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
 464                 clock-names = "biu", "ciu";
 465                 fifo-depth = <0x80>;
 466                 status = "disabled";
 467         };
 468
 469         mmc_3: mmc@12230000 {
 470                 compatible = "samsung,exynos5250-dw-mshc";
 471                 reg = <0x12230000 0x1000>;
 472                 interrupts = <0 78 0>;
 473                 #address-cells = <1>;
 474                 #size-cells = <0>;
 475                 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
 476                 clock-names = "biu", "ciu";
 477                 fifo-depth = <0x80>;
 478                 status = "disabled";
 479         };
 480
 481         i2s0: i2s@03830000 {
 482                 compatible = "samsung,s5pv210-i2s";
 483                 status = "disabled";
 484                 reg = <0x03830000 0x100>;
 485                 dmas = <&pdma0 10
 486                         &pdma0 9
 487                         &pdma0 8>;
 488                 dma-names = "tx", "rx", "tx-sec";
 489                 clocks = <&clock_audss EXYNOS_I2S_BUS>,
 490                         <&clock_audss EXYNOS_I2S_BUS>,
 491                         <&clock_audss EXYNOS_SCLK_I2S>;
 492                 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
 493                 samsung,idma-addr = <0x03000000>;
 494                 pinctrl-names = "default";
 495                 pinctrl-0 = <&i2s0_bus>;
 496         };
 497
 498         i2s1: i2s@12D60000 {
 499                 compatible = "samsung,s3c6410-i2s";
 500                 status = "disabled";
 501                 reg = <0x12D60000 0x100>;
 502                 dmas = <&pdma1 12
 503                         &pdma1 11>;
 504                 dma-names = "tx", "rx";
 505                 clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>;
 506                 clock-names = "iis", "i2s_opclk0";
 507                 pinctrl-names = "default";
 508                 pinctrl-0 = <&i2s1_bus>;
 509         };
 510
 511         i2s2: i2s@12D70000 {
 512                 compatible = "samsung,s3c6410-i2s";
 513                 status = "disabled";
 514                 reg = <0x12D70000 0x100>;
 515                 dmas = <&pdma0 12
 516                         &pdma0 11>;
 517                 dma-names = "tx", "rx";
 518                 clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>;
 519                 clock-names = "iis", "i2s_opclk0";
 520                 pinctrl-names = "default";
 521                 pinctrl-0 = <&i2s2_bus>;
 522         };
 523
 524         usb@12000000 {
 525                 compatible = "samsung,exynos5250-dwusb3";
 526                 clocks = <&clock CLK_USB3>;
 527                 clock-names = "usbdrd30";
 528                 #address-cells = <1>;
 529                 #size-cells = <1>;
 530                 ranges;
 531
 532                 dwc3 {
 533                         compatible = "synopsys,dwc3";
 534                         reg = <0x12000000 0x10000>;
 535                         interrupts = <0 72 0>;
 536                         usb-phy = <&usb2_phy &usb3_phy>;
 537                 };
 538         };
 539
 540         usb3_phy: usbphy@12100000 {
 541                 compatible = "samsung,exynos5250-usb3phy";
 542                 reg = <0x12100000 0x100>;
 543                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_USB3>;
 544                 clock-names = "ext_xtal", "usbdrd30";
 545                 #address-cells = <1>;
 546                 #size-cells = <1>;
 547                 ranges;
 548
 549                 usbphy-sys {
 550                         reg = <0x10040704 0x8>;
 551                 };
 552         };
 553
 554         usb@12110000 {
 555                 compatible = "samsung,exynos4210-ehci";
 556                 reg = <0x12110000 0x100>;
 557                 interrupts = <0 71 0>;
 558
 559                 clocks = <&clock CLK_USB2>;
 560                 clock-names = "usbhost";
 561         };
 562
 563         usb@12120000 {
 564                 compatible = "samsung,exynos4210-ohci";
 565                 reg = <0x12120000 0x100>;
 566                 interrupts = <0 71 0>;
 567
 568                 clocks = <&clock CLK_USB2>;
 569                 clock-names = "usbhost";
 570         };
 571
 572         usb2_phy: usbphy@12130000 {
 573                 compatible = "samsung,exynos5250-usb2phy";
 574                 reg = <0x12130000 0x100>;
 575                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_USB2>;
 576                 clock-names = "ext_xtal", "usbhost";
 577                 #address-cells = <1>;
 578                 #size-cells = <1>;
 579                 ranges;
 580
 581                 usbphy-sys {
 582                         reg = <0x10040704 0x8>,
 583                               <0x10050230 0x4>;
 584                 };
 585         };
 586
 587         pwm: pwm@12dd0000 {
 588                 compatible = "samsung,exynos4210-pwm";
 589                 reg = <0x12dd0000 0x100>;
 590                 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
 591                 #pwm-cells = <3>;
 592                 clocks = <&clock CLK_PWM>;
 593                 clock-names = "timers";
 594         };
 595
 596         amba {
 597                 #address-cells = <1>;
 598                 #size-cells = <1>;
 599                 compatible = "arm,amba-bus";
 600                 interrupt-parent = <&gic>;
 601                 ranges;
 602
 603                 pdma0: pdma@121A0000 {
 604                         compatible = "arm,pl330", "arm,primecell";
 605                         reg = <0x121A0000 0x1000>;
 606                         interrupts = <0 34 0>;
 607                         clocks = <&clock CLK_PDMA0>;
 608                         clock-names = "apb_pclk";
 609                         #dma-cells = <1>;
 610                         #dma-channels = <8>;
 611                         #dma-requests = <32>;
 612                 };
 613
 614                 pdma1: pdma@121B0000 {
 615                         compatible = "arm,pl330", "arm,primecell";
 616                         reg = <0x121B0000 0x1000>;
 617                         interrupts = <0 35 0>;
 618                         clocks = <&clock CLK_PDMA1>;
 619                         clock-names = "apb_pclk";
 620                         #dma-cells = <1>;
 621                         #dma-channels = <8>;
 622                         #dma-requests = <32>;
 623                 };
 624
 625                 mdma0: mdma@10800000 {
 626                         compatible = "arm,pl330", "arm,primecell";
 627                         reg = <0x10800000 0x1000>;
 628                         interrupts = <0 33 0>;
 629                         clocks = <&clock CLK_MDMA0>;
 630                         clock-names = "apb_pclk";
 631                         #dma-cells = <1>;
 632                         #dma-channels = <8>;
 633                         #dma-requests = <1>;
 634                 };
 635
 636                 mdma1: mdma@11C10000 {
 637                         compatible = "arm,pl330", "arm,primecell";
 638                         reg = <0x11C10000 0x1000>;
 639                         interrupts = <0 124 0>;
 640                         clocks = <&clock CLK_MDMA1>;
 641                         clock-names = "apb_pclk";
 642                         #dma-cells = <1>;
 643                         #dma-channels = <8>;
 644                         #dma-requests = <1>;
 645                 };
 646         };
 647
 648         gsc_0:  gsc@13e00000 {
 649                 compatible = "samsung,exynos5-gsc";
 650                 reg = <0x13e00000 0x1000>;
 651                 interrupts = <0 85 0>;
 652                 samsung,power-domain = <&pd_gsc>;
 653                 clocks = <&clock CLK_GSCL0>;
 654                 clock-names = "gscl";
 655         };
 656
 657         gsc_1:  gsc@13e10000 {
 658                 compatible = "samsung,exynos5-gsc";
 659                 reg = <0x13e10000 0x1000>;
 660                 interrupts = <0 86 0>;
 661                 samsung,power-domain = <&pd_gsc>;
 662                 clocks = <&clock CLK_GSCL1>;
 663                 clock-names = "gscl";
 664         };
 665
 666         gsc_2:  gsc@13e20000 {
 667                 compatible = "samsung,exynos5-gsc";
 668                 reg = <0x13e20000 0x1000>;
 669                 interrupts = <0 87 0>;
 670                 samsung,power-domain = <&pd_gsc>;
 671                 clocks = <&clock CLK_GSCL2>;
 672                 clock-names = "gscl";
 673         };
 674
 675         gsc_3:  gsc@13e30000 {
 676                 compatible = "samsung,exynos5-gsc";
 677                 reg = <0x13e30000 0x1000>;
 678                 interrupts = <0 88 0>;
 679                 samsung,power-domain = <&pd_gsc>;
 680                 clocks = <&clock CLK_GSCL3>;
 681                 clock-names = "gscl";
 682         };
 683
 684         hdmi {
 685                 compatible = "samsung,exynos4212-hdmi";
 686                 reg = <0x14530000 0x70000>;
 687                 interrupts = <0 95 0>;
 688                 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
 689                          <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
 690                          <&clock CLK_MOUT_HDMI>;
 691                 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
 692                                 "sclk_hdmiphy", "mout_hdmi";
 693         };
 694
 695         mixer {
 696                 compatible = "samsung,exynos5250-mixer";
 697                 reg = <0x14450000 0x10000>;
 698                 interrupts = <0 94 0>;
 699                 clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>;
 700                 clock-names = "mixer", "sclk_hdmi";
 701         };
 702
 703         dp_phy: video-phy@10040720 {
 704                 compatible = "samsung,exynos5250-dp-video-phy";
 705                 reg = <0x10040720 4>;
 706                 #phy-cells = <0>;
 707         };
 708
 709         dp-controller@145B0000 {
 710                 clocks = <&clock CLK_DP>;
 711                 clock-names = "dp";
 712                 phys = <&dp_phy>;
 713                 phy-names = "dp";
 714         };
 715
 716         fimd@14400000 {
 717                 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
 718                 clock-names = "sclk_fimd", "fimd";
 719         };
 720
 721         adc: adc@12D10000 {
 722                 compatible = "samsung,exynos-adc-v1";
 723                 reg = <0x12D10000 0x100>, <0x10040718 0x4>;
 724                 interrupts = <0 106 0>;
 725                 clocks = <&clock CLK_ADC>;
 726                 clock-names = "adc";
 727                 #io-channel-cells = <1>;
 728                 io-channel-ranges;
 729                 status = "disabled";
 730         };
 731
 732         sss@10830000 {
 733                 compatible = "samsung,exynos4210-secss";
 734                 reg = <0x10830000 0x10000>;
 735                 interrupts = <0 112 0>;
 736                 clocks = <&clock 348>;
 737                 clock-names = "secss";
 738         };
 739 };