Documentation/devicetree/bindings/clock/st/st,clkgen.txt

   1 Binding for a Clockgen hardware block found on
   2 certain STMicroelectronics consumer electronics SoC devices.
   3
   4 A Clockgen node can contain pll, diviser or multiplexer nodes.
   5
   6 We will find only the base address of the Clockgen, this base
   7 address is common of all subnode.
   8
   9         clockgen_node {
  10                 reg = <>;
  11
  12                 pll_node {
  13                         ...
  14                 };
  15
  16                 prediv_node {
  17                         ...
  18                 };
  19
  20                 divmux_node {
  21                         ...
  22                 };
  23
  24                 quadfs_node {
  25                         ...
  26                 };
  27                 ...
  28         };
  29
  30 This binding uses the common clock binding[1].
  31 Each subnode should use the binding discribe in [2]..[4]
  32
  33 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
  34 [2] Documentation/devicetree/bindings/clock/st,quadfs.txt
  35 [3] Documentation/devicetree/bindings/clock/st,quadfs.txt
  36 [4] Documentation/devicetree/bindings/clock/st,quadfs.txt
  37
  38 Required properties:
  39 - reg : A Base address and length of the register set.
  40
  41 Example:
  42
  43         clockgenA@fee62000 {
  44
  45                 reg = <0xfee62000 0xb48>;
  46
  47                 CLK_S_A0_PLL: CLK_S_A0_PLL {
  48                         #clock-cells = <1>;
  49                         compatible = "st,clkgena-plls-c65";
  50
  51                         clocks = <&CLK_SYSIN>;
  52
  53                         clock-output-names = "CLK_S_A0_PLL0_HS",
  54                                              "CLK_S_A0_PLL0_LS",
  55                                              "CLK_S_A0_PLL1";
  56                 };
  57
  58                 CLK_S_A0_OSC_PREDIV: CLK_S_A0_OSC_PREDIV {
  59                         #clock-cells = <0>;
  60                         compatible = "st,clkgena-prediv-c65",
  61                                      "st,clkgena-prediv";
  62
  63                         clocks = <&CLK_SYSIN>;
  64
  65                         clock-output-names = "CLK_S_A0_OSC_PREDIV";
  66                 };
  67
  68                 CLK_S_A0_HS: CLK_S_A0_HS {
  69                         #clock-cells = <1>;
  70                         compatible = "st,clkgena-divmux-c65-hs",
  71                                      "st,clkgena-divmux";
  72
  73                         clocks = <&CLK_S_A0_OSC_PREDIV>,
  74                                  <&CLK_S_A0_PLL 0>, /* PLL0 HS */
  75                                  <&CLK_S_A0_PLL 2>; /* PLL1 */
  76
  77                         clock-output-names = "CLK_S_FDMA_0",
  78                                              "CLK_S_FDMA_1",
  79                                              ""; /* CLK_S_JIT_SENSE */
  80                                              /* Fourth output unused */
  81                 };
  82         };
  83