MIPS: Octeon: Fix CN6880 hang on XAUI init

Some CN68XX series Octeon II chips seem to hang if a reset is issued on
XAUI initialization. Avoid the hang by disabling the reset on affected
models. Tested on Cavium EBB6800 evaluation board and Kontron S1901 board.

Signed-off-by: Janne Huttunen <janne.huttunen@nokia.com>
Signed-off-by: Aaro Koskinen <aaro.koskinen@nokia.com>
Acked-by: David Daney <david.daney@cavium.com>
Cc: David Daney <ddaney.cavm@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: Janne Huttunen <janne.huttunen@nokia.com>
Cc: Aaro Koskinen <aaro.koskinen@nokia.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: devel@driverdev.osuosl.org
Patchwork: http://patchwork.linux-mips.org/patch/10970/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c b/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c
index 7653b7e92197f01d5091847172bb9c1087b2f29c..323a784f70711e921f75cc6fff06049788439e99 100644 (file)
--- a/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c
@@ -151,7 +151,12 @@ int __cvmx_helper_xaui_enable(int interface)
        /* (4)c Aply reset sequence */
        xauiCtl.u64 = cvmx_read_csr(CVMX_PCSXX_CONTROL1_REG(interface));
        xauiCtl.s.lo_pwr = 0;
-       xauiCtl.s.reset = 1;
+
+       /* Issuing a reset here seems to hang some CN68XX chips. */
+       if (!OCTEON_IS_MODEL(OCTEON_CN68XX_PASS1_X) &&
+           !OCTEON_IS_MODEL(OCTEON_CN68XX_PASS2_X))
+               xauiCtl.s.reset = 1;
+
        cvmx_write_csr(CVMX_PCSXX_CONTROL1_REG(interface), xauiCtl.u64);
 
        /* Wait for PCS to come out of reset */