net: thunderx: Enable CQE count threshold interrupt
authorSunil Goutham <sgoutham@cavium.com>
Thu, 10 Dec 2015 07:55:20 +0000 (13:25 +0530)
committerDavid S. Miller <davem@davemloft.net>
Sat, 12 Dec 2015 04:38:17 +0000 (23:38 -0500)
This feature is introduced in pass-2 chip and with this CQ interrupt
coalescing will work based on both timer and count.

Signed-off-by: Sunil Goutham <sgoutham@cavium.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/cavium/thunder/nicvf_queues.c
drivers/net/ethernet/cavium/thunder/nicvf_queues.h

index b11fc094f7694524424b4fc756e47a86b19c30a7..d0d1b54900610046955a390f6f5c87ce45cbf1df 100644 (file)
@@ -299,7 +299,7 @@ static int nicvf_init_cmp_queue(struct nicvf *nic,
                return err;
 
        cq->desc = cq->dmem.base;
-       cq->thresh = CMP_QUEUE_CQE_THRESH;
+       cq->thresh = pass1_silicon(nic->pdev) ? 0 : CMP_QUEUE_CQE_THRESH;
        nic->cq_coalesce_usecs = (CMP_QUEUE_TIMER_THRESH * 0.05) - 1;
 
        return 0;
index a4f6667fdbd44ad01245849377ad994bfb33c9a8..c5030a7f213ae57e9799142958e5d4fe64a8fbf5 100644 (file)
@@ -75,7 +75,7 @@
  */
 #define CMP_QSIZE              CMP_QUEUE_SIZE2
 #define CMP_QUEUE_LEN          (1ULL << (CMP_QSIZE + 10))
-#define CMP_QUEUE_CQE_THRESH   0
+#define CMP_QUEUE_CQE_THRESH   (NAPI_POLL_WEIGHT / 2)
 #define CMP_QUEUE_TIMER_THRESH 80 /* ~2usec */
 
 #define RBDR_SIZE              RBDR_SIZE0