MIPS: Read CPU IRQ line that FDC to routed to
authorJames Hogan <james.hogan@imgtec.com>
Thu, 29 Jan 2015 11:14:07 +0000 (11:14 +0000)
committerRalf Baechle <ralf@linux-mips.org>
Tue, 31 Mar 2015 10:04:12 +0000 (12:04 +0200)
Read the CPU IRQ line reportedly used for the Fast Debug Channel (FDC)
interrupt from the IntCtl register and store it in cp0_fdc_irq where
platform implementations of the new weak platform function
get_c0_fdc_int() can refer to it.

[ralf@linux-mips.org: Fixed conflict.]

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: James Hogan <james.hogan@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/9140/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/include/asm/irq.h
arch/mips/kernel/traps.c

index 5a4e1bb8fb1be99e98c372efa5138b7f7681ebbc..f0db99f8defe9b5ef17a7f39e6861916a85acd12 100644 (file)
@@ -47,6 +47,9 @@ extern void free_irqno(unsigned int irq);
 extern int cp0_compare_irq;
 extern int cp0_compare_irq_shift;
 extern int cp0_perfcount_irq;
+extern int cp0_fdc_irq;
+
+extern int __weak get_c0_fdc_int(void);
 
 void arch_trigger_all_cpu_backtrace(bool);
 #define arch_trigger_all_cpu_backtrace arch_trigger_all_cpu_backtrace
index 424567cfeb3d3609f0c1bf1ed732171c44793599..b0210b0651978ab6d6d5fd9bd23266a6058af50c 100644 (file)
@@ -1969,6 +1969,12 @@ int cp0_compare_irq_shift;
 int cp0_perfcount_irq;
 EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
 
+/*
+ * Fast debug channel IRQ or -1 if not present
+ */
+int cp0_fdc_irq;
+EXPORT_SYMBOL_GPL(cp0_fdc_irq);
+
 static int noulri;
 
 static int __init ulri_disable(char *s)
@@ -2050,15 +2056,21 @@ void per_cpu_trap_init(bool is_boot_cpu)
         *
         *  o read IntCtl.IPTI to determine the timer interrupt
         *  o read IntCtl.IPPCI to determine the performance counter interrupt
+        *  o read IntCtl.IPFDC to determine the fast debug channel interrupt
         */
        if (cpu_has_mips_r2_r6) {
                cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
                cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
                cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;
+               cp0_fdc_irq = (read_c0_intctl() >> INTCTLB_IPFDC) & 7;
+               if (!cp0_fdc_irq)
+                       cp0_fdc_irq = -1;
+
        } else {
                cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
                cp0_compare_irq_shift = CP0_LEGACY_PERFCNT_IRQ;
                cp0_perfcount_irq = -1;
+               cp0_fdc_irq = -1;
        }
 
        if (!cpu_data[cpu].asid_cache)