sound/pci/hda/hda_tegra.c

   1 /*
   2  *
   3  * Implementation of primary ALSA driver code base for NVIDIA Tegra HDA.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16  *
  17  */
  18
  19 #include <linux/clk.h>
  20 #include <linux/clocksource.h>
  21 #include <linux/completion.h>
  22 #include <linux/delay.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/init.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/io.h>
  27 #include <linux/kernel.h>
  28 #include <linux/module.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/mutex.h>
  31 #include <linux/of_device.h>
  32 #include <linux/slab.h>
  33 #include <linux/time.h>
  34
  35 #include <sound/core.h>
  36 #include <sound/initval.h>
  37
  38 #include "hda_codec.h"
  39 #include "hda_controller.h"
  40
  41 /* Defines for Nvidia Tegra HDA support */
  42 #define HDA_BAR0           0x8000
  43
  44 #define HDA_CFG_CMD        0x1004
  45 #define HDA_CFG_BAR0       0x1010
  46
  47 #define HDA_ENABLE_IO_SPACE       (1 << 0)
  48 #define HDA_ENABLE_MEM_SPACE      (1 << 1)
  49 #define HDA_ENABLE_BUS_MASTER     (1 << 2)
  50 #define HDA_ENABLE_SERR           (1 << 8)
  51 #define HDA_DISABLE_INTR          (1 << 10)
  52 #define HDA_BAR0_INIT_PROGRAM     0xFFFFFFFF
  53 #define HDA_BAR0_FINAL_PROGRAM    (1 << 14)
  54
  55 /* IPFS */
  56 #define HDA_IPFS_CONFIG           0x180
  57 #define HDA_IPFS_EN_FPCI          0x1
  58
  59 #define HDA_IPFS_FPCI_BAR0        0x80
  60 #define HDA_FPCI_BAR0_START       0x40
  61
  62 #define HDA_IPFS_INTR_MASK        0x188
  63 #define HDA_IPFS_EN_INTR          (1 << 16)
  64
  65 /* max number of SDs */
  66 #define NUM_CAPTURE_SD 1
  67 #define NUM_PLAYBACK_SD 1
  68
  69 struct hda_tegra {
  70         struct azx chip;
  71         struct device *dev;
  72         struct clk *hda_clk;
  73         struct clk *hda2codec_2x_clk;
  74         struct clk *hda2hdmi_clk;
  75         void __iomem *regs;
  76 };
  77
  78 #ifdef CONFIG_PM
  79 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
  80 module_param(power_save, bint, 0644);
  81 MODULE_PARM_DESC(power_save,
  82                  "Automatic power-saving timeout (in seconds, 0 = disable).");
  83 #else
  84 #define power_save      0
  85 #endif
  86
  87 /*
  88  * DMA page allocation ops.
  89  */
  90 static int dma_alloc_pages(struct hdac_bus *bus, int type, size_t size,
  91                            struct snd_dma_buffer *buf)
  92 {
  93         return snd_dma_alloc_pages(type, bus->dev, size, buf);
  94 }
  95
  96 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
  97 {
  98         snd_dma_free_pages(buf);
  99 }
 100
 101 static int substream_alloc_pages(struct azx *chip,
 102                                  struct snd_pcm_substream *substream,
 103                                  size_t size)
 104 {
 105         return snd_pcm_lib_malloc_pages(substream, size);
 106 }
 107
 108 static int substream_free_pages(struct azx *chip,
 109                                 struct snd_pcm_substream *substream)
 110 {
 111         return snd_pcm_lib_free_pages(substream);
 112 }
 113
 114 /*
 115  * Register access ops. Tegra HDA register access is DWORD only.
 116  */
 117 static void hda_tegra_writel(u32 value, u32 *addr)
 118 {
 119         writel(value, addr);
 120 }
 121
 122 static u32 hda_tegra_readl(u32 *addr)
 123 {
 124         return readl(addr);
 125 }
 126
 127 static void hda_tegra_writew(u16 value, u16 *addr)
 128 {
 129         unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
 130         void *dword_addr = (void *)((unsigned long)(addr) & ~0x3);
 131         u32 v;
 132
 133         v = readl(dword_addr);
 134         v &= ~(0xffff << shift);
 135         v |= value << shift;
 136         writel(v, dword_addr);
 137 }
 138
 139 static u16 hda_tegra_readw(u16 *addr)
 140 {
 141         unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
 142         void *dword_addr = (void *)((unsigned long)(addr) & ~0x3);
 143         u32 v;
 144
 145         v = readl(dword_addr);
 146         return (v >> shift) & 0xffff;
 147 }
 148
 149 static void hda_tegra_writeb(u8 value, u8 *addr)
 150 {
 151         unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
 152         void *dword_addr = (void *)((unsigned long)(addr) & ~0x3);
 153         u32 v;
 154
 155         v = readl(dword_addr);
 156         v &= ~(0xff << shift);
 157         v |= value << shift;
 158         writel(v, dword_addr);
 159 }
 160
 161 static u8 hda_tegra_readb(u8 *addr)
 162 {
 163         unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
 164         void *dword_addr = (void *)((unsigned long)(addr) & ~0x3);
 165         u32 v;
 166
 167         v = readl(dword_addr);
 168         return (v >> shift) & 0xff;
 169 }
 170
 171 static const struct hdac_io_ops hda_tegra_io_ops = {
 172         .reg_writel = hda_tegra_writel,
 173         .reg_readl = hda_tegra_readl,
 174         .reg_writew = hda_tegra_writew,
 175         .reg_readw = hda_tegra_readw,
 176         .reg_writeb = hda_tegra_writeb,
 177         .reg_readb = hda_tegra_readb,
 178         .dma_alloc_pages = dma_alloc_pages,
 179         .dma_free_pages = dma_free_pages,
 180 };
 181
 182 static const struct hda_controller_ops hda_tegra_ops = {
 183         .substream_alloc_pages = substream_alloc_pages,
 184         .substream_free_pages = substream_free_pages,
 185 };
 186
 187 static void hda_tegra_init(struct hda_tegra *hda)
 188 {
 189         u32 v;
 190
 191         /* Enable PCI access */
 192         v = readl(hda->regs + HDA_IPFS_CONFIG);
 193         v |= HDA_IPFS_EN_FPCI;
 194         writel(v, hda->regs + HDA_IPFS_CONFIG);
 195
 196         /* Enable MEM/IO space and bus master */
 197         v = readl(hda->regs + HDA_CFG_CMD);
 198         v &= ~HDA_DISABLE_INTR;
 199         v |= HDA_ENABLE_MEM_SPACE | HDA_ENABLE_IO_SPACE |
 200                 HDA_ENABLE_BUS_MASTER | HDA_ENABLE_SERR;
 201         writel(v, hda->regs + HDA_CFG_CMD);
 202
 203         writel(HDA_BAR0_INIT_PROGRAM, hda->regs + HDA_CFG_BAR0);
 204         writel(HDA_BAR0_FINAL_PROGRAM, hda->regs + HDA_CFG_BAR0);
 205         writel(HDA_FPCI_BAR0_START, hda->regs + HDA_IPFS_FPCI_BAR0);
 206
 207         v = readl(hda->regs + HDA_IPFS_INTR_MASK);
 208         v |= HDA_IPFS_EN_INTR;
 209         writel(v, hda->regs + HDA_IPFS_INTR_MASK);
 210 }
 211
 212 static int hda_tegra_enable_clocks(struct hda_tegra *data)
 213 {
 214         int rc;
 215
 216         rc = clk_prepare_enable(data->hda_clk);
 217         if (rc)
 218                 return rc;
 219         rc = clk_prepare_enable(data->hda2codec_2x_clk);
 220         if (rc)
 221                 goto disable_hda;
 222         rc = clk_prepare_enable(data->hda2hdmi_clk);
 223         if (rc)
 224                 goto disable_codec_2x;
 225
 226         return 0;
 227
 228 disable_codec_2x:
 229         clk_disable_unprepare(data->hda2codec_2x_clk);
 230 disable_hda:
 231         clk_disable_unprepare(data->hda_clk);
 232         return rc;
 233 }
 234
 235 #ifdef CONFIG_PM_SLEEP
 236 static void hda_tegra_disable_clocks(struct hda_tegra *data)
 237 {
 238         clk_disable_unprepare(data->hda2hdmi_clk);
 239         clk_disable_unprepare(data->hda2codec_2x_clk);
 240         clk_disable_unprepare(data->hda_clk);
 241 }
 242
 243 /*
 244  * power management
 245  */
 246 static int hda_tegra_suspend(struct device *dev)
 247 {
 248         struct snd_card *card = dev_get_drvdata(dev);
 249         struct azx *chip = card->private_data;
 250         struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
 251
 252         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
 253
 254         azx_stop_chip(chip);
 255         azx_enter_link_reset(chip);
 256         hda_tegra_disable_clocks(hda);
 257
 258         return 0;
 259 }
 260
 261 static int hda_tegra_resume(struct device *dev)
 262 {
 263         struct snd_card *card = dev_get_drvdata(dev);
 264         struct azx *chip = card->private_data;
 265         struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
 266
 267         hda_tegra_enable_clocks(hda);
 268
 269         hda_tegra_init(hda);
 270
 271         azx_init_chip(chip, 1);
 272
 273         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
 274
 275         return 0;
 276 }
 277 #endif /* CONFIG_PM_SLEEP */
 278
 279 static const struct dev_pm_ops hda_tegra_pm = {
 280         SET_SYSTEM_SLEEP_PM_OPS(hda_tegra_suspend, hda_tegra_resume)
 281 };
 282
 283 static int hda_tegra_dev_disconnect(struct snd_device *device)
 284 {
 285         struct azx *chip = device->device_data;
 286
 287         chip->bus.shutdown = 1;
 288         return 0;
 289 }
 290
 291 /*
 292  * destructor
 293  */
 294 static int hda_tegra_dev_free(struct snd_device *device)
 295 {
 296         struct azx *chip = device->device_data;
 297
 298         if (azx_bus(chip)->chip_init) {
 299                 azx_stop_all_streams(chip);
 300                 azx_stop_chip(chip);
 301         }
 302
 303         azx_free_stream_pages(chip);
 304         azx_free_streams(chip);
 305         snd_hdac_bus_exit(azx_bus(chip));
 306
 307         return 0;
 308 }
 309
 310 static int hda_tegra_init_chip(struct azx *chip, struct platform_device *pdev)
 311 {
 312         struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
 313         struct hdac_bus *bus = azx_bus(chip);
 314         struct device *dev = hda->dev;
 315         struct resource *res;
 316         int err;
 317
 318         hda->hda_clk = devm_clk_get(dev, "hda");
 319         if (IS_ERR(hda->hda_clk)) {
 320                 dev_err(dev, "failed to get hda clock\n");
 321                 return PTR_ERR(hda->hda_clk);
 322         }
 323         hda->hda2codec_2x_clk = devm_clk_get(dev, "hda2codec_2x");
 324         if (IS_ERR(hda->hda2codec_2x_clk)) {
 325                 dev_err(dev, "failed to get hda2codec_2x clock\n");
 326                 return PTR_ERR(hda->hda2codec_2x_clk);
 327         }
 328         hda->hda2hdmi_clk = devm_clk_get(dev, "hda2hdmi");
 329         if (IS_ERR(hda->hda2hdmi_clk)) {
 330                 dev_err(dev, "failed to get hda2hdmi clock\n");
 331                 return PTR_ERR(hda->hda2hdmi_clk);
 332         }
 333
 334         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 335         hda->regs = devm_ioremap_resource(dev, res);
 336         if (IS_ERR(hda->regs))
 337                 return PTR_ERR(hda->regs);
 338
 339         bus->remap_addr = hda->regs + HDA_BAR0;
 340         bus->addr = res->start + HDA_BAR0;
 341
 342         err = hda_tegra_enable_clocks(hda);
 343         if (err) {
 344                 dev_err(dev, "failed to get enable clocks\n");
 345                 return err;
 346         }
 347
 348         hda_tegra_init(hda);
 349
 350         return 0;
 351 }
 352
 353 static int hda_tegra_first_init(struct azx *chip, struct platform_device *pdev)
 354 {
 355         struct hdac_bus *bus = azx_bus(chip);
 356         struct snd_card *card = chip->card;
 357         int err;
 358         unsigned short gcap;
 359         int irq_id = platform_get_irq(pdev, 0);
 360
 361         err = hda_tegra_init_chip(chip, pdev);
 362         if (err)
 363                 return err;
 364
 365         err = devm_request_irq(chip->card->dev, irq_id, azx_interrupt,
 366                              IRQF_SHARED, KBUILD_MODNAME, chip);
 367         if (err) {
 368                 dev_err(chip->card->dev,
 369                         "unable to request IRQ %d, disabling device\n",
 370                         irq_id);
 371                 return err;
 372         }
 373         bus->irq = irq_id;
 374
 375         synchronize_irq(bus->irq);
 376
 377         gcap = azx_readw(chip, GCAP);
 378         dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
 379
 380         /* read number of streams from GCAP register instead of using
 381          * hardcoded value
 382          */
 383         chip->capture_streams = (gcap >> 8) & 0x0f;
 384         chip->playback_streams = (gcap >> 12) & 0x0f;
 385         if (!chip->playback_streams && !chip->capture_streams) {
 386                 /* gcap didn't give any info, switching to old method */
 387                 chip->playback_streams = NUM_PLAYBACK_SD;
 388                 chip->capture_streams = NUM_CAPTURE_SD;
 389         }
 390         chip->capture_index_offset = 0;
 391         chip->playback_index_offset = chip->capture_streams;
 392         chip->num_streams = chip->playback_streams + chip->capture_streams;
 393
 394         /* initialize streams */
 395         err = azx_init_streams(chip);
 396         if (err < 0) {
 397                 dev_err(card->dev, "failed to initialize streams: %d\n", err);
 398                 return err;
 399         }
 400
 401         err = azx_alloc_stream_pages(chip);
 402         if (err < 0) {
 403                 dev_err(card->dev, "failed to allocate stream pages: %d\n",
 404                         err);
 405                 return err;
 406         }
 407
 408         /* initialize chip */
 409         azx_init_chip(chip, 1);
 410
 411         /* codec detection */
 412         if (!bus->codec_mask) {
 413                 dev_err(card->dev, "no codecs found!\n");
 414                 return -ENODEV;
 415         }
 416
 417         strcpy(card->driver, "tegra-hda");
 418         strcpy(card->shortname, "tegra-hda");
 419         snprintf(card->longname, sizeof(card->longname),
 420                  "%s at 0x%lx irq %i",
 421                  card->shortname, bus->addr, bus->irq);
 422
 423         return 0;
 424 }
 425
 426 /*
 427  * constructor
 428  */
 429 static int hda_tegra_create(struct snd_card *card,
 430                             unsigned int driver_caps,
 431                             struct hda_tegra *hda)
 432 {
 433         static struct snd_device_ops ops = {
 434                 .dev_disconnect = hda_tegra_dev_disconnect,
 435                 .dev_free = hda_tegra_dev_free,
 436         };
 437         struct azx *chip;
 438         int err;
 439
 440         chip = &hda->chip;
 441
 442         mutex_init(&chip->open_mutex);
 443         chip->card = card;
 444         chip->ops = &hda_tegra_ops;
 445         chip->driver_caps = driver_caps;
 446         chip->driver_type = driver_caps & 0xff;
 447         chip->dev_index = 0;
 448         INIT_LIST_HEAD(&chip->pcm_list);
 449
 450         chip->codec_probe_mask = -1;
 451
 452         chip->single_cmd = false;
 453         chip->snoop = true;
 454
 455         err = azx_bus_init(chip, NULL, &hda_tegra_io_ops);
 456         if (err < 0)
 457                 return err;
 458
 459         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
 460         if (err < 0) {
 461                 dev_err(card->dev, "Error creating device\n");
 462                 return err;
 463         }
 464
 465         return 0;
 466 }
 467
 468 static const struct of_device_id hda_tegra_match[] = {
 469         { .compatible = "nvidia,tegra30-hda" },
 470         {},
 471 };
 472 MODULE_DEVICE_TABLE(of, hda_tegra_match);
 473
 474 static int hda_tegra_probe(struct platform_device *pdev)
 475 {
 476         const unsigned int driver_flags = AZX_DCAPS_RIRB_DELAY |
 477                                           AZX_DCAPS_CORBRP_SELF_CLEAR;
 478         struct snd_card *card;
 479         struct azx *chip;
 480         struct hda_tegra *hda;
 481         int err;
 482
 483         hda = devm_kzalloc(&pdev->dev, sizeof(*hda), GFP_KERNEL);
 484         if (!hda)
 485                 return -ENOMEM;
 486         hda->dev = &pdev->dev;
 487         chip = &hda->chip;
 488
 489         err = snd_card_new(&pdev->dev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
 490                            THIS_MODULE, 0, &card);
 491         if (err < 0) {
 492                 dev_err(&pdev->dev, "Error creating card!\n");
 493                 return err;
 494         }
 495
 496         err = hda_tegra_create(card, driver_flags, hda);
 497         if (err < 0)
 498                 goto out_free;
 499         card->private_data = chip;
 500
 501         dev_set_drvdata(&pdev->dev, card);
 502
 503         err = hda_tegra_first_init(chip, pdev);
 504         if (err < 0)
 505                 goto out_free;
 506
 507         /* create codec instances */
 508         err = azx_probe_codecs(chip, 0);
 509         if (err < 0)
 510                 goto out_free;
 511
 512         err = azx_codec_configure(chip);
 513         if (err < 0)
 514                 goto out_free;
 515
 516         err = snd_card_register(chip->card);
 517         if (err < 0)
 518                 goto out_free;
 519
 520         chip->running = 1;
 521         snd_hda_set_power_save(&chip->bus, power_save * 1000);
 522
 523         return 0;
 524
 525 out_free:
 526         snd_card_free(card);
 527         return err;
 528 }
 529
 530 static int hda_tegra_remove(struct platform_device *pdev)
 531 {
 532         return snd_card_free(dev_get_drvdata(&pdev->dev));
 533 }
 534
 535 static void hda_tegra_shutdown(struct platform_device *pdev)
 536 {
 537         struct snd_card *card = dev_get_drvdata(&pdev->dev);
 538         struct azx *chip;
 539
 540         if (!card)
 541                 return;
 542         chip = card->private_data;
 543         if (chip && chip->running)
 544                 azx_stop_chip(chip);
 545 }
 546
 547 static struct platform_driver tegra_platform_hda = {
 548         .driver = {
 549                 .name = "tegra-hda",
 550                 .pm = &hda_tegra_pm,
 551                 .of_match_table = hda_tegra_match,
 552         },
 553         .probe = hda_tegra_probe,
 554         .remove = hda_tegra_remove,
 555         .shutdown = hda_tegra_shutdown,
 556 };
 557 module_platform_driver(tegra_platform_hda);
 558
 559 MODULE_DESCRIPTION("Tegra HDA bus driver");
 560 MODULE_LICENSE("GPL v2");