sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base
   4  *                for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the Free
  13  *  Software Foundation; either version 2 of the License, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  *  more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along with
  22  *  this program; if not, write to the Free Software Foundation, Inc., 59
  23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  24  *
  25  *  CONTACTS:
  26  *
  27  *  Matt Jared          matt.jared@intel.com
  28  *  Andy Kopp           andy.kopp@intel.com
  29  *  Dan Kogan           dan.d.kogan@intel.com
  30  *
  31  *  CHANGES:
  32  *
  33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  34  *
  35  */
  36
  37 #include <linux/delay.h>
  38 #include <linux/interrupt.h>
  39 #include <linux/kernel.h>
  40 #include <linux/module.h>
  41 #include <linux/dma-mapping.h>
  42 #include <linux/moduleparam.h>
  43 #include <linux/init.h>
  44 #include <linux/slab.h>
  45 #include <linux/pci.h>
  46 #include <linux/mutex.h>
  47 #include <linux/io.h>
  48 #include <linux/pm_runtime.h>
  49 #include <linux/clocksource.h>
  50 #include <linux/time.h>
  51 #include <linux/completion.h>
  52
  53 #ifdef CONFIG_X86
  54 /* for snoop control */
  55 #include <asm/pgtable.h>
  56 #include <asm/cacheflush.h>
  57 #endif
  58 #include <sound/core.h>
  59 #include <sound/initval.h>
  60 #include <sound/hdaudio.h>
  61 #include <sound/hda_i915.h>
  62 #include <linux/vgaarb.h>
  63 #include <linux/vga_switcheroo.h>
  64 #include <linux/firmware.h>
  65 #include "hda_codec.h"
  66 #include "hda_controller.h"
  67 #include "hda_intel.h"
  68
  69 #define CREATE_TRACE_POINTS
  70 #include "hda_intel_trace.h"
  71
  72 /* position fix mode */
  73 enum {
  74         POS_FIX_AUTO,
  75         POS_FIX_LPIB,
  76         POS_FIX_POSBUF,
  77         POS_FIX_VIACOMBO,
  78         POS_FIX_COMBO,
  79 };
  80
  81 /* Defines for ATI HD Audio support in SB450 south bridge */
  82 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
  83 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
  84
  85 /* Defines for Nvidia HDA support */
  86 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
  87 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
  88 #define NVIDIA_HDA_ISTRM_COH          0x4d
  89 #define NVIDIA_HDA_OSTRM_COH          0x4c
  90 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
  91
  92 /* Defines for Intel SCH HDA snoop control */
  93 #define INTEL_SCH_HDA_DEVC      0x78
  94 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
  95
  96 /* Define IN stream 0 FIFO size offset in VIA controller */
  97 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
  98 /* Define VIA HD Audio Device ID*/
  99 #define VIA_HDAC_DEVICE_ID              0x3288
 100
 101 /* max number of SDs */
 102 /* ICH, ATI and VIA have 4 playback and 4 capture */
 103 #define ICH6_NUM_CAPTURE        4
 104 #define ICH6_NUM_PLAYBACK       4
 105
 106 /* ULI has 6 playback and 5 capture */
 107 #define ULI_NUM_CAPTURE         5
 108 #define ULI_NUM_PLAYBACK        6
 109
 110 /* ATI HDMI may have up to 8 playbacks and 0 capture */
 111 #define ATIHDMI_NUM_CAPTURE     0
 112 #define ATIHDMI_NUM_PLAYBACK    8
 113
 114 /* TERA has 4 playback and 3 capture */
 115 #define TERA_NUM_CAPTURE        3
 116 #define TERA_NUM_PLAYBACK       4
 117
 118
 119 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
 120 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
 121 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
 122 static char *model[SNDRV_CARDS];
 123 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 124 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 125 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 126 static int probe_only[SNDRV_CARDS];
 127 static int jackpoll_ms[SNDRV_CARDS];
 128 static bool single_cmd;
 129 static int enable_msi = -1;
 130 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 131 static char *patch[SNDRV_CARDS];
 132 #endif
 133 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 134 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
 135                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
 136 #endif
 137
 138 module_param_array(index, int, NULL, 0444);
 139 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
 140 module_param_array(id, charp, NULL, 0444);
 141 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
 142 module_param_array(enable, bool, NULL, 0444);
 143 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
 144 module_param_array(model, charp, NULL, 0444);
 145 MODULE_PARM_DESC(model, "Use the given board model.");
 146 module_param_array(position_fix, int, NULL, 0444);
 147 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
 148                  "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
 149 module_param_array(bdl_pos_adj, int, NULL, 0644);
 150 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
 151 module_param_array(probe_mask, int, NULL, 0444);
 152 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
 153 module_param_array(probe_only, int, NULL, 0444);
 154 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
 155 module_param_array(jackpoll_ms, int, NULL, 0444);
 156 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
 157 module_param(single_cmd, bool, 0444);
 158 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
 159                  "(for debugging only).");
 160 module_param(enable_msi, bint, 0444);
 161 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
 162 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 163 module_param_array(patch, charp, NULL, 0444);
 164 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
 165 #endif
 166 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 167 module_param_array(beep_mode, bool, NULL, 0444);
 168 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 169                             "(0=off, 1=on) (default=1).");
 170 #endif
 171
 172 #ifdef CONFIG_PM
 173 static int param_set_xint(const char *val, const struct kernel_param *kp);
 174 static const struct kernel_param_ops param_ops_xint = {
 175         .set = param_set_xint,
 176         .get = param_get_int,
 177 };
 178 #define param_check_xint param_check_int
 179
 180 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 181 module_param(power_save, xint, 0644);
 182 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 183                  "(in second, 0 = disable).");
 184
 185 /* reset the HD-audio controller in power save mode.
 186  * this may give more power-saving, but will take longer time to
 187  * wake up.
 188  */
 189 static bool power_save_controller = 1;
 190 module_param(power_save_controller, bool, 0644);
 191 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 192 #else
 193 #define power_save      0
 194 #endif /* CONFIG_PM */
 195
 196 static int align_buffer_size = -1;
 197 module_param(align_buffer_size, bint, 0644);
 198 MODULE_PARM_DESC(align_buffer_size,
 199                 "Force buffer and period sizes to be multiple of 128 bytes.");
 200
 201 #ifdef CONFIG_X86
 202 static int hda_snoop = -1;
 203 module_param_named(snoop, hda_snoop, bint, 0444);
 204 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
 205 #else
 206 #define hda_snoop               true
 207 #endif
 208
 209
 210 MODULE_LICENSE("GPL");
 211 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 212                          "{Intel, ICH6M},"
 213                          "{Intel, ICH7},"
 214                          "{Intel, ESB2},"
 215                          "{Intel, ICH8},"
 216                          "{Intel, ICH9},"
 217                          "{Intel, ICH10},"
 218                          "{Intel, PCH},"
 219                          "{Intel, CPT},"
 220                          "{Intel, PPT},"
 221                          "{Intel, LPT},"
 222                          "{Intel, LPT_LP},"
 223                          "{Intel, WPT_LP},"
 224                          "{Intel, SPT},"
 225                          "{Intel, SPT_LP},"
 226                          "{Intel, HPT},"
 227                          "{Intel, PBG},"
 228                          "{Intel, SCH},"
 229                          "{ATI, SB450},"
 230                          "{ATI, SB600},"
 231                          "{ATI, RS600},"
 232                          "{ATI, RS690},"
 233                          "{ATI, RS780},"
 234                          "{ATI, R600},"
 235                          "{ATI, RV630},"
 236                          "{ATI, RV610},"
 237                          "{ATI, RV670},"
 238                          "{ATI, RV635},"
 239                          "{ATI, RV620},"
 240                          "{ATI, RV770},"
 241                          "{VIA, VT8251},"
 242                          "{VIA, VT8237A},"
 243                          "{SiS, SIS966},"
 244                          "{ULI, M5461}}");
 245 MODULE_DESCRIPTION("Intel HDA driver");
 246
 247 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
 248 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
 249 #define SUPPORT_VGA_SWITCHEROO
 250 #endif
 251 #endif
 252
 253
 254 /*
 255  */
 256
 257 /* driver types */
 258 enum {
 259         AZX_DRIVER_ICH,
 260         AZX_DRIVER_PCH,
 261         AZX_DRIVER_SCH,
 262         AZX_DRIVER_HDMI,
 263         AZX_DRIVER_ATI,
 264         AZX_DRIVER_ATIHDMI,
 265         AZX_DRIVER_ATIHDMI_NS,
 266         AZX_DRIVER_VIA,
 267         AZX_DRIVER_SIS,
 268         AZX_DRIVER_ULI,
 269         AZX_DRIVER_NVIDIA,
 270         AZX_DRIVER_TERA,
 271         AZX_DRIVER_CTX,
 272         AZX_DRIVER_CTHDA,
 273         AZX_DRIVER_CMEDIA,
 274         AZX_DRIVER_GENERIC,
 275         AZX_NUM_DRIVERS, /* keep this as last entry */
 276 };
 277
 278 #define azx_get_snoop_type(chip) \
 279         (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
 280 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
 281
 282 /* quirks for old Intel chipsets */
 283 #define AZX_DCAPS_INTEL_ICH \
 284         (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
 285
 286 /* quirks for Intel PCH */
 287 #define AZX_DCAPS_INTEL_PCH_BASE \
 288         (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
 289          AZX_DCAPS_REVERSE_ASSIGN | AZX_DCAPS_SNOOP_TYPE(SCH))
 290
 291 /* PCH up to IVB; bound with i915 audio component for HDMI, no runtime PM */
 292 #define AZX_DCAPS_INTEL_PCH_NOPM \
 293         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_POWERWELL)
 294
 295 /* PCH for HSW/BDW; with runtime PM, but no i915 binding */
 296 #define AZX_DCAPS_INTEL_PCH \
 297         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
 298
 299 /* HSW HDMI */
 300 #define AZX_DCAPS_INTEL_HASWELL \
 301         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
 302          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
 303          AZX_DCAPS_SNOOP_TYPE(SCH))
 304
 305 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
 306 #define AZX_DCAPS_INTEL_BROADWELL \
 307         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
 308          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
 309          AZX_DCAPS_SNOOP_TYPE(SCH))
 310
 311 #define AZX_DCAPS_INTEL_BAYTRAIL \
 312         (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_I915_POWERWELL)
 313
 314 #define AZX_DCAPS_INTEL_BRASWELL \
 315         (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_I915_POWERWELL)
 316
 317 #define AZX_DCAPS_INTEL_SKYLAKE \
 318         (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
 319          AZX_DCAPS_I915_POWERWELL)
 320
 321 #define AZX_DCAPS_INTEL_BROXTON \
 322         (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
 323          AZX_DCAPS_I915_POWERWELL)
 324
 325 /* quirks for ATI SB / AMD Hudson */
 326 #define AZX_DCAPS_PRESET_ATI_SB \
 327         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
 328          AZX_DCAPS_SNOOP_TYPE(ATI))
 329
 330 /* quirks for ATI/AMD HDMI */
 331 #define AZX_DCAPS_PRESET_ATI_HDMI \
 332         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
 333          AZX_DCAPS_NO_MSI64)
 334
 335 /* quirks for ATI HDMI with snoop off */
 336 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
 337         (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
 338
 339 /* quirks for Nvidia */
 340 #define AZX_DCAPS_PRESET_NVIDIA \
 341         (AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI | /*AZX_DCAPS_ALIGN_BUFSIZE |*/ \
 342          AZX_DCAPS_NO_64BIT | AZX_DCAPS_CORBRP_SELF_CLEAR |\
 343          AZX_DCAPS_SNOOP_TYPE(NVIDIA))
 344
 345 #define AZX_DCAPS_PRESET_CTHDA \
 346         (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
 347          AZX_DCAPS_NO_64BIT |\
 348          AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
 349
 350 /*
 351  * vga_switcheroo support
 352  */
 353 #ifdef SUPPORT_VGA_SWITCHEROO
 354 #define use_vga_switcheroo(chip)        ((chip)->use_vga_switcheroo)
 355 #else
 356 #define use_vga_switcheroo(chip)        0
 357 #endif
 358
 359 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
 360                                         ((pci)->device == 0x0c0c) || \
 361                                         ((pci)->device == 0x0d0c) || \
 362                                         ((pci)->device == 0x160c))
 363
 364 static char *driver_short_names[] = {
 365         [AZX_DRIVER_ICH] = "HDA Intel",
 366         [AZX_DRIVER_PCH] = "HDA Intel PCH",
 367         [AZX_DRIVER_SCH] = "HDA Intel MID",
 368         [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
 369         [AZX_DRIVER_ATI] = "HDA ATI SB",
 370         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 371         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
 372         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 373         [AZX_DRIVER_SIS] = "HDA SIS966",
 374         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 375         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 376         [AZX_DRIVER_TERA] = "HDA Teradici",
 377         [AZX_DRIVER_CTX] = "HDA Creative",
 378         [AZX_DRIVER_CTHDA] = "HDA Creative",
 379         [AZX_DRIVER_CMEDIA] = "HDA C-Media",
 380         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 381 };
 382
 383 #ifdef CONFIG_X86
 384 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
 385 {
 386         int pages;
 387
 388         if (azx_snoop(chip))
 389                 return;
 390         if (!dmab || !dmab->area || !dmab->bytes)
 391                 return;
 392
 393 #ifdef CONFIG_SND_DMA_SGBUF
 394         if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
 395                 struct snd_sg_buf *sgbuf = dmab->private_data;
 396                 if (chip->driver_type == AZX_DRIVER_CMEDIA)
 397                         return; /* deal with only CORB/RIRB buffers */
 398                 if (on)
 399                         set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
 400                 else
 401                         set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
 402                 return;
 403         }
 404 #endif
 405
 406         pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
 407         if (on)
 408                 set_memory_wc((unsigned long)dmab->area, pages);
 409         else
 410                 set_memory_wb((unsigned long)dmab->area, pages);
 411 }
 412
 413 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 414                                  bool on)
 415 {
 416         __mark_pages_wc(chip, buf, on);
 417 }
 418 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 419                                    struct snd_pcm_substream *substream, bool on)
 420 {
 421         if (azx_dev->wc_marked != on) {
 422                 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
 423                 azx_dev->wc_marked = on;
 424         }
 425 }
 426 #else
 427 /* NOP for other archs */
 428 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 429                                  bool on)
 430 {
 431 }
 432 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 433                                    struct snd_pcm_substream *substream, bool on)
 434 {
 435 }
 436 #endif
 437
 438 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 439
 440 /*
 441  * initialize the PCI registers
 442  */
 443 /* update bits in a PCI register byte */
 444 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
 445                             unsigned char mask, unsigned char val)
 446 {
 447         unsigned char data;
 448
 449         pci_read_config_byte(pci, reg, &data);
 450         data &= ~mask;
 451         data |= (val & mask);
 452         pci_write_config_byte(pci, reg, data);
 453 }
 454
 455 static void azx_init_pci(struct azx *chip)
 456 {
 457         int snoop_type = azx_get_snoop_type(chip);
 458
 459         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 460          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 461          * Ensuring these bits are 0 clears playback static on some HD Audio
 462          * codecs.
 463          * The PCI register TCSEL is defined in the Intel manuals.
 464          */
 465         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
 466                 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
 467                 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
 468         }
 469
 470         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
 471          * we need to enable snoop.
 472          */
 473         if (snoop_type == AZX_SNOOP_TYPE_ATI) {
 474                 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
 475                         azx_snoop(chip));
 476                 update_pci_byte(chip->pci,
 477                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
 478                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
 479         }
 480
 481         /* For NVIDIA HDA, enable snoop */
 482         if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
 483                 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
 484                         azx_snoop(chip));
 485                 update_pci_byte(chip->pci,
 486                                 NVIDIA_HDA_TRANSREG_ADDR,
 487                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
 488                 update_pci_byte(chip->pci,
 489                                 NVIDIA_HDA_ISTRM_COH,
 490                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 491                 update_pci_byte(chip->pci,
 492                                 NVIDIA_HDA_OSTRM_COH,
 493                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 494         }
 495
 496         /* Enable SCH/PCH snoop if needed */
 497         if (snoop_type == AZX_SNOOP_TYPE_SCH) {
 498                 unsigned short snoop;
 499                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
 500                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
 501                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
 502                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
 503                         if (!azx_snoop(chip))
 504                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
 505                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
 506                         pci_read_config_word(chip->pci,
 507                                 INTEL_SCH_HDA_DEVC, &snoop);
 508                 }
 509                 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
 510                         (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
 511                         "Disabled" : "Enabled");
 512         }
 513 }
 514
 515 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
 516 {
 517         struct hdac_bus *bus = azx_bus(chip);
 518
 519         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
 520                 snd_hdac_set_codec_wakeup(bus, true);
 521         azx_init_chip(chip, full_reset);
 522         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
 523                 snd_hdac_set_codec_wakeup(bus, false);
 524 }
 525
 526 /* calculate runtime delay from LPIB */
 527 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
 528                                    unsigned int pos)
 529 {
 530         struct snd_pcm_substream *substream = azx_dev->core.substream;
 531         int stream = substream->stream;
 532         unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
 533         int delay;
 534
 535         if (stream == SNDRV_PCM_STREAM_PLAYBACK)
 536                 delay = pos - lpib_pos;
 537         else
 538                 delay = lpib_pos - pos;
 539         if (delay < 0) {
 540                 if (delay >= azx_dev->core.delay_negative_threshold)
 541                         delay = 0;
 542                 else
 543                         delay += azx_dev->core.bufsize;
 544         }
 545
 546         if (delay >= azx_dev->core.period_bytes) {
 547                 dev_info(chip->card->dev,
 548                          "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
 549                          delay, azx_dev->core.period_bytes);
 550                 delay = 0;
 551                 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
 552                 chip->get_delay[stream] = NULL;
 553         }
 554
 555         return bytes_to_frames(substream->runtime, delay);
 556 }
 557
 558 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
 559
 560 /* called from IRQ */
 561 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
 562 {
 563         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 564         int ok;
 565
 566         ok = azx_position_ok(chip, azx_dev);
 567         if (ok == 1) {
 568                 azx_dev->irq_pending = 0;
 569                 return ok;
 570         } else if (ok == 0) {
 571                 /* bogus IRQ, process it later */
 572                 azx_dev->irq_pending = 1;
 573                 schedule_work(&hda->irq_pending_work);
 574         }
 575         return 0;
 576 }
 577
 578 /* Enable/disable i915 display power for the link */
 579 static int azx_intel_link_power(struct azx *chip, bool enable)
 580 {
 581         struct hdac_bus *bus = azx_bus(chip);
 582
 583         return snd_hdac_display_power(bus, enable);
 584 }
 585
 586 /*
 587  * Check whether the current DMA position is acceptable for updating
 588  * periods.  Returns non-zero if it's OK.
 589  *
 590  * Many HD-audio controllers appear pretty inaccurate about
 591  * the update-IRQ timing.  The IRQ is issued before actually the
 592  * data is processed.  So, we need to process it afterwords in a
 593  * workqueue.
 594  */
 595 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
 596 {
 597         struct snd_pcm_substream *substream = azx_dev->core.substream;
 598         int stream = substream->stream;
 599         u32 wallclk;
 600         unsigned int pos;
 601
 602         wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
 603         if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
 604                 return -1;      /* bogus (too early) interrupt */
 605
 606         if (chip->get_position[stream])
 607                 pos = chip->get_position[stream](chip, azx_dev);
 608         else { /* use the position buffer as default */
 609                 pos = azx_get_pos_posbuf(chip, azx_dev);
 610                 if (!pos || pos == (u32)-1) {
 611                         dev_info(chip->card->dev,
 612                                  "Invalid position buffer, using LPIB read method instead.\n");
 613                         chip->get_position[stream] = azx_get_pos_lpib;
 614                         if (chip->get_position[0] == azx_get_pos_lpib &&
 615                             chip->get_position[1] == azx_get_pos_lpib)
 616                                 azx_bus(chip)->use_posbuf = false;
 617                         pos = azx_get_pos_lpib(chip, azx_dev);
 618                         chip->get_delay[stream] = NULL;
 619                 } else {
 620                         chip->get_position[stream] = azx_get_pos_posbuf;
 621                         if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
 622                                 chip->get_delay[stream] = azx_get_delay_from_lpib;
 623                 }
 624         }
 625
 626         if (pos >= azx_dev->core.bufsize)
 627                 pos = 0;
 628
 629         if (WARN_ONCE(!azx_dev->core.period_bytes,
 630                       "hda-intel: zero azx_dev->period_bytes"))
 631                 return -1; /* this shouldn't happen! */
 632         if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
 633             pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
 634                 /* NG - it's below the first next period boundary */
 635                 return chip->bdl_pos_adj[chip->dev_index] ? 0 : -1;
 636         azx_dev->core.start_wallclk += wallclk;
 637         return 1; /* OK, it's fine */
 638 }
 639
 640 /*
 641  * The work for pending PCM period updates.
 642  */
 643 static void azx_irq_pending_work(struct work_struct *work)
 644 {
 645         struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
 646         struct azx *chip = &hda->chip;
 647         struct hdac_bus *bus = azx_bus(chip);
 648         struct hdac_stream *s;
 649         int pending, ok;
 650
 651         if (!hda->irq_pending_warned) {
 652                 dev_info(chip->card->dev,
 653                          "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
 654                          chip->card->number);
 655                 hda->irq_pending_warned = 1;
 656         }
 657
 658         for (;;) {
 659                 pending = 0;
 660                 spin_lock_irq(&bus->reg_lock);
 661                 list_for_each_entry(s, &bus->stream_list, list) {
 662                         struct azx_dev *azx_dev = stream_to_azx_dev(s);
 663                         if (!azx_dev->irq_pending ||
 664                             !s->substream ||
 665                             !s->running)
 666                                 continue;
 667                         ok = azx_position_ok(chip, azx_dev);
 668                         if (ok > 0) {
 669                                 azx_dev->irq_pending = 0;
 670                                 spin_unlock(&bus->reg_lock);
 671                                 snd_pcm_period_elapsed(s->substream);
 672                                 spin_lock(&bus->reg_lock);
 673                         } else if (ok < 0) {
 674                                 pending = 0;    /* too early */
 675                         } else
 676                                 pending++;
 677                 }
 678                 spin_unlock_irq(&bus->reg_lock);
 679                 if (!pending)
 680                         return;
 681                 msleep(1);
 682         }
 683 }
 684
 685 /* clear irq_pending flags and assure no on-going workq */
 686 static void azx_clear_irq_pending(struct azx *chip)
 687 {
 688         struct hdac_bus *bus = azx_bus(chip);
 689         struct hdac_stream *s;
 690
 691         spin_lock_irq(&bus->reg_lock);
 692         list_for_each_entry(s, &bus->stream_list, list) {
 693                 struct azx_dev *azx_dev = stream_to_azx_dev(s);
 694                 azx_dev->irq_pending = 0;
 695         }
 696         spin_unlock_irq(&bus->reg_lock);
 697 }
 698
 699 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
 700 {
 701         struct hdac_bus *bus = azx_bus(chip);
 702
 703         if (request_irq(chip->pci->irq, azx_interrupt,
 704                         chip->msi ? 0 : IRQF_SHARED,
 705                         KBUILD_MODNAME, chip)) {
 706                 dev_err(chip->card->dev,
 707                         "unable to grab IRQ %d, disabling device\n",
 708                         chip->pci->irq);
 709                 if (do_disconnect)
 710                         snd_card_disconnect(chip->card);
 711                 return -1;
 712         }
 713         bus->irq = chip->pci->irq;
 714         pci_intx(chip->pci, !chip->msi);
 715         return 0;
 716 }
 717
 718 /* get the current DMA position with correction on VIA chips */
 719 static unsigned int azx_via_get_position(struct azx *chip,
 720                                          struct azx_dev *azx_dev)
 721 {
 722         unsigned int link_pos, mini_pos, bound_pos;
 723         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
 724         unsigned int fifo_size;
 725
 726         link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 727         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 728                 /* Playback, no problem using link position */
 729                 return link_pos;
 730         }
 731
 732         /* Capture */
 733         /* For new chipset,
 734          * use mod to get the DMA position just like old chipset
 735          */
 736         mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
 737         mod_dma_pos %= azx_dev->core.period_bytes;
 738
 739         /* azx_dev->fifo_size can't get FIFO size of in stream.
 740          * Get from base address + offset.
 741          */
 742         fifo_size = readw(azx_bus(chip)->remap_addr +
 743                           VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
 744
 745         if (azx_dev->insufficient) {
 746                 /* Link position never gather than FIFO size */
 747                 if (link_pos <= fifo_size)
 748                         return 0;
 749
 750                 azx_dev->insufficient = 0;
 751         }
 752
 753         if (link_pos <= fifo_size)
 754                 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
 755         else
 756                 mini_pos = link_pos - fifo_size;
 757
 758         /* Find nearest previous boudary */
 759         mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
 760         mod_link_pos = link_pos % azx_dev->core.period_bytes;
 761         if (mod_link_pos >= fifo_size)
 762                 bound_pos = link_pos - mod_link_pos;
 763         else if (mod_dma_pos >= mod_mini_pos)
 764                 bound_pos = mini_pos - mod_mini_pos;
 765         else {
 766                 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
 767                 if (bound_pos >= azx_dev->core.bufsize)
 768                         bound_pos = 0;
 769         }
 770
 771         /* Calculate real DMA position we want */
 772         return bound_pos + mod_dma_pos;
 773 }
 774
 775 #ifdef CONFIG_PM
 776 static DEFINE_MUTEX(card_list_lock);
 777 static LIST_HEAD(card_list);
 778
 779 static void azx_add_card_list(struct azx *chip)
 780 {
 781         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 782         mutex_lock(&card_list_lock);
 783         list_add(&hda->list, &card_list);
 784         mutex_unlock(&card_list_lock);
 785 }
 786
 787 static void azx_del_card_list(struct azx *chip)
 788 {
 789         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 790         mutex_lock(&card_list_lock);
 791         list_del_init(&hda->list);
 792         mutex_unlock(&card_list_lock);
 793 }
 794
 795 /* trigger power-save check at writing parameter */
 796 static int param_set_xint(const char *val, const struct kernel_param *kp)
 797 {
 798         struct hda_intel *hda;
 799         struct azx *chip;
 800         int prev = power_save;
 801         int ret = param_set_int(val, kp);
 802
 803         if (ret || prev == power_save)
 804                 return ret;
 805
 806         mutex_lock(&card_list_lock);
 807         list_for_each_entry(hda, &card_list, list) {
 808                 chip = &hda->chip;
 809                 if (!hda->probe_continued || chip->disabled)
 810                         continue;
 811                 snd_hda_set_power_save(&chip->bus, power_save * 1000);
 812         }
 813         mutex_unlock(&card_list_lock);
 814         return 0;
 815 }
 816 #else
 817 #define azx_add_card_list(chip) /* NOP */
 818 #define azx_del_card_list(chip) /* NOP */
 819 #endif /* CONFIG_PM */
 820
 821 /* Intel HSW/BDW display HDA controller is in GPU. Both its power and link BCLK
 822  * depends on GPU. Two Extended Mode registers EM4 (M value) and EM5 (N Value)
 823  * are used to convert CDClk (Core Display Clock) to 24MHz BCLK:
 824  * BCLK = CDCLK * M / N
 825  * The values will be lost when the display power well is disabled and need to
 826  * be restored to avoid abnormal playback speed.
 827  */
 828 static void haswell_set_bclk(struct hda_intel *hda)
 829 {
 830         struct azx *chip = &hda->chip;
 831         int cdclk_freq;
 832         unsigned int bclk_m, bclk_n;
 833
 834         if (!hda->need_i915_power)
 835                 return;
 836
 837         cdclk_freq = snd_hdac_get_display_clk(azx_bus(chip));
 838         switch (cdclk_freq) {
 839         case 337500:
 840                 bclk_m = 16;
 841                 bclk_n = 225;
 842                 break;
 843
 844         case 450000:
 845         default: /* default CDCLK 450MHz */
 846                 bclk_m = 4;
 847                 bclk_n = 75;
 848                 break;
 849
 850         case 540000:
 851                 bclk_m = 4;
 852                 bclk_n = 90;
 853                 break;
 854
 855         case 675000:
 856                 bclk_m = 8;
 857                 bclk_n = 225;
 858                 break;
 859         }
 860
 861         azx_writew(chip, HSW_EM4, bclk_m);
 862         azx_writew(chip, HSW_EM5, bclk_n);
 863 }
 864
 865 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
 866 /*
 867  * power management
 868  */
 869 static int azx_suspend(struct device *dev)
 870 {
 871         struct snd_card *card = dev_get_drvdata(dev);
 872         struct azx *chip;
 873         struct hda_intel *hda;
 874         struct hdac_bus *bus;
 875
 876         if (!card)
 877                 return 0;
 878
 879         chip = card->private_data;
 880         hda = container_of(chip, struct hda_intel, chip);
 881         if (chip->disabled || hda->init_failed || !chip->running)
 882                 return 0;
 883
 884         bus = azx_bus(chip);
 885         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
 886         azx_clear_irq_pending(chip);
 887         azx_stop_chip(chip);
 888         azx_enter_link_reset(chip);
 889         if (bus->irq >= 0) {
 890                 free_irq(bus->irq, chip);
 891                 bus->irq = -1;
 892         }
 893
 894         if (chip->msi)
 895                 pci_disable_msi(chip->pci);
 896         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
 897                 && hda->need_i915_power)
 898                 snd_hdac_display_power(bus, false);
 899
 900         trace_azx_suspend(chip);
 901         return 0;
 902 }
 903
 904 static int azx_resume(struct device *dev)
 905 {
 906         struct pci_dev *pci = to_pci_dev(dev);
 907         struct snd_card *card = dev_get_drvdata(dev);
 908         struct azx *chip;
 909         struct hda_intel *hda;
 910
 911         if (!card)
 912                 return 0;
 913
 914         chip = card->private_data;
 915         hda = container_of(chip, struct hda_intel, chip);
 916         if (chip->disabled || hda->init_failed || !chip->running)
 917                 return 0;
 918
 919         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
 920                 && hda->need_i915_power) {
 921                 snd_hdac_display_power(azx_bus(chip), true);
 922                 haswell_set_bclk(hda);
 923         }
 924         if (chip->msi)
 925                 if (pci_enable_msi(pci) < 0)
 926                         chip->msi = 0;
 927         if (azx_acquire_irq(chip, 1) < 0)
 928                 return -EIO;
 929         azx_init_pci(chip);
 930
 931         hda_intel_init_chip(chip, true);
 932
 933         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
 934
 935         trace_azx_resume(chip);
 936         return 0;
 937 }
 938 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
 939
 940 #ifdef CONFIG_PM
 941 static int azx_runtime_suspend(struct device *dev)
 942 {
 943         struct snd_card *card = dev_get_drvdata(dev);
 944         struct azx *chip;
 945         struct hda_intel *hda;
 946
 947         if (!card)
 948                 return 0;
 949
 950         chip = card->private_data;
 951         hda = container_of(chip, struct hda_intel, chip);
 952         if (chip->disabled || hda->init_failed)
 953                 return 0;
 954
 955         if (!azx_has_pm_runtime(chip))
 956                 return 0;
 957
 958         /* enable controller wake up event */
 959         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
 960                   STATESTS_INT_MASK);
 961
 962         azx_stop_chip(chip);
 963         azx_enter_link_reset(chip);
 964         azx_clear_irq_pending(chip);
 965         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
 966                 && hda->need_i915_power)
 967                 snd_hdac_display_power(azx_bus(chip), false);
 968
 969         trace_azx_runtime_suspend(chip);
 970         return 0;
 971 }
 972
 973 static int azx_runtime_resume(struct device *dev)
 974 {
 975         struct snd_card *card = dev_get_drvdata(dev);
 976         struct azx *chip;
 977         struct hda_intel *hda;
 978         struct hdac_bus *bus;
 979         struct hda_codec *codec;
 980         int status;
 981
 982         if (!card)
 983                 return 0;
 984
 985         chip = card->private_data;
 986         hda = container_of(chip, struct hda_intel, chip);
 987         if (chip->disabled || hda->init_failed)
 988                 return 0;
 989
 990         if (!azx_has_pm_runtime(chip))
 991                 return 0;
 992
 993         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
 994                 bus = azx_bus(chip);
 995                 if (hda->need_i915_power) {
 996                         snd_hdac_display_power(bus, true);
 997                         haswell_set_bclk(hda);
 998                 } else {
 999                         /* toggle codec wakeup bit for STATESTS read */
1000                         snd_hdac_set_codec_wakeup(bus, true);
1001                         snd_hdac_set_codec_wakeup(bus, false);
1002                 }
1003         }
1004
1005         /* Read STATESTS before controller reset */
1006         status = azx_readw(chip, STATESTS);
1007
1008         azx_init_pci(chip);
1009         hda_intel_init_chip(chip, true);
1010
1011         if (status) {
1012                 list_for_each_codec(codec, &chip->bus)
1013                         if (status & (1 << codec->addr))
1014                                 schedule_delayed_work(&codec->jackpoll_work,
1015                                                       codec->jackpoll_interval);
1016         }
1017
1018         /* disable controller Wake Up event*/
1019         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1020                         ~STATESTS_INT_MASK);
1021
1022         trace_azx_runtime_resume(chip);
1023         return 0;
1024 }
1025
1026 static int azx_runtime_idle(struct device *dev)
1027 {
1028         struct snd_card *card = dev_get_drvdata(dev);
1029         struct azx *chip;
1030         struct hda_intel *hda;
1031
1032         if (!card)
1033                 return 0;
1034
1035         chip = card->private_data;
1036         hda = container_of(chip, struct hda_intel, chip);
1037         if (chip->disabled || hda->init_failed)
1038                 return 0;
1039
1040         if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1041             azx_bus(chip)->codec_powered || !chip->running)
1042                 return -EBUSY;
1043
1044         return 0;
1045 }
1046
1047 static const struct dev_pm_ops azx_pm = {
1048         SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1049         SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1050 };
1051
1052 #define AZX_PM_OPS      &azx_pm
1053 #else
1054 #define AZX_PM_OPS      NULL
1055 #endif /* CONFIG_PM */
1056
1057
1058 static int azx_probe_continue(struct azx *chip);
1059
1060 #ifdef SUPPORT_VGA_SWITCHEROO
1061 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1062
1063 static void azx_vs_set_state(struct pci_dev *pci,
1064                              enum vga_switcheroo_state state)
1065 {
1066         struct snd_card *card = pci_get_drvdata(pci);
1067         struct azx *chip = card->private_data;
1068         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1069         bool disabled;
1070
1071         wait_for_completion(&hda->probe_wait);
1072         if (hda->init_failed)
1073                 return;
1074
1075         disabled = (state == VGA_SWITCHEROO_OFF);
1076         if (chip->disabled == disabled)
1077                 return;
1078
1079         if (!hda->probe_continued) {
1080                 chip->disabled = disabled;
1081                 if (!disabled) {
1082                         dev_info(chip->card->dev,
1083                                  "Start delayed initialization\n");
1084                         if (azx_probe_continue(chip) < 0) {
1085                                 dev_err(chip->card->dev, "initialization error\n");
1086                                 hda->init_failed = true;
1087                         }
1088                 }
1089         } else {
1090                 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1091                          disabled ? "Disabling" : "Enabling");
1092                 if (disabled) {
1093                         pm_runtime_put_sync_suspend(card->dev);
1094                         azx_suspend(card->dev);
1095                         /* when we get suspended by vga_switcheroo we end up in D3cold,
1096                          * however we have no ACPI handle, so pci/acpi can't put us there,
1097                          * put ourselves there */
1098                         pci->current_state = PCI_D3cold;
1099                         chip->disabled = true;
1100                         if (snd_hda_lock_devices(&chip->bus))
1101                                 dev_warn(chip->card->dev,
1102                                          "Cannot lock devices!\n");
1103                 } else {
1104                         snd_hda_unlock_devices(&chip->bus);
1105                         pm_runtime_get_noresume(card->dev);
1106                         chip->disabled = false;
1107                         azx_resume(card->dev);
1108                 }
1109         }
1110 }
1111
1112 static bool azx_vs_can_switch(struct pci_dev *pci)
1113 {
1114         struct snd_card *card = pci_get_drvdata(pci);
1115         struct azx *chip = card->private_data;
1116         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1117
1118         wait_for_completion(&hda->probe_wait);
1119         if (hda->init_failed)
1120                 return false;
1121         if (chip->disabled || !hda->probe_continued)
1122                 return true;
1123         if (snd_hda_lock_devices(&chip->bus))
1124                 return false;
1125         snd_hda_unlock_devices(&chip->bus);
1126         return true;
1127 }
1128
1129 static void init_vga_switcheroo(struct azx *chip)
1130 {
1131         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1132         struct pci_dev *p = get_bound_vga(chip->pci);
1133         if (p) {
1134                 dev_info(chip->card->dev,
1135                          "Handle vga_switcheroo audio client\n");
1136                 hda->use_vga_switcheroo = 1;
1137                 pci_dev_put(p);
1138         }
1139 }
1140
1141 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1142         .set_gpu_state = azx_vs_set_state,
1143         .can_switch = azx_vs_can_switch,
1144 };
1145
1146 static int register_vga_switcheroo(struct azx *chip)
1147 {
1148         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1149         int err;
1150
1151         if (!hda->use_vga_switcheroo)
1152                 return 0;
1153         /* FIXME: currently only handling DIS controller
1154          * is there any machine with two switchable HDMI audio controllers?
1155          */
1156         err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
1157                                                    VGA_SWITCHEROO_DIS);
1158         if (err < 0)
1159                 return err;
1160         hda->vga_switcheroo_registered = 1;
1161
1162         /* register as an optimus hdmi audio power domain */
1163         vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
1164                                                          &hda->hdmi_pm_domain);
1165         return 0;
1166 }
1167 #else
1168 #define init_vga_switcheroo(chip)               /* NOP */
1169 #define register_vga_switcheroo(chip)           0
1170 #define check_hdmi_disabled(pci)        false
1171 #endif /* SUPPORT_VGA_SWITCHER */
1172
1173 /*
1174  * destructor
1175  */
1176 static int azx_free(struct azx *chip)
1177 {
1178         struct pci_dev *pci = chip->pci;
1179         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1180         struct hdac_bus *bus = azx_bus(chip);
1181
1182         if (azx_has_pm_runtime(chip) && chip->running)
1183                 pm_runtime_get_noresume(&pci->dev);
1184
1185         azx_del_card_list(chip);
1186
1187         hda->init_failed = 1; /* to be sure */
1188         complete_all(&hda->probe_wait);
1189
1190         if (use_vga_switcheroo(hda)) {
1191                 if (chip->disabled && hda->probe_continued)
1192                         snd_hda_unlock_devices(&chip->bus);
1193                 if (hda->vga_switcheroo_registered)
1194                         vga_switcheroo_unregister_client(chip->pci);
1195         }
1196
1197         if (bus->chip_init) {
1198                 azx_clear_irq_pending(chip);
1199                 azx_stop_all_streams(chip);
1200                 azx_stop_chip(chip);
1201         }
1202
1203         if (bus->irq >= 0)
1204                 free_irq(bus->irq, (void*)chip);
1205         if (chip->msi)
1206                 pci_disable_msi(chip->pci);
1207         iounmap(bus->remap_addr);
1208
1209         azx_free_stream_pages(chip);
1210         azx_free_streams(chip);
1211         snd_hdac_bus_exit(bus);
1212
1213         if (chip->region_requested)
1214                 pci_release_regions(chip->pci);
1215
1216         pci_disable_device(chip->pci);
1217 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1218         release_firmware(chip->fw);
1219 #endif
1220
1221         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1222                 if (hda->need_i915_power)
1223                         snd_hdac_display_power(bus, false);
1224                 snd_hdac_i915_exit(bus);
1225         }
1226         kfree(hda);
1227
1228         return 0;
1229 }
1230
1231 static int azx_dev_disconnect(struct snd_device *device)
1232 {
1233         struct azx *chip = device->device_data;
1234
1235         chip->bus.shutdown = 1;
1236         return 0;
1237 }
1238
1239 static int azx_dev_free(struct snd_device *device)
1240 {
1241         return azx_free(device->device_data);
1242 }
1243
1244 #ifdef SUPPORT_VGA_SWITCHEROO
1245 /*
1246  * Check of disabled HDMI controller by vga_switcheroo
1247  */
1248 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1249 {
1250         struct pci_dev *p;
1251
1252         /* check only discrete GPU */
1253         switch (pci->vendor) {
1254         case PCI_VENDOR_ID_ATI:
1255         case PCI_VENDOR_ID_AMD:
1256         case PCI_VENDOR_ID_NVIDIA:
1257                 if (pci->devfn == 1) {
1258                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1259                                                         pci->bus->number, 0);
1260                         if (p) {
1261                                 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1262                                         return p;
1263                                 pci_dev_put(p);
1264                         }
1265                 }
1266                 break;
1267         }
1268         return NULL;
1269 }
1270
1271 static bool check_hdmi_disabled(struct pci_dev *pci)
1272 {
1273         bool vga_inactive = false;
1274         struct pci_dev *p = get_bound_vga(pci);
1275
1276         if (p) {
1277                 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1278                         vga_inactive = true;
1279                 pci_dev_put(p);
1280         }
1281         return vga_inactive;
1282 }
1283 #endif /* SUPPORT_VGA_SWITCHEROO */
1284
1285 /*
1286  * white/black-listing for position_fix
1287  */
1288 static struct snd_pci_quirk position_fix_list[] = {
1289         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1290         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1291         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1292         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1293         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1294         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1295         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1296         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1297         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1298         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1299         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1300         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1301         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1302         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1303         {}
1304 };
1305
1306 static int check_position_fix(struct azx *chip, int fix)
1307 {
1308         const struct snd_pci_quirk *q;
1309
1310         switch (fix) {
1311         case POS_FIX_AUTO:
1312         case POS_FIX_LPIB:
1313         case POS_FIX_POSBUF:
1314         case POS_FIX_VIACOMBO:
1315         case POS_FIX_COMBO:
1316                 return fix;
1317         }
1318
1319         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1320         if (q) {
1321                 dev_info(chip->card->dev,
1322                          "position_fix set to %d for device %04x:%04x\n",
1323                          q->value, q->subvendor, q->subdevice);
1324                 return q->value;
1325         }
1326
1327         /* Check VIA/ATI HD Audio Controller exist */
1328         if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
1329                 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1330                 return POS_FIX_VIACOMBO;
1331         }
1332         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1333                 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1334                 return POS_FIX_LPIB;
1335         }
1336         return POS_FIX_AUTO;
1337 }
1338
1339 static void assign_position_fix(struct azx *chip, int fix)
1340 {
1341         static azx_get_pos_callback_t callbacks[] = {
1342                 [POS_FIX_AUTO] = NULL,
1343                 [POS_FIX_LPIB] = azx_get_pos_lpib,
1344                 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1345                 [POS_FIX_VIACOMBO] = azx_via_get_position,
1346                 [POS_FIX_COMBO] = azx_get_pos_lpib,
1347         };
1348
1349         chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1350
1351         /* combo mode uses LPIB only for playback */
1352         if (fix == POS_FIX_COMBO)
1353                 chip->get_position[1] = NULL;
1354
1355         if (fix == POS_FIX_POSBUF &&
1356             (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1357                 chip->get_delay[0] = chip->get_delay[1] =
1358                         azx_get_delay_from_lpib;
1359         }
1360
1361 }
1362
1363 /*
1364  * black-lists for probe_mask
1365  */
1366 static struct snd_pci_quirk probe_mask_list[] = {
1367         /* Thinkpad often breaks the controller communication when accessing
1368          * to the non-working (or non-existing) modem codec slot.
1369          */
1370         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1371         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1372         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1373         /* broken BIOS */
1374         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1375         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1376         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1377         /* forced codec slots */
1378         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1379         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1380         /* WinFast VP200 H (Teradici) user reported broken communication */
1381         SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1382         {}
1383 };
1384
1385 #define AZX_FORCE_CODEC_MASK    0x100
1386
1387 static void check_probe_mask(struct azx *chip, int dev)
1388 {
1389         const struct snd_pci_quirk *q;
1390
1391         chip->codec_probe_mask = probe_mask[dev];
1392         if (chip->codec_probe_mask == -1) {
1393                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1394                 if (q) {
1395                         dev_info(chip->card->dev,
1396                                  "probe_mask set to 0x%x for device %04x:%04x\n",
1397                                  q->value, q->subvendor, q->subdevice);
1398                         chip->codec_probe_mask = q->value;
1399                 }
1400         }
1401
1402         /* check forced option */
1403         if (chip->codec_probe_mask != -1 &&
1404             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1405                 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1406                 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1407                          (int)azx_bus(chip)->codec_mask);
1408         }
1409 }
1410
1411 /*
1412  * white/black-list for enable_msi
1413  */
1414 static struct snd_pci_quirk msi_black_list[] = {
1415         SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1416         SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1417         SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1418         SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1419         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1420         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1421         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1422         SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1423         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1424         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1425         {}
1426 };
1427
1428 static void check_msi(struct azx *chip)
1429 {
1430         const struct snd_pci_quirk *q;
1431
1432         if (enable_msi >= 0) {
1433                 chip->msi = !!enable_msi;
1434                 return;
1435         }
1436         chip->msi = 1;  /* enable MSI as default */
1437         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1438         if (q) {
1439                 dev_info(chip->card->dev,
1440                          "msi for device %04x:%04x set to %d\n",
1441                          q->subvendor, q->subdevice, q->value);
1442                 chip->msi = q->value;
1443                 return;
1444         }
1445
1446         /* NVidia chipsets seem to cause troubles with MSI */
1447         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1448                 dev_info(chip->card->dev, "Disabling MSI\n");
1449                 chip->msi = 0;
1450         }
1451 }
1452
1453 /* check the snoop mode availability */
1454 static void azx_check_snoop_available(struct azx *chip)
1455 {
1456         int snoop = hda_snoop;
1457
1458         if (snoop >= 0) {
1459                 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1460                          snoop ? "snoop" : "non-snoop");
1461                 chip->snoop = snoop;
1462                 return;
1463         }
1464
1465         snoop = true;
1466         if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1467             chip->driver_type == AZX_DRIVER_VIA) {
1468                 /* force to non-snoop mode for a new VIA controller
1469                  * when BIOS is set
1470                  */
1471                 u8 val;
1472                 pci_read_config_byte(chip->pci, 0x42, &val);
1473                 if (!(val & 0x80) && chip->pci->revision == 0x30)
1474                         snoop = false;
1475         }
1476
1477         if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1478                 snoop = false;
1479
1480         chip->snoop = snoop;
1481         if (!snoop)
1482                 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1483 }
1484
1485 static void azx_probe_work(struct work_struct *work)
1486 {
1487         struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1488         azx_probe_continue(&hda->chip);
1489 }
1490
1491 /*
1492  * constructor
1493  */
1494 static const struct hdac_io_ops pci_hda_io_ops;
1495 static const struct hda_controller_ops pci_hda_ops;
1496
1497 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1498                       int dev, unsigned int driver_caps,
1499                       struct azx **rchip)
1500 {
1501         static struct snd_device_ops ops = {
1502                 .dev_disconnect = azx_dev_disconnect,
1503                 .dev_free = azx_dev_free,
1504         };
1505         struct hda_intel *hda;
1506         struct azx *chip;
1507         int err;
1508
1509         *rchip = NULL;
1510
1511         err = pci_enable_device(pci);
1512         if (err < 0)
1513                 return err;
1514
1515         hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1516         if (!hda) {
1517                 pci_disable_device(pci);
1518                 return -ENOMEM;
1519         }
1520
1521         chip = &hda->chip;
1522         mutex_init(&chip->open_mutex);
1523         chip->card = card;
1524         chip->pci = pci;
1525         chip->ops = &pci_hda_ops;
1526         chip->driver_caps = driver_caps;
1527         chip->driver_type = driver_caps & 0xff;
1528         check_msi(chip);
1529         chip->dev_index = dev;
1530         chip->jackpoll_ms = jackpoll_ms;
1531         INIT_LIST_HEAD(&chip->pcm_list);
1532         INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1533         INIT_LIST_HEAD(&hda->list);
1534         init_vga_switcheroo(chip);
1535         init_completion(&hda->probe_wait);
1536
1537         assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1538
1539         check_probe_mask(chip, dev);
1540
1541         chip->single_cmd = single_cmd;
1542         azx_check_snoop_available(chip);
1543
1544         if (bdl_pos_adj[dev] < 0) {
1545                 switch (chip->driver_type) {
1546                 case AZX_DRIVER_ICH:
1547                 case AZX_DRIVER_PCH:
1548                         bdl_pos_adj[dev] = 1;
1549                         break;
1550                 default:
1551                         bdl_pos_adj[dev] = 32;
1552                         break;
1553                 }
1554         }
1555         chip->bdl_pos_adj = bdl_pos_adj;
1556
1557         err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1558         if (err < 0) {
1559                 kfree(hda);
1560                 pci_disable_device(pci);
1561                 return err;
1562         }
1563
1564         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1565         if (err < 0) {
1566                 dev_err(card->dev, "Error creating device [card]!\n");
1567                 azx_free(chip);
1568                 return err;
1569         }
1570
1571         /* continue probing in work context as may trigger request module */
1572         INIT_WORK(&hda->probe_work, azx_probe_work);
1573
1574         *rchip = chip;
1575
1576         return 0;
1577 }
1578
1579 static int azx_first_init(struct azx *chip)
1580 {
1581         int dev = chip->dev_index;
1582         struct pci_dev *pci = chip->pci;
1583         struct snd_card *card = chip->card;
1584         struct hdac_bus *bus = azx_bus(chip);
1585         int err;
1586         unsigned short gcap;
1587         unsigned int dma_bits = 64;
1588
1589 #if BITS_PER_LONG != 64
1590         /* Fix up base address on ULI M5461 */
1591         if (chip->driver_type == AZX_DRIVER_ULI) {
1592                 u16 tmp3;
1593                 pci_read_config_word(pci, 0x40, &tmp3);
1594                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1595                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1596         }
1597 #endif
1598
1599         err = pci_request_regions(pci, "ICH HD audio");
1600         if (err < 0)
1601                 return err;
1602         chip->region_requested = 1;
1603
1604         bus->addr = pci_resource_start(pci, 0);
1605         bus->remap_addr = pci_ioremap_bar(pci, 0);
1606         if (bus->remap_addr == NULL) {
1607                 dev_err(card->dev, "ioremap error\n");
1608                 return -ENXIO;
1609         }
1610
1611         if (chip->msi) {
1612                 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1613                         dev_dbg(card->dev, "Disabling 64bit MSI\n");
1614                         pci->no_64bit_msi = true;
1615                 }
1616                 if (pci_enable_msi(pci) < 0)
1617                         chip->msi = 0;
1618         }
1619
1620         if (azx_acquire_irq(chip, 0) < 0)
1621                 return -EBUSY;
1622
1623         pci_set_master(pci);
1624         synchronize_irq(bus->irq);
1625
1626         gcap = azx_readw(chip, GCAP);
1627         dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1628
1629         /* AMD devices support 40 or 48bit DMA, take the safe one */
1630         if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1631                 dma_bits = 40;
1632
1633         /* disable SB600 64bit support for safety */
1634         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1635                 struct pci_dev *p_smbus;
1636                 dma_bits = 40;
1637                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1638                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1639                                          NULL);
1640                 if (p_smbus) {
1641                         if (p_smbus->revision < 0x30)
1642                                 gcap &= ~AZX_GCAP_64OK;
1643                         pci_dev_put(p_smbus);
1644                 }
1645         }
1646
1647         /* disable 64bit DMA address on some devices */
1648         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1649                 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1650                 gcap &= ~AZX_GCAP_64OK;
1651         }
1652
1653         /* disable buffer size rounding to 128-byte multiples if supported */
1654         if (align_buffer_size >= 0)
1655                 chip->align_buffer_size = !!align_buffer_size;
1656         else {
1657                 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1658                         chip->align_buffer_size = 0;
1659                 else
1660                         chip->align_buffer_size = 1;
1661         }
1662
1663         /* allow 64bit DMA address if supported by H/W */
1664         if (!(gcap & AZX_GCAP_64OK))
1665                 dma_bits = 32;
1666         if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1667                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
1668         } else {
1669                 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1670                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
1671         }
1672
1673         /* read number of streams from GCAP register instead of using
1674          * hardcoded value
1675          */
1676         chip->capture_streams = (gcap >> 8) & 0x0f;
1677         chip->playback_streams = (gcap >> 12) & 0x0f;
1678         if (!chip->playback_streams && !chip->capture_streams) {
1679                 /* gcap didn't give any info, switching to old method */
1680
1681                 switch (chip->driver_type) {
1682                 case AZX_DRIVER_ULI:
1683                         chip->playback_streams = ULI_NUM_PLAYBACK;
1684                         chip->capture_streams = ULI_NUM_CAPTURE;
1685                         break;
1686                 case AZX_DRIVER_ATIHDMI:
1687                 case AZX_DRIVER_ATIHDMI_NS:
1688                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1689                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1690                         break;
1691                 case AZX_DRIVER_GENERIC:
1692                 default:
1693                         chip->playback_streams = ICH6_NUM_PLAYBACK;
1694                         chip->capture_streams = ICH6_NUM_CAPTURE;
1695                         break;
1696                 }
1697         }
1698         chip->capture_index_offset = 0;
1699         chip->playback_index_offset = chip->capture_streams;
1700         chip->num_streams = chip->playback_streams + chip->capture_streams;
1701
1702         /* initialize streams */
1703         err = azx_init_streams(chip);
1704         if (err < 0)
1705                 return err;
1706
1707         err = azx_alloc_stream_pages(chip);
1708         if (err < 0)
1709                 return err;
1710
1711         /* initialize chip */
1712         azx_init_pci(chip);
1713
1714         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1715                 struct hda_intel *hda;
1716
1717                 hda = container_of(chip, struct hda_intel, chip);
1718                 haswell_set_bclk(hda);
1719         }
1720
1721         hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1722
1723         /* codec detection */
1724         if (!azx_bus(chip)->codec_mask) {
1725                 dev_err(card->dev, "no codecs found!\n");
1726                 return -ENODEV;
1727         }
1728
1729         strcpy(card->driver, "HDA-Intel");
1730         strlcpy(card->shortname, driver_short_names[chip->driver_type],
1731                 sizeof(card->shortname));
1732         snprintf(card->longname, sizeof(card->longname),
1733                  "%s at 0x%lx irq %i",
1734                  card->shortname, bus->addr, bus->irq);
1735
1736         return 0;
1737 }
1738
1739 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1740 /* callback from request_firmware_nowait() */
1741 static void azx_firmware_cb(const struct firmware *fw, void *context)
1742 {
1743         struct snd_card *card = context;
1744         struct azx *chip = card->private_data;
1745         struct pci_dev *pci = chip->pci;
1746
1747         if (!fw) {
1748                 dev_err(card->dev, "Cannot load firmware, aborting\n");
1749                 goto error;
1750         }
1751
1752         chip->fw = fw;
1753         if (!chip->disabled) {
1754                 /* continue probing */
1755                 if (azx_probe_continue(chip))
1756                         goto error;
1757         }
1758         return; /* OK */
1759
1760  error:
1761         snd_card_free(card);
1762         pci_set_drvdata(pci, NULL);
1763 }
1764 #endif
1765
1766 /*
1767  * HDA controller ops.
1768  */
1769
1770 /* PCI register access. */
1771 static void pci_azx_writel(u32 value, u32 __iomem *addr)
1772 {
1773         writel(value, addr);
1774 }
1775
1776 static u32 pci_azx_readl(u32 __iomem *addr)
1777 {
1778         return readl(addr);
1779 }
1780
1781 static void pci_azx_writew(u16 value, u16 __iomem *addr)
1782 {
1783         writew(value, addr);
1784 }
1785
1786 static u16 pci_azx_readw(u16 __iomem *addr)
1787 {
1788         return readw(addr);
1789 }
1790
1791 static void pci_azx_writeb(u8 value, u8 __iomem *addr)
1792 {
1793         writeb(value, addr);
1794 }
1795
1796 static u8 pci_azx_readb(u8 __iomem *addr)
1797 {
1798         return readb(addr);
1799 }
1800
1801 static int disable_msi_reset_irq(struct azx *chip)
1802 {
1803         struct hdac_bus *bus = azx_bus(chip);
1804         int err;
1805
1806         free_irq(bus->irq, chip);
1807         bus->irq = -1;
1808         pci_disable_msi(chip->pci);
1809         chip->msi = 0;
1810         err = azx_acquire_irq(chip, 1);
1811         if (err < 0)
1812                 return err;
1813
1814         return 0;
1815 }
1816
1817 /* DMA page allocation helpers.  */
1818 static int dma_alloc_pages(struct hdac_bus *bus,
1819                            int type,
1820                            size_t size,
1821                            struct snd_dma_buffer *buf)
1822 {
1823         struct azx *chip = bus_to_azx(bus);
1824         int err;
1825
1826         err = snd_dma_alloc_pages(type,
1827                                   bus->dev,
1828                                   size, buf);
1829         if (err < 0)
1830                 return err;
1831         mark_pages_wc(chip, buf, true);
1832         return 0;
1833 }
1834
1835 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
1836 {
1837         struct azx *chip = bus_to_azx(bus);
1838
1839         mark_pages_wc(chip, buf, false);
1840         snd_dma_free_pages(buf);
1841 }
1842
1843 static int substream_alloc_pages(struct azx *chip,
1844                                  struct snd_pcm_substream *substream,
1845                                  size_t size)
1846 {
1847         struct azx_dev *azx_dev = get_azx_dev(substream);
1848         int ret;
1849
1850         mark_runtime_wc(chip, azx_dev, substream, false);
1851         ret = snd_pcm_lib_malloc_pages(substream, size);
1852         if (ret < 0)
1853                 return ret;
1854         mark_runtime_wc(chip, azx_dev, substream, true);
1855         return 0;
1856 }
1857
1858 static int substream_free_pages(struct azx *chip,
1859                                 struct snd_pcm_substream *substream)
1860 {
1861         struct azx_dev *azx_dev = get_azx_dev(substream);
1862         mark_runtime_wc(chip, azx_dev, substream, false);
1863         return snd_pcm_lib_free_pages(substream);
1864 }
1865
1866 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
1867                              struct vm_area_struct *area)
1868 {
1869 #ifdef CONFIG_X86
1870         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1871         struct azx *chip = apcm->chip;
1872         if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA)
1873                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
1874 #endif
1875 }
1876
1877 static const struct hdac_io_ops pci_hda_io_ops = {
1878         .reg_writel = pci_azx_writel,
1879         .reg_readl = pci_azx_readl,
1880         .reg_writew = pci_azx_writew,
1881         .reg_readw = pci_azx_readw,
1882         .reg_writeb = pci_azx_writeb,
1883         .reg_readb = pci_azx_readb,
1884         .dma_alloc_pages = dma_alloc_pages,
1885         .dma_free_pages = dma_free_pages,
1886 };
1887
1888 static const struct hda_controller_ops pci_hda_ops = {
1889         .disable_msi_reset_irq = disable_msi_reset_irq,
1890         .substream_alloc_pages = substream_alloc_pages,
1891         .substream_free_pages = substream_free_pages,
1892         .pcm_mmap_prepare = pcm_mmap_prepare,
1893         .position_check = azx_position_check,
1894         .link_power = azx_intel_link_power,
1895 };
1896
1897 static int azx_probe(struct pci_dev *pci,
1898                      const struct pci_device_id *pci_id)
1899 {
1900         static int dev;
1901         struct snd_card *card;
1902         struct hda_intel *hda;
1903         struct azx *chip;
1904         bool schedule_probe;
1905         int err;
1906
1907         if (dev >= SNDRV_CARDS)
1908                 return -ENODEV;
1909         if (!enable[dev]) {
1910                 dev++;
1911                 return -ENOENT;
1912         }
1913
1914         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1915                            0, &card);
1916         if (err < 0) {
1917                 dev_err(&pci->dev, "Error creating card!\n");
1918                 return err;
1919         }
1920
1921         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
1922         if (err < 0)
1923                 goto out_free;
1924         card->private_data = chip;
1925         hda = container_of(chip, struct hda_intel, chip);
1926
1927         pci_set_drvdata(pci, card);
1928
1929         err = register_vga_switcheroo(chip);
1930         if (err < 0) {
1931                 dev_err(card->dev, "Error registering vga_switcheroo client\n");
1932                 goto out_free;
1933         }
1934
1935         if (check_hdmi_disabled(pci)) {
1936                 dev_info(card->dev, "VGA controller is disabled\n");
1937                 dev_info(card->dev, "Delaying initialization\n");
1938                 chip->disabled = true;
1939         }
1940
1941         schedule_probe = !chip->disabled;
1942
1943 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1944         if (patch[dev] && *patch[dev]) {
1945                 dev_info(card->dev, "Applying patch firmware '%s'\n",
1946                          patch[dev]);
1947                 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
1948                                               &pci->dev, GFP_KERNEL, card,
1949                                               azx_firmware_cb);
1950                 if (err < 0)
1951                         goto out_free;
1952                 schedule_probe = false; /* continued in azx_firmware_cb() */
1953         }
1954 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
1955
1956 #ifndef CONFIG_SND_HDA_I915
1957         if (CONTROLLER_IN_GPU(pci))
1958                 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
1959 #endif
1960
1961         if (schedule_probe)
1962                 schedule_work(&hda->probe_work);
1963
1964         dev++;
1965         if (chip->disabled)
1966                 complete_all(&hda->probe_wait);
1967         return 0;
1968
1969 out_free:
1970         snd_card_free(card);
1971         return err;
1972 }
1973
1974 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1975 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
1976         [AZX_DRIVER_NVIDIA] = 8,
1977         [AZX_DRIVER_TERA] = 1,
1978 };
1979
1980 static int azx_probe_continue(struct azx *chip)
1981 {
1982         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1983         struct hdac_bus *bus = azx_bus(chip);
1984         struct pci_dev *pci = chip->pci;
1985         int dev = chip->dev_index;
1986         int err;
1987
1988         hda->probe_continued = 1;
1989
1990         /* Request display power well for the HDA controller or codec. For
1991          * Haswell/Broadwell, both the display HDA controller and codec need
1992          * this power. For other platforms, like Baytrail/Braswell, only the
1993          * display codec needs the power and it can be released after probe.
1994          */
1995         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1996                 /* HSW/BDW controllers need this power */
1997                 if (CONTROLLER_IN_GPU(pci))
1998                         hda->need_i915_power = 1;
1999
2000                 err = snd_hdac_i915_init(bus);
2001                 if (err < 0) {
2002                         /* if the controller is bound only with HDMI/DP
2003                          * (for HSW and BDW), we need to abort the probe;
2004                          * for other chips, still continue probing as other
2005                          * codecs can be on the same link.
2006                          */
2007                         if (CONTROLLER_IN_GPU(pci))
2008                                 goto out_free;
2009                         else
2010                                 goto skip_i915;
2011                 }
2012
2013                 err = snd_hdac_display_power(bus, true);
2014                 if (err < 0) {
2015                         dev_err(chip->card->dev,
2016                                 "Cannot turn on display power on i915\n");
2017                         goto i915_power_fail;
2018                 }
2019         }
2020
2021  skip_i915:
2022         err = azx_first_init(chip);
2023         if (err < 0)
2024                 goto out_free;
2025
2026 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2027         chip->beep_mode = beep_mode[dev];
2028 #endif
2029
2030         /* create codec instances */
2031         err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2032         if (err < 0)
2033                 goto out_free;
2034
2035 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2036         if (chip->fw) {
2037                 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2038                                          chip->fw->data);
2039                 if (err < 0)
2040                         goto out_free;
2041 #ifndef CONFIG_PM
2042                 release_firmware(chip->fw); /* no longer needed */
2043                 chip->fw = NULL;
2044 #endif
2045         }
2046 #endif
2047         if ((probe_only[dev] & 1) == 0) {
2048                 err = azx_codec_configure(chip);
2049                 if (err < 0)
2050                         goto out_free;
2051         }
2052
2053         err = snd_card_register(chip->card);
2054         if (err < 0)
2055                 goto out_free;
2056
2057         chip->running = 1;
2058         azx_add_card_list(chip);
2059         snd_hda_set_power_save(&chip->bus, power_save * 1000);
2060         if (azx_has_pm_runtime(chip) || hda->use_vga_switcheroo)
2061                 pm_runtime_put_noidle(&pci->dev);
2062
2063 out_free:
2064         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
2065                 && !hda->need_i915_power)
2066                 snd_hdac_display_power(bus, false);
2067
2068 i915_power_fail:
2069         if (err < 0)
2070                 hda->init_failed = 1;
2071         complete_all(&hda->probe_wait);
2072         return err;
2073 }
2074
2075 static void azx_remove(struct pci_dev *pci)
2076 {
2077         struct snd_card *card = pci_get_drvdata(pci);
2078
2079         if (card)
2080                 snd_card_free(card);
2081 }
2082
2083 static void azx_shutdown(struct pci_dev *pci)
2084 {
2085         struct snd_card *card = pci_get_drvdata(pci);
2086         struct azx *chip;
2087
2088         if (!card)
2089                 return;
2090         chip = card->private_data;
2091         if (chip && chip->running)
2092                 azx_stop_chip(chip);
2093 }
2094
2095 /* PCI IDs */
2096 static const struct pci_device_id azx_ids[] = {
2097         /* CPT */
2098         { PCI_DEVICE(0x8086, 0x1c20),
2099           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2100         /* PBG */
2101         { PCI_DEVICE(0x8086, 0x1d20),
2102           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2103         /* Panther Point */
2104         { PCI_DEVICE(0x8086, 0x1e20),
2105           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2106         /* Lynx Point */
2107         { PCI_DEVICE(0x8086, 0x8c20),
2108           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2109         /* 9 Series */
2110         { PCI_DEVICE(0x8086, 0x8ca0),
2111           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2112         /* Wellsburg */
2113         { PCI_DEVICE(0x8086, 0x8d20),
2114           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2115         { PCI_DEVICE(0x8086, 0x8d21),
2116           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2117         /* Lewisburg */
2118         { PCI_DEVICE(0x8086, 0xa1f0),
2119           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2120         { PCI_DEVICE(0x8086, 0xa270),
2121           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2122         /* Lynx Point-LP */
2123         { PCI_DEVICE(0x8086, 0x9c20),
2124           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2125         /* Lynx Point-LP */
2126         { PCI_DEVICE(0x8086, 0x9c21),
2127           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2128         /* Wildcat Point-LP */
2129         { PCI_DEVICE(0x8086, 0x9ca0),
2130           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2131         /* Sunrise Point */
2132         { PCI_DEVICE(0x8086, 0xa170),
2133           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2134         /* Sunrise Point-LP */
2135         { PCI_DEVICE(0x8086, 0x9d70),
2136           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2137         /* Broxton-P(Apollolake) */
2138         { PCI_DEVICE(0x8086, 0x5a98),
2139           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BROXTON },
2140         /* Haswell */
2141         { PCI_DEVICE(0x8086, 0x0a0c),
2142           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2143         { PCI_DEVICE(0x8086, 0x0c0c),
2144           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2145         { PCI_DEVICE(0x8086, 0x0d0c),
2146           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2147         /* Broadwell */
2148         { PCI_DEVICE(0x8086, 0x160c),
2149           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2150         /* 5 Series/3400 */
2151         { PCI_DEVICE(0x8086, 0x3b56),
2152           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2153         /* Poulsbo */
2154         { PCI_DEVICE(0x8086, 0x811b),
2155           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2156         /* Oaktrail */
2157         { PCI_DEVICE(0x8086, 0x080a),
2158           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2159         /* BayTrail */
2160         { PCI_DEVICE(0x8086, 0x0f04),
2161           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2162         /* Braswell */
2163         { PCI_DEVICE(0x8086, 0x2284),
2164           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2165         /* ICH6 */
2166         { PCI_DEVICE(0x8086, 0x2668),
2167           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2168         /* ICH7 */
2169         { PCI_DEVICE(0x8086, 0x27d8),
2170           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2171         /* ESB2 */
2172         { PCI_DEVICE(0x8086, 0x269a),
2173           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2174         /* ICH8 */
2175         { PCI_DEVICE(0x8086, 0x284b),
2176           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2177         /* ICH9 */
2178         { PCI_DEVICE(0x8086, 0x293e),
2179           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2180         /* ICH9 */
2181         { PCI_DEVICE(0x8086, 0x293f),
2182           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2183         /* ICH10 */
2184         { PCI_DEVICE(0x8086, 0x3a3e),
2185           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2186         /* ICH10 */
2187         { PCI_DEVICE(0x8086, 0x3a6e),
2188           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2189         /* Generic Intel */
2190         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2191           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2192           .class_mask = 0xffffff,
2193           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2194         /* ATI SB 450/600/700/800/900 */
2195         { PCI_DEVICE(0x1002, 0x437b),
2196           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2197         { PCI_DEVICE(0x1002, 0x4383),
2198           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2199         /* AMD Hudson */
2200         { PCI_DEVICE(0x1022, 0x780d),
2201           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2202         /* ATI HDMI */
2203         { PCI_DEVICE(0x1002, 0x1308),
2204           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2205         { PCI_DEVICE(0x1002, 0x157a),
2206           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2207         { PCI_DEVICE(0x1002, 0x793b),
2208           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2209         { PCI_DEVICE(0x1002, 0x7919),
2210           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2211         { PCI_DEVICE(0x1002, 0x960f),
2212           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2213         { PCI_DEVICE(0x1002, 0x970f),
2214           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2215         { PCI_DEVICE(0x1002, 0x9840),
2216           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2217         { PCI_DEVICE(0x1002, 0xaa00),
2218           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2219         { PCI_DEVICE(0x1002, 0xaa08),
2220           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2221         { PCI_DEVICE(0x1002, 0xaa10),
2222           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2223         { PCI_DEVICE(0x1002, 0xaa18),
2224           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2225         { PCI_DEVICE(0x1002, 0xaa20),
2226           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2227         { PCI_DEVICE(0x1002, 0xaa28),
2228           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2229         { PCI_DEVICE(0x1002, 0xaa30),
2230           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2231         { PCI_DEVICE(0x1002, 0xaa38),
2232           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2233         { PCI_DEVICE(0x1002, 0xaa40),
2234           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2235         { PCI_DEVICE(0x1002, 0xaa48),
2236           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2237         { PCI_DEVICE(0x1002, 0xaa50),
2238           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2239         { PCI_DEVICE(0x1002, 0xaa58),
2240           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2241         { PCI_DEVICE(0x1002, 0xaa60),
2242           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2243         { PCI_DEVICE(0x1002, 0xaa68),
2244           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2245         { PCI_DEVICE(0x1002, 0xaa80),
2246           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2247         { PCI_DEVICE(0x1002, 0xaa88),
2248           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2249         { PCI_DEVICE(0x1002, 0xaa90),
2250           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2251         { PCI_DEVICE(0x1002, 0xaa98),
2252           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2253         { PCI_DEVICE(0x1002, 0x9902),
2254           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2255         { PCI_DEVICE(0x1002, 0xaaa0),
2256           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2257         { PCI_DEVICE(0x1002, 0xaaa8),
2258           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2259         { PCI_DEVICE(0x1002, 0xaab0),
2260           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2261         { PCI_DEVICE(0x1002, 0xaac0),
2262           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2263         { PCI_DEVICE(0x1002, 0xaac8),
2264           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2265         { PCI_DEVICE(0x1002, 0xaad8),
2266           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2267         { PCI_DEVICE(0x1002, 0xaae8),
2268           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2269         /* VIA VT8251/VT8237A */
2270         { PCI_DEVICE(0x1106, 0x3288),
2271           .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
2272         /* VIA GFX VT7122/VX900 */
2273         { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2274         /* VIA GFX VT6122/VX11 */
2275         { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2276         /* SIS966 */
2277         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2278         /* ULI M5461 */
2279         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2280         /* NVIDIA MCP */
2281         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2282           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2283           .class_mask = 0xffffff,
2284           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2285         /* Teradici */
2286         { PCI_DEVICE(0x6549, 0x1200),
2287           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2288         { PCI_DEVICE(0x6549, 0x2200),
2289           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2290         /* Creative X-Fi (CA0110-IBG) */
2291         /* CTHDA chips */
2292         { PCI_DEVICE(0x1102, 0x0010),
2293           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2294         { PCI_DEVICE(0x1102, 0x0012),
2295           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2296 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2297         /* the following entry conflicts with snd-ctxfi driver,
2298          * as ctxfi driver mutates from HD-audio to native mode with
2299          * a special command sequence.
2300          */
2301         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2302           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2303           .class_mask = 0xffffff,
2304           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2305           AZX_DCAPS_NO_64BIT |
2306           AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
2307 #else
2308         /* this entry seems still valid -- i.e. without emu20kx chip */
2309         { PCI_DEVICE(0x1102, 0x0009),
2310           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2311           AZX_DCAPS_NO_64BIT |
2312           AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
2313 #endif
2314         /* CM8888 */
2315         { PCI_DEVICE(0x13f6, 0x5011),
2316           .driver_data = AZX_DRIVER_CMEDIA |
2317           AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2318         /* Vortex86MX */
2319         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2320         /* VMware HDAudio */
2321         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2322         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2323         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2324           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2325           .class_mask = 0xffffff,
2326           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2327         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2328           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2329           .class_mask = 0xffffff,
2330           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2331         { 0, }
2332 };
2333 MODULE_DEVICE_TABLE(pci, azx_ids);
2334
2335 /* pci_driver definition */
2336 static struct pci_driver azx_driver = {
2337         .name = KBUILD_MODNAME,
2338         .id_table = azx_ids,
2339         .probe = azx_probe,
2340         .remove = azx_remove,
2341         .shutdown = azx_shutdown,
2342         .driver = {
2343                 .pm = AZX_PM_OPS,
2344         },
2345 };
2346
2347 module_pci_driver(azx_driver);