drivers/staging/rdma/hfi1/verbs.c

   1 /*
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2015 Intel Corporation.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of version 2 of the GNU General Public License as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
  15  * WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * General Public License for more details.
  18  *
  19  * BSD LICENSE
  20  *
  21  * Copyright(c) 2015 Intel Corporation.
  22  *
  23  * Redistribution and use in source and binary forms, with or without
  24  * modification, are permitted provided that the following conditions
  25  * are met:
  26  *
  27  *  - Redistributions of source code must retain the above copyright
  28  *    notice, this list of conditions and the following disclaimer.
  29  *  - Redistributions in binary form must reproduce the above copyright
  30  *    notice, this list of conditions and the following disclaimer in
  31  *    the documentation and/or other materials provided with the
  32  *    distribution.
  33  *  - Neither the name of Intel Corporation nor the names of its
  34  *    contributors may be used to endorse or promote products derived
  35  *    from this software without specific prior written permission.
  36  *
  37  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  38  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  39  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  40  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  41  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  42  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  43  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  44  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  45  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  46  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  47  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  48  *
  49  */
  50
  51 #include <rdma/ib_mad.h>
  52 #include <rdma/ib_user_verbs.h>
  53 #include <linux/io.h>
  54 #include <linux/module.h>
  55 #include <linux/utsname.h>
  56 #include <linux/rculist.h>
  57 #include <linux/mm.h>
  58 #include <linux/random.h>
  59 #include <linux/vmalloc.h>
  60
  61 #include "hfi.h"
  62 #include "common.h"
  63 #include "device.h"
  64 #include "trace.h"
  65 #include "qp.h"
  66 #include "sdma.h"
  67
  68 unsigned int hfi1_lkey_table_size = 16;
  69 module_param_named(lkey_table_size, hfi1_lkey_table_size, uint,
  70                    S_IRUGO);
  71 MODULE_PARM_DESC(lkey_table_size,
  72                  "LKEY table size in bits (2^n, 1 <= n <= 23)");
  73
  74 static unsigned int hfi1_max_pds = 0xFFFF;
  75 module_param_named(max_pds, hfi1_max_pds, uint, S_IRUGO);
  76 MODULE_PARM_DESC(max_pds,
  77                  "Maximum number of protection domains to support");
  78
  79 static unsigned int hfi1_max_ahs = 0xFFFF;
  80 module_param_named(max_ahs, hfi1_max_ahs, uint, S_IRUGO);
  81 MODULE_PARM_DESC(max_ahs, "Maximum number of address handles to support");
  82
  83 unsigned int hfi1_max_cqes = 0x2FFFF;
  84 module_param_named(max_cqes, hfi1_max_cqes, uint, S_IRUGO);
  85 MODULE_PARM_DESC(max_cqes,
  86                  "Maximum number of completion queue entries to support");
  87
  88 unsigned int hfi1_max_cqs = 0x1FFFF;
  89 module_param_named(max_cqs, hfi1_max_cqs, uint, S_IRUGO);
  90 MODULE_PARM_DESC(max_cqs, "Maximum number of completion queues to support");
  91
  92 unsigned int hfi1_max_qp_wrs = 0x3FFF;
  93 module_param_named(max_qp_wrs, hfi1_max_qp_wrs, uint, S_IRUGO);
  94 MODULE_PARM_DESC(max_qp_wrs, "Maximum number of QP WRs to support");
  95
  96 unsigned int hfi1_max_qps = 16384;
  97 module_param_named(max_qps, hfi1_max_qps, uint, S_IRUGO);
  98 MODULE_PARM_DESC(max_qps, "Maximum number of QPs to support");
  99
 100 unsigned int hfi1_max_sges = 0x60;
 101 module_param_named(max_sges, hfi1_max_sges, uint, S_IRUGO);
 102 MODULE_PARM_DESC(max_sges, "Maximum number of SGEs to support");
 103
 104 unsigned int hfi1_max_mcast_grps = 16384;
 105 module_param_named(max_mcast_grps, hfi1_max_mcast_grps, uint, S_IRUGO);
 106 MODULE_PARM_DESC(max_mcast_grps,
 107                  "Maximum number of multicast groups to support");
 108
 109 unsigned int hfi1_max_mcast_qp_attached = 16;
 110 module_param_named(max_mcast_qp_attached, hfi1_max_mcast_qp_attached,
 111                    uint, S_IRUGO);
 112 MODULE_PARM_DESC(max_mcast_qp_attached,
 113                  "Maximum number of attached QPs to support");
 114
 115 unsigned int hfi1_max_srqs = 1024;
 116 module_param_named(max_srqs, hfi1_max_srqs, uint, S_IRUGO);
 117 MODULE_PARM_DESC(max_srqs, "Maximum number of SRQs to support");
 118
 119 unsigned int hfi1_max_srq_sges = 128;
 120 module_param_named(max_srq_sges, hfi1_max_srq_sges, uint, S_IRUGO);
 121 MODULE_PARM_DESC(max_srq_sges, "Maximum number of SRQ SGEs to support");
 122
 123 unsigned int hfi1_max_srq_wrs = 0x1FFFF;
 124 module_param_named(max_srq_wrs, hfi1_max_srq_wrs, uint, S_IRUGO);
 125 MODULE_PARM_DESC(max_srq_wrs, "Maximum number of SRQ WRs support");
 126
 127 static void verbs_sdma_complete(
 128         struct sdma_txreq *cookie,
 129         int status,
 130         int drained);
 131
 132 /* Length of buffer to create verbs txreq cache name */
 133 #define TXREQ_NAME_LEN 24
 134
 135 /*
 136  * Note that it is OK to post send work requests in the SQE and ERR
 137  * states; hfi1_do_send() will process them and generate error
 138  * completions as per IB 1.2 C10-96.
 139  */
 140 const int ib_hfi1_state_ops[IB_QPS_ERR + 1] = {
 141         [IB_QPS_RESET] = 0,
 142         [IB_QPS_INIT] = HFI1_POST_RECV_OK,
 143         [IB_QPS_RTR] = HFI1_POST_RECV_OK | HFI1_PROCESS_RECV_OK,
 144         [IB_QPS_RTS] = HFI1_POST_RECV_OK | HFI1_PROCESS_RECV_OK |
 145             HFI1_POST_SEND_OK | HFI1_PROCESS_SEND_OK |
 146             HFI1_PROCESS_NEXT_SEND_OK,
 147         [IB_QPS_SQD] = HFI1_POST_RECV_OK | HFI1_PROCESS_RECV_OK |
 148             HFI1_POST_SEND_OK | HFI1_PROCESS_SEND_OK,
 149         [IB_QPS_SQE] = HFI1_POST_RECV_OK | HFI1_PROCESS_RECV_OK |
 150             HFI1_POST_SEND_OK | HFI1_FLUSH_SEND,
 151         [IB_QPS_ERR] = HFI1_POST_RECV_OK | HFI1_FLUSH_RECV |
 152             HFI1_POST_SEND_OK | HFI1_FLUSH_SEND,
 153 };
 154
 155 struct hfi1_ucontext {
 156         struct ib_ucontext ibucontext;
 157 };
 158
 159 static inline struct hfi1_ucontext *to_iucontext(struct ib_ucontext
 160                                                   *ibucontext)
 161 {
 162         return container_of(ibucontext, struct hfi1_ucontext, ibucontext);
 163 }
 164
 165 /*
 166  * Translate ib_wr_opcode into ib_wc_opcode.
 167  */
 168 const enum ib_wc_opcode ib_hfi1_wc_opcode[] = {
 169         [IB_WR_RDMA_WRITE] = IB_WC_RDMA_WRITE,
 170         [IB_WR_RDMA_WRITE_WITH_IMM] = IB_WC_RDMA_WRITE,
 171         [IB_WR_SEND] = IB_WC_SEND,
 172         [IB_WR_SEND_WITH_IMM] = IB_WC_SEND,
 173         [IB_WR_RDMA_READ] = IB_WC_RDMA_READ,
 174         [IB_WR_ATOMIC_CMP_AND_SWP] = IB_WC_COMP_SWAP,
 175         [IB_WR_ATOMIC_FETCH_AND_ADD] = IB_WC_FETCH_ADD
 176 };
 177
 178 /*
 179  * Length of header by opcode, 0 --> not supported
 180  */
 181 const u8 hdr_len_by_opcode[256] = {
 182         /* RC */
 183         [IB_OPCODE_RC_SEND_FIRST]                     = 12 + 8,
 184         [IB_OPCODE_RC_SEND_MIDDLE]                    = 12 + 8,
 185         [IB_OPCODE_RC_SEND_LAST]                      = 12 + 8,
 186         [IB_OPCODE_RC_SEND_LAST_WITH_IMMEDIATE]       = 12 + 8 + 4,
 187         [IB_OPCODE_RC_SEND_ONLY]                      = 12 + 8,
 188         [IB_OPCODE_RC_SEND_ONLY_WITH_IMMEDIATE]       = 12 + 8 + 4,
 189         [IB_OPCODE_RC_RDMA_WRITE_FIRST]               = 12 + 8 + 16,
 190         [IB_OPCODE_RC_RDMA_WRITE_MIDDLE]              = 12 + 8,
 191         [IB_OPCODE_RC_RDMA_WRITE_LAST]                = 12 + 8,
 192         [IB_OPCODE_RC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = 12 + 8 + 4,
 193         [IB_OPCODE_RC_RDMA_WRITE_ONLY]                = 12 + 8 + 16,
 194         [IB_OPCODE_RC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = 12 + 8 + 20,
 195         [IB_OPCODE_RC_RDMA_READ_REQUEST]              = 12 + 8 + 16,
 196         [IB_OPCODE_RC_RDMA_READ_RESPONSE_FIRST]       = 12 + 8 + 4,
 197         [IB_OPCODE_RC_RDMA_READ_RESPONSE_MIDDLE]      = 12 + 8,
 198         [IB_OPCODE_RC_RDMA_READ_RESPONSE_LAST]        = 12 + 8 + 4,
 199         [IB_OPCODE_RC_RDMA_READ_RESPONSE_ONLY]        = 12 + 8 + 4,
 200         [IB_OPCODE_RC_ACKNOWLEDGE]                    = 12 + 8 + 4,
 201         [IB_OPCODE_RC_ATOMIC_ACKNOWLEDGE]             = 12 + 8 + 4,
 202         [IB_OPCODE_RC_COMPARE_SWAP]                   = 12 + 8 + 28,
 203         [IB_OPCODE_RC_FETCH_ADD]                      = 12 + 8 + 28,
 204         /* UC */
 205         [IB_OPCODE_UC_SEND_FIRST]                     = 12 + 8,
 206         [IB_OPCODE_UC_SEND_MIDDLE]                    = 12 + 8,
 207         [IB_OPCODE_UC_SEND_LAST]                      = 12 + 8,
 208         [IB_OPCODE_UC_SEND_LAST_WITH_IMMEDIATE]       = 12 + 8 + 4,
 209         [IB_OPCODE_UC_SEND_ONLY]                      = 12 + 8,
 210         [IB_OPCODE_UC_SEND_ONLY_WITH_IMMEDIATE]       = 12 + 8 + 4,
 211         [IB_OPCODE_UC_RDMA_WRITE_FIRST]               = 12 + 8 + 16,
 212         [IB_OPCODE_UC_RDMA_WRITE_MIDDLE]              = 12 + 8,
 213         [IB_OPCODE_UC_RDMA_WRITE_LAST]                = 12 + 8,
 214         [IB_OPCODE_UC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = 12 + 8 + 4,
 215         [IB_OPCODE_UC_RDMA_WRITE_ONLY]                = 12 + 8 + 16,
 216         [IB_OPCODE_UC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = 12 + 8 + 20,
 217         /* UD */
 218         [IB_OPCODE_UD_SEND_ONLY]                      = 12 + 8 + 8,
 219         [IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE]       = 12 + 8 + 12
 220 };
 221
 222 static const opcode_handler opcode_handler_tbl[256] = {
 223         /* RC */
 224         [IB_OPCODE_RC_SEND_FIRST]                     = &hfi1_rc_rcv,
 225         [IB_OPCODE_RC_SEND_MIDDLE]                    = &hfi1_rc_rcv,
 226         [IB_OPCODE_RC_SEND_LAST]                      = &hfi1_rc_rcv,
 227         [IB_OPCODE_RC_SEND_LAST_WITH_IMMEDIATE]       = &hfi1_rc_rcv,
 228         [IB_OPCODE_RC_SEND_ONLY]                      = &hfi1_rc_rcv,
 229         [IB_OPCODE_RC_SEND_ONLY_WITH_IMMEDIATE]       = &hfi1_rc_rcv,
 230         [IB_OPCODE_RC_RDMA_WRITE_FIRST]               = &hfi1_rc_rcv,
 231         [IB_OPCODE_RC_RDMA_WRITE_MIDDLE]              = &hfi1_rc_rcv,
 232         [IB_OPCODE_RC_RDMA_WRITE_LAST]                = &hfi1_rc_rcv,
 233         [IB_OPCODE_RC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = &hfi1_rc_rcv,
 234         [IB_OPCODE_RC_RDMA_WRITE_ONLY]                = &hfi1_rc_rcv,
 235         [IB_OPCODE_RC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = &hfi1_rc_rcv,
 236         [IB_OPCODE_RC_RDMA_READ_REQUEST]              = &hfi1_rc_rcv,
 237         [IB_OPCODE_RC_RDMA_READ_RESPONSE_FIRST]       = &hfi1_rc_rcv,
 238         [IB_OPCODE_RC_RDMA_READ_RESPONSE_MIDDLE]      = &hfi1_rc_rcv,
 239         [IB_OPCODE_RC_RDMA_READ_RESPONSE_LAST]        = &hfi1_rc_rcv,
 240         [IB_OPCODE_RC_RDMA_READ_RESPONSE_ONLY]        = &hfi1_rc_rcv,
 241         [IB_OPCODE_RC_ACKNOWLEDGE]                    = &hfi1_rc_rcv,
 242         [IB_OPCODE_RC_ATOMIC_ACKNOWLEDGE]             = &hfi1_rc_rcv,
 243         [IB_OPCODE_RC_COMPARE_SWAP]                   = &hfi1_rc_rcv,
 244         [IB_OPCODE_RC_FETCH_ADD]                      = &hfi1_rc_rcv,
 245         /* UC */
 246         [IB_OPCODE_UC_SEND_FIRST]                     = &hfi1_uc_rcv,
 247         [IB_OPCODE_UC_SEND_MIDDLE]                    = &hfi1_uc_rcv,
 248         [IB_OPCODE_UC_SEND_LAST]                      = &hfi1_uc_rcv,
 249         [IB_OPCODE_UC_SEND_LAST_WITH_IMMEDIATE]       = &hfi1_uc_rcv,
 250         [IB_OPCODE_UC_SEND_ONLY]                      = &hfi1_uc_rcv,
 251         [IB_OPCODE_UC_SEND_ONLY_WITH_IMMEDIATE]       = &hfi1_uc_rcv,
 252         [IB_OPCODE_UC_RDMA_WRITE_FIRST]               = &hfi1_uc_rcv,
 253         [IB_OPCODE_UC_RDMA_WRITE_MIDDLE]              = &hfi1_uc_rcv,
 254         [IB_OPCODE_UC_RDMA_WRITE_LAST]                = &hfi1_uc_rcv,
 255         [IB_OPCODE_UC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = &hfi1_uc_rcv,
 256         [IB_OPCODE_UC_RDMA_WRITE_ONLY]                = &hfi1_uc_rcv,
 257         [IB_OPCODE_UC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = &hfi1_uc_rcv,
 258         /* UD */
 259         [IB_OPCODE_UD_SEND_ONLY]                      = &hfi1_ud_rcv,
 260         [IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE]       = &hfi1_ud_rcv,
 261         /* CNP */
 262         [IB_OPCODE_CNP]                               = &hfi1_cnp_rcv
 263 };
 264
 265 /*
 266  * System image GUID.
 267  */
 268 __be64 ib_hfi1_sys_image_guid;
 269
 270 /**
 271  * hfi1_copy_sge - copy data to SGE memory
 272  * @ss: the SGE state
 273  * @data: the data to copy
 274  * @length: the length of the data
 275  */
 276 void hfi1_copy_sge(
 277         struct hfi1_sge_state *ss,
 278         void *data, u32 length,
 279         int release)
 280 {
 281         struct hfi1_sge *sge = &ss->sge;
 282
 283         while (length) {
 284                 u32 len = sge->length;
 285
 286                 if (len > length)
 287                         len = length;
 288                 if (len > sge->sge_length)
 289                         len = sge->sge_length;
 290                 WARN_ON_ONCE(len == 0);
 291                 memcpy(sge->vaddr, data, len);
 292                 sge->vaddr += len;
 293                 sge->length -= len;
 294                 sge->sge_length -= len;
 295                 if (sge->sge_length == 0) {
 296                         if (release)
 297                                 hfi1_put_mr(sge->mr);
 298                         if (--ss->num_sge)
 299                                 *sge = *ss->sg_list++;
 300                 } else if (sge->length == 0 && sge->mr->lkey) {
 301                         if (++sge->n >= HFI1_SEGSZ) {
 302                                 if (++sge->m >= sge->mr->mapsz)
 303                                         break;
 304                                 sge->n = 0;
 305                         }
 306                         sge->vaddr =
 307                                 sge->mr->map[sge->m]->segs[sge->n].vaddr;
 308                         sge->length =
 309                                 sge->mr->map[sge->m]->segs[sge->n].length;
 310                 }
 311                 data += len;
 312                 length -= len;
 313         }
 314 }
 315
 316 /**
 317  * hfi1_skip_sge - skip over SGE memory
 318  * @ss: the SGE state
 319  * @length: the number of bytes to skip
 320  */
 321 void hfi1_skip_sge(struct hfi1_sge_state *ss, u32 length, int release)
 322 {
 323         struct hfi1_sge *sge = &ss->sge;
 324
 325         while (length) {
 326                 u32 len = sge->length;
 327
 328                 if (len > length)
 329                         len = length;
 330                 if (len > sge->sge_length)
 331                         len = sge->sge_length;
 332                 WARN_ON_ONCE(len == 0);
 333                 sge->vaddr += len;
 334                 sge->length -= len;
 335                 sge->sge_length -= len;
 336                 if (sge->sge_length == 0) {
 337                         if (release)
 338                                 hfi1_put_mr(sge->mr);
 339                         if (--ss->num_sge)
 340                                 *sge = *ss->sg_list++;
 341                 } else if (sge->length == 0 && sge->mr->lkey) {
 342                         if (++sge->n >= HFI1_SEGSZ) {
 343                                 if (++sge->m >= sge->mr->mapsz)
 344                                         break;
 345                                 sge->n = 0;
 346                         }
 347                         sge->vaddr =
 348                                 sge->mr->map[sge->m]->segs[sge->n].vaddr;
 349                         sge->length =
 350                                 sge->mr->map[sge->m]->segs[sge->n].length;
 351                 }
 352                 length -= len;
 353         }
 354 }
 355
 356 /**
 357  * post_one_send - post one RC, UC, or UD send work request
 358  * @qp: the QP to post on
 359  * @wr: the work request to send
 360  */
 361 static int post_one_send(struct hfi1_qp *qp, struct ib_send_wr *wr)
 362 {
 363         struct hfi1_swqe *wqe;
 364         u32 next;
 365         int i;
 366         int j;
 367         int acc;
 368         struct hfi1_lkey_table *rkt;
 369         struct hfi1_pd *pd;
 370         struct hfi1_devdata *dd = dd_from_ibdev(qp->ibqp.device);
 371         struct hfi1_pportdata *ppd;
 372         struct hfi1_ibport *ibp;
 373
 374         /* IB spec says that num_sge == 0 is OK. */
 375         if (unlikely(wr->num_sge > qp->s_max_sge))
 376                 return -EINVAL;
 377
 378         ppd = &dd->pport[qp->port_num - 1];
 379         ibp = &ppd->ibport_data;
 380
 381         /*
 382          * Don't allow RDMA reads or atomic operations on UC or
 383          * undefined operations.
 384          * Make sure buffer is large enough to hold the result for atomics.
 385          */
 386         if (wr->opcode == IB_WR_FAST_REG_MR) {
 387                 return -EINVAL;
 388         } else if (qp->ibqp.qp_type == IB_QPT_UC) {
 389                 if ((unsigned) wr->opcode >= IB_WR_RDMA_READ)
 390                         return -EINVAL;
 391         } else if (qp->ibqp.qp_type != IB_QPT_RC) {
 392                 /* Check IB_QPT_SMI, IB_QPT_GSI, IB_QPT_UD opcode */
 393                 if (wr->opcode != IB_WR_SEND &&
 394                     wr->opcode != IB_WR_SEND_WITH_IMM)
 395                         return -EINVAL;
 396                 /* Check UD destination address PD */
 397                 if (qp->ibqp.pd != wr->wr.ud.ah->pd)
 398                         return -EINVAL;
 399         } else if ((unsigned) wr->opcode > IB_WR_ATOMIC_FETCH_AND_ADD)
 400                 return -EINVAL;
 401         else if (wr->opcode >= IB_WR_ATOMIC_CMP_AND_SWP &&
 402                    (wr->num_sge == 0 ||
 403                     wr->sg_list[0].length < sizeof(u64) ||
 404                     wr->sg_list[0].addr & (sizeof(u64) - 1)))
 405                 return -EINVAL;
 406         else if (wr->opcode >= IB_WR_RDMA_READ && !qp->s_max_rd_atomic)
 407                 return -EINVAL;
 408
 409         next = qp->s_head + 1;
 410         if (next >= qp->s_size)
 411                 next = 0;
 412         if (next == qp->s_last)
 413                 return -ENOMEM;
 414
 415         rkt = &to_idev(qp->ibqp.device)->lk_table;
 416         pd = to_ipd(qp->ibqp.pd);
 417         wqe = get_swqe_ptr(qp, qp->s_head);
 418         wqe->wr = *wr;
 419         wqe->length = 0;
 420         j = 0;
 421         if (wr->num_sge) {
 422                 acc = wr->opcode >= IB_WR_RDMA_READ ?
 423                         IB_ACCESS_LOCAL_WRITE : 0;
 424                 for (i = 0; i < wr->num_sge; i++) {
 425                         u32 length = wr->sg_list[i].length;
 426                         int ok;
 427
 428                         if (length == 0)
 429                                 continue;
 430                         ok = hfi1_lkey_ok(rkt, pd, &wqe->sg_list[j],
 431                                           &wr->sg_list[i], acc);
 432                         if (!ok)
 433                                 goto bail_inval_free;
 434                         wqe->length += length;
 435                         j++;
 436                 }
 437                 wqe->wr.num_sge = j;
 438         }
 439         if (qp->ibqp.qp_type == IB_QPT_UC ||
 440             qp->ibqp.qp_type == IB_QPT_RC) {
 441                 if (wqe->length > 0x80000000U)
 442                         goto bail_inval_free;
 443         } else {
 444                 struct hfi1_ah *ah = to_iah(wr->wr.ud.ah);
 445
 446                 atomic_inc(&ah->refcount);
 447         }
 448         wqe->ssn = qp->s_ssn++;
 449         qp->s_head = next;
 450
 451         return 0;
 452
 453 bail_inval_free:
 454         /* release mr holds */
 455         while (j) {
 456                 struct hfi1_sge *sge = &wqe->sg_list[--j];
 457
 458                 hfi1_put_mr(sge->mr);
 459         }
 460         return -EINVAL;
 461 }
 462
 463 /**
 464  * post_send - post a send on a QP
 465  * @ibqp: the QP to post the send on
 466  * @wr: the list of work requests to post
 467  * @bad_wr: the first bad WR is put here
 468  *
 469  * This may be called from interrupt context.
 470  */
 471 static int post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
 472                      struct ib_send_wr **bad_wr)
 473 {
 474         struct hfi1_qp *qp = to_iqp(ibqp);
 475         int err = 0;
 476         int call_send;
 477         unsigned long flags;
 478         unsigned nreq = 0;
 479
 480         spin_lock_irqsave(&qp->s_lock, flags);
 481
 482         /* Check that state is OK to post send. */
 483         if (unlikely(!(ib_hfi1_state_ops[qp->state] & HFI1_POST_SEND_OK))) {
 484                 spin_unlock_irqrestore(&qp->s_lock, flags);
 485                 return -EINVAL;
 486         }
 487
 488         /* sq empty and not list -> call send */
 489         call_send = qp->s_head == qp->s_last && !wr->next;
 490
 491         for (; wr; wr = wr->next) {
 492                 err = post_one_send(qp, wr);
 493                 if (unlikely(err)) {
 494                         *bad_wr = wr;
 495                         goto bail;
 496                 }
 497                 nreq++;
 498         }
 499 bail:
 500         if (nreq && !call_send)
 501                 hfi1_schedule_send(qp);
 502         spin_unlock_irqrestore(&qp->s_lock, flags);
 503         if (nreq && call_send)
 504                 hfi1_do_send(&qp->s_iowait.iowork);
 505         return err;
 506 }
 507
 508 /**
 509  * post_receive - post a receive on a QP
 510  * @ibqp: the QP to post the receive on
 511  * @wr: the WR to post
 512  * @bad_wr: the first bad WR is put here
 513  *
 514  * This may be called from interrupt context.
 515  */
 516 static int post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
 517                         struct ib_recv_wr **bad_wr)
 518 {
 519         struct hfi1_qp *qp = to_iqp(ibqp);
 520         struct hfi1_rwq *wq = qp->r_rq.wq;
 521         unsigned long flags;
 522         int ret;
 523
 524         /* Check that state is OK to post receive. */
 525         if (!(ib_hfi1_state_ops[qp->state] & HFI1_POST_RECV_OK) || !wq) {
 526                 *bad_wr = wr;
 527                 ret = -EINVAL;
 528                 goto bail;
 529         }
 530
 531         for (; wr; wr = wr->next) {
 532                 struct hfi1_rwqe *wqe;
 533                 u32 next;
 534                 int i;
 535
 536                 if ((unsigned) wr->num_sge > qp->r_rq.max_sge) {
 537                         *bad_wr = wr;
 538                         ret = -EINVAL;
 539                         goto bail;
 540                 }
 541
 542                 spin_lock_irqsave(&qp->r_rq.lock, flags);
 543                 next = wq->head + 1;
 544                 if (next >= qp->r_rq.size)
 545                         next = 0;
 546                 if (next == wq->tail) {
 547                         spin_unlock_irqrestore(&qp->r_rq.lock, flags);
 548                         *bad_wr = wr;
 549                         ret = -ENOMEM;
 550                         goto bail;
 551                 }
 552
 553                 wqe = get_rwqe_ptr(&qp->r_rq, wq->head);
 554                 wqe->wr_id = wr->wr_id;
 555                 wqe->num_sge = wr->num_sge;
 556                 for (i = 0; i < wr->num_sge; i++)
 557                         wqe->sg_list[i] = wr->sg_list[i];
 558                 /* Make sure queue entry is written before the head index. */
 559                 smp_wmb();
 560                 wq->head = next;
 561                 spin_unlock_irqrestore(&qp->r_rq.lock, flags);
 562         }
 563         ret = 0;
 564
 565 bail:
 566         return ret;
 567 }
 568
 569 /*
 570  * Make sure the QP is ready and able to accept the given opcode.
 571  */
 572 static inline int qp_ok(int opcode, struct hfi1_packet *packet)
 573 {
 574         struct hfi1_ibport *ibp;
 575
 576         if (!(ib_hfi1_state_ops[packet->qp->state] & HFI1_PROCESS_RECV_OK))
 577                 goto dropit;
 578         if (((opcode & OPCODE_QP_MASK) == packet->qp->allowed_ops) ||
 579             (opcode == IB_OPCODE_CNP))
 580                 return 1;
 581 dropit:
 582         ibp = &packet->rcd->ppd->ibport_data;
 583         ibp->n_pkt_drops++;
 584         return 0;
 585 }
 586
 587
 588 /**
 589  * hfi1_ib_rcv - process an incoming packet
 590  * @packet: data packet information
 591  *
 592  * This is called to process an incoming packet at interrupt level.
 593  *
 594  * Tlen is the length of the header + data + CRC in bytes.
 595  */
 596 void hfi1_ib_rcv(struct hfi1_packet *packet)
 597 {
 598         struct hfi1_ctxtdata *rcd = packet->rcd;
 599         struct hfi1_ib_header *hdr = packet->hdr;
 600         u32 tlen = packet->tlen;
 601         struct hfi1_pportdata *ppd = rcd->ppd;
 602         struct hfi1_ibport *ibp = &ppd->ibport_data;
 603         unsigned long flags;
 604         u32 qp_num;
 605         int lnh;
 606         u8 opcode;
 607         u16 lid;
 608
 609         /* Check for GRH */
 610         lnh = be16_to_cpu(hdr->lrh[0]) & 3;
 611         if (lnh == HFI1_LRH_BTH)
 612                 packet->ohdr = &hdr->u.oth;
 613         else if (lnh == HFI1_LRH_GRH) {
 614                 u32 vtf;
 615
 616                 packet->ohdr = &hdr->u.l.oth;
 617                 if (hdr->u.l.grh.next_hdr != IB_GRH_NEXT_HDR)
 618                         goto drop;
 619                 vtf = be32_to_cpu(hdr->u.l.grh.version_tclass_flow);
 620                 if ((vtf >> IB_GRH_VERSION_SHIFT) != IB_GRH_VERSION)
 621                         goto drop;
 622                 packet->rcv_flags |= HFI1_HAS_GRH;
 623         } else
 624                 goto drop;
 625
 626         trace_input_ibhdr(rcd->dd, hdr);
 627
 628         opcode = (be32_to_cpu(packet->ohdr->bth[0]) >> 24);
 629         inc_opstats(tlen, &rcd->opstats->stats[opcode]);
 630
 631         /* Get the destination QP number. */
 632         qp_num = be32_to_cpu(packet->ohdr->bth[1]) & HFI1_QPN_MASK;
 633         lid = be16_to_cpu(hdr->lrh[1]);
 634         if (unlikely((lid >= HFI1_MULTICAST_LID_BASE) &&
 635             (lid != HFI1_PERMISSIVE_LID))) {
 636                 struct hfi1_mcast *mcast;
 637                 struct hfi1_mcast_qp *p;
 638
 639                 if (lnh != HFI1_LRH_GRH)
 640                         goto drop;
 641                 mcast = hfi1_mcast_find(ibp, &hdr->u.l.grh.dgid);
 642                 if (mcast == NULL)
 643                         goto drop;
 644                 list_for_each_entry_rcu(p, &mcast->qp_list, list) {
 645                         packet->qp = p->qp;
 646                         spin_lock_irqsave(&packet->qp->r_lock, flags);
 647                         if (likely((qp_ok(opcode, packet))))
 648                                 opcode_handler_tbl[opcode](packet);
 649                         spin_unlock_irqrestore(&packet->qp->r_lock, flags);
 650                 }
 651                 /*
 652                  * Notify hfi1_multicast_detach() if it is waiting for us
 653                  * to finish.
 654                  */
 655                 if (atomic_dec_return(&mcast->refcount) <= 1)
 656                         wake_up(&mcast->wait);
 657         } else {
 658                 rcu_read_lock();
 659                 packet->qp = hfi1_lookup_qpn(ibp, qp_num);
 660                 if (!packet->qp) {
 661                         rcu_read_unlock();
 662                         goto drop;
 663                 }
 664                 spin_lock_irqsave(&packet->qp->r_lock, flags);
 665                 if (likely((qp_ok(opcode, packet))))
 666                         opcode_handler_tbl[opcode](packet);
 667                 spin_unlock_irqrestore(&packet->qp->r_lock, flags);
 668                 rcu_read_unlock();
 669         }
 670         return;
 671
 672 drop:
 673         ibp->n_pkt_drops++;
 674 }
 675
 676 /*
 677  * This is called from a timer to check for QPs
 678  * which need kernel memory in order to send a packet.
 679  */
 680 static void mem_timer(unsigned long data)
 681 {
 682         struct hfi1_ibdev *dev = (struct hfi1_ibdev *)data;
 683         struct list_head *list = &dev->memwait;
 684         struct hfi1_qp *qp = NULL;
 685         struct iowait *wait;
 686         unsigned long flags;
 687
 688         write_seqlock_irqsave(&dev->iowait_lock, flags);
 689         if (!list_empty(list)) {
 690                 wait = list_first_entry(list, struct iowait, list);
 691                 qp = container_of(wait, struct hfi1_qp, s_iowait);
 692                 list_del_init(&qp->s_iowait.list);
 693                 /* refcount held until actual wake up */
 694                 if (!list_empty(list))
 695                         mod_timer(&dev->mem_timer, jiffies + 1);
 696         }
 697         write_sequnlock_irqrestore(&dev->iowait_lock, flags);
 698
 699         if (qp)
 700                 hfi1_qp_wakeup(qp, HFI1_S_WAIT_KMEM);
 701 }
 702
 703 void update_sge(struct hfi1_sge_state *ss, u32 length)
 704 {
 705         struct hfi1_sge *sge = &ss->sge;
 706
 707         sge->vaddr += length;
 708         sge->length -= length;
 709         sge->sge_length -= length;
 710         if (sge->sge_length == 0) {
 711                 if (--ss->num_sge)
 712                         *sge = *ss->sg_list++;
 713         } else if (sge->length == 0 && sge->mr->lkey) {
 714                 if (++sge->n >= HFI1_SEGSZ) {
 715                         if (++sge->m >= sge->mr->mapsz)
 716                                 return;
 717                         sge->n = 0;
 718                 }
 719                 sge->vaddr = sge->mr->map[sge->m]->segs[sge->n].vaddr;
 720                 sge->length = sge->mr->map[sge->m]->segs[sge->n].length;
 721         }
 722 }
 723
 724 static noinline struct verbs_txreq *__get_txreq(struct hfi1_ibdev *dev,
 725                                                 struct hfi1_qp *qp)
 726 {
 727         struct verbs_txreq *tx;
 728         unsigned long flags;
 729
 730         tx = kmem_cache_alloc(dev->verbs_txreq_cache, GFP_ATOMIC);
 731         if (!tx) {
 732                 spin_lock_irqsave(&qp->s_lock, flags);
 733                 write_seqlock(&dev->iowait_lock);
 734                 if (ib_hfi1_state_ops[qp->state] & HFI1_PROCESS_RECV_OK &&
 735                     list_empty(&qp->s_iowait.list)) {
 736                         dev->n_txwait++;
 737                         qp->s_flags |= HFI1_S_WAIT_TX;
 738                         list_add_tail(&qp->s_iowait.list, &dev->txwait);
 739                         trace_hfi1_qpsleep(qp, HFI1_S_WAIT_TX);
 740                         atomic_inc(&qp->refcount);
 741                 }
 742                 qp->s_flags &= ~HFI1_S_BUSY;
 743                 write_sequnlock(&dev->iowait_lock);
 744                 spin_unlock_irqrestore(&qp->s_lock, flags);
 745                 tx = ERR_PTR(-EBUSY);
 746         }
 747         return tx;
 748 }
 749
 750 static inline struct verbs_txreq *get_txreq(struct hfi1_ibdev *dev,
 751                                             struct hfi1_qp *qp)
 752 {
 753         struct verbs_txreq *tx;
 754
 755         tx = kmem_cache_alloc(dev->verbs_txreq_cache, GFP_ATOMIC);
 756         if (!tx) {
 757                 /* call slow path to get the lock */
 758                 tx =  __get_txreq(dev, qp);
 759                 if (IS_ERR(tx))
 760                         return tx;
 761         }
 762         tx->qp = qp;
 763         return tx;
 764 }
 765
 766 void hfi1_put_txreq(struct verbs_txreq *tx)
 767 {
 768         struct hfi1_ibdev *dev;
 769         struct hfi1_qp *qp;
 770         unsigned long flags;
 771         unsigned int seq;
 772
 773         qp = tx->qp;
 774         dev = to_idev(qp->ibqp.device);
 775
 776         if (tx->mr) {
 777                 hfi1_put_mr(tx->mr);
 778                 tx->mr = NULL;
 779         }
 780         sdma_txclean(dd_from_dev(dev), &tx->txreq);
 781
 782         /* Free verbs_txreq and return to slab cache */
 783         kmem_cache_free(dev->verbs_txreq_cache, tx);
 784
 785         do {
 786                 seq = read_seqbegin(&dev->iowait_lock);
 787                 if (!list_empty(&dev->txwait)) {
 788                         struct iowait *wait;
 789
 790                         write_seqlock_irqsave(&dev->iowait_lock, flags);
 791                         /* Wake up first QP wanting a free struct */
 792                         wait = list_first_entry(&dev->txwait, struct iowait,
 793                                                 list);
 794                         qp = container_of(wait, struct hfi1_qp, s_iowait);
 795                         list_del_init(&qp->s_iowait.list);
 796                         /* refcount held until actual wake up */
 797                         write_sequnlock_irqrestore(&dev->iowait_lock, flags);
 798                         hfi1_qp_wakeup(qp, HFI1_S_WAIT_TX);
 799                         break;
 800                 }
 801         } while (read_seqretry(&dev->iowait_lock, seq));
 802 }
 803
 804 /*
 805  * This is called with progress side lock held.
 806  */
 807 /* New API */
 808 static void verbs_sdma_complete(
 809         struct sdma_txreq *cookie,
 810         int status,
 811         int drained)
 812 {
 813         struct verbs_txreq *tx =
 814                 container_of(cookie, struct verbs_txreq, txreq);
 815         struct hfi1_qp *qp = tx->qp;
 816
 817         spin_lock(&qp->s_lock);
 818         if (tx->wqe)
 819                 hfi1_send_complete(qp, tx->wqe, IB_WC_SUCCESS);
 820         else if (qp->ibqp.qp_type == IB_QPT_RC) {
 821                 struct hfi1_ib_header *hdr;
 822
 823                 hdr = &tx->phdr.hdr;
 824                 hfi1_rc_send_complete(qp, hdr);
 825         }
 826         if (drained) {
 827                 /*
 828                  * This happens when the send engine notes
 829                  * a QP in the error state and cannot
 830                  * do the flush work until that QP's
 831                  * sdma work has finished.
 832                  */
 833                 if (qp->s_flags & HFI1_S_WAIT_DMA) {
 834                         qp->s_flags &= ~HFI1_S_WAIT_DMA;
 835                         hfi1_schedule_send(qp);
 836                 }
 837         }
 838         spin_unlock(&qp->s_lock);
 839
 840         hfi1_put_txreq(tx);
 841 }
 842
 843 static int wait_kmem(struct hfi1_ibdev *dev, struct hfi1_qp *qp)
 844 {
 845         unsigned long flags;
 846         int ret = 0;
 847
 848         spin_lock_irqsave(&qp->s_lock, flags);
 849         if (ib_hfi1_state_ops[qp->state] & HFI1_PROCESS_RECV_OK) {
 850                 write_seqlock(&dev->iowait_lock);
 851                 if (list_empty(&qp->s_iowait.list)) {
 852                         if (list_empty(&dev->memwait))
 853                                 mod_timer(&dev->mem_timer, jiffies + 1);
 854                         qp->s_flags |= HFI1_S_WAIT_KMEM;
 855                         list_add_tail(&qp->s_iowait.list, &dev->memwait);
 856                         trace_hfi1_qpsleep(qp, HFI1_S_WAIT_KMEM);
 857                         atomic_inc(&qp->refcount);
 858                 }
 859                 write_sequnlock(&dev->iowait_lock);
 860                 qp->s_flags &= ~HFI1_S_BUSY;
 861                 ret = -EBUSY;
 862         }
 863         spin_unlock_irqrestore(&qp->s_lock, flags);
 864
 865         return ret;
 866 }
 867
 868 /*
 869  * This routine calls txadds for each sg entry.
 870  *
 871  * Add failures will revert the sge cursor
 872  */
 873 static int build_verbs_ulp_payload(
 874         struct sdma_engine *sde,
 875         struct hfi1_sge_state *ss,
 876         u32 length,
 877         struct verbs_txreq *tx)
 878 {
 879         struct hfi1_sge *sg_list = ss->sg_list;
 880         struct hfi1_sge sge = ss->sge;
 881         u8 num_sge = ss->num_sge;
 882         u32 len;
 883         int ret = 0;
 884
 885         while (length) {
 886                 len = ss->sge.length;
 887                 if (len > length)
 888                         len = length;
 889                 if (len > ss->sge.sge_length)
 890                         len = ss->sge.sge_length;
 891                 WARN_ON_ONCE(len == 0);
 892                 ret = sdma_txadd_kvaddr(
 893                         sde->dd,
 894                         &tx->txreq,
 895                         ss->sge.vaddr,
 896                         len);
 897                 if (ret)
 898                         goto bail_txadd;
 899                 update_sge(ss, len);
 900                 length -= len;
 901         }
 902         return ret;
 903 bail_txadd:
 904         /* unwind cursor */
 905         ss->sge = sge;
 906         ss->num_sge = num_sge;
 907         ss->sg_list = sg_list;
 908         return ret;
 909 }
 910
 911 /*
 912  * Build the number of DMA descriptors needed to send length bytes of data.
 913  *
 914  * NOTE: DMA mapping is held in the tx until completed in the ring or
 915  *       the tx desc is freed without having been submitted to the ring
 916  *
 917  * This routine insures the following all the helper routine
 918  * calls succeed.
 919  */
 920 /* New API */
 921 static int build_verbs_tx_desc(
 922         struct sdma_engine *sde,
 923         struct hfi1_sge_state *ss,
 924         u32 length,
 925         struct verbs_txreq *tx,
 926         struct ahg_ib_header *ahdr,
 927         u64 pbc)
 928 {
 929         int ret = 0;
 930         struct hfi1_pio_header *phdr;
 931         u16 hdrbytes = tx->hdr_dwords << 2;
 932
 933         phdr = &tx->phdr;
 934         if (!ahdr->ahgcount) {
 935                 ret = sdma_txinit_ahg(
 936                         &tx->txreq,
 937                         ahdr->tx_flags,
 938                         hdrbytes + length,
 939                         ahdr->ahgidx,
 940                         0,
 941                         NULL,
 942                         0,
 943                         verbs_sdma_complete);
 944                 if (ret)
 945                         goto bail_txadd;
 946                 phdr->pbc = cpu_to_le64(pbc);
 947                 memcpy(&phdr->hdr, &ahdr->ibh, hdrbytes - sizeof(phdr->pbc));
 948                 /* add the header */
 949                 ret = sdma_txadd_kvaddr(
 950                         sde->dd,
 951                         &tx->txreq,
 952                         &tx->phdr,
 953                         tx->hdr_dwords << 2);
 954                 if (ret)
 955                         goto bail_txadd;
 956         } else {
 957                 struct hfi1_other_headers *sohdr = &ahdr->ibh.u.oth;
 958                 struct hfi1_other_headers *dohdr = &phdr->hdr.u.oth;
 959
 960                 /* needed in rc_send_complete() */
 961                 phdr->hdr.lrh[0] = ahdr->ibh.lrh[0];
 962                 if ((be16_to_cpu(phdr->hdr.lrh[0]) & 3) == HFI1_LRH_GRH) {
 963                         sohdr = &ahdr->ibh.u.l.oth;
 964                         dohdr = &phdr->hdr.u.l.oth;
 965                 }
 966                 /* opcode */
 967                 dohdr->bth[0] = sohdr->bth[0];
 968                 /* PSN/ACK  */
 969                 dohdr->bth[2] = sohdr->bth[2];
 970                 ret = sdma_txinit_ahg(
 971                         &tx->txreq,
 972                         ahdr->tx_flags,
 973                         length,
 974                         ahdr->ahgidx,
 975                         ahdr->ahgcount,
 976                         ahdr->ahgdesc,
 977                         hdrbytes,
 978                         verbs_sdma_complete);
 979                 if (ret)
 980                         goto bail_txadd;
 981         }
 982
 983         /* add the ulp payload - if any.  ss can be NULL for acks */
 984         if (ss)
 985                 ret = build_verbs_ulp_payload(sde, ss, length, tx);
 986 bail_txadd:
 987         return ret;
 988 }
 989
 990 int hfi1_verbs_send_dma(struct hfi1_qp *qp, struct ahg_ib_header *ahdr,
 991                         u32 hdrwords, struct hfi1_sge_state *ss, u32 len,
 992                         u32 plen, u32 dwords, u64 pbc)
 993 {
 994         struct hfi1_ibdev *dev = to_idev(qp->ibqp.device);
 995         struct hfi1_ibport *ibp = to_iport(qp->ibqp.device, qp->port_num);
 996         struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
 997         struct verbs_txreq *tx;
 998         struct sdma_txreq *stx;
 999         u64 pbc_flags = 0;
1000         struct sdma_engine *sde;
1001         u8 sc5 = qp->s_sc;
1002         int ret;
1003
1004         if (!list_empty(&qp->s_iowait.tx_head)) {
1005                 stx = list_first_entry(
1006                         &qp->s_iowait.tx_head,
1007                         struct sdma_txreq,
1008                         list);
1009                 list_del_init(&stx->list);
1010                 tx = container_of(stx, struct verbs_txreq, txreq);
1011                 ret = sdma_send_txreq(tx->sde, &qp->s_iowait, stx);
1012                 if (unlikely(ret == -ECOMM))
1013                         goto bail_ecomm;
1014                 return ret;
1015         }
1016
1017         tx = get_txreq(dev, qp);
1018         if (IS_ERR(tx))
1019                 goto bail_tx;
1020
1021         if (!qp->s_hdr->sde) {
1022                 tx->sde = sde = qp_to_sdma_engine(qp, sc5);
1023                 if (!sde)
1024                         goto bail_no_sde;
1025         } else
1026                 tx->sde = sde = qp->s_hdr->sde;
1027
1028         if (likely(pbc == 0)) {
1029                 u32 vl = sc_to_vlt(dd_from_ibdev(qp->ibqp.device), sc5);
1030                 /* No vl15 here */
1031                 /* set PBC_DC_INFO bit (aka SC[4]) in pbc_flags */
1032                 pbc_flags |= (!!(sc5 & 0x10)) << PBC_DC_INFO_SHIFT;
1033
1034                 pbc = create_pbc(ppd, pbc_flags, qp->srate_mbps, vl, plen);
1035         }
1036         tx->wqe = qp->s_wqe;
1037         tx->mr = qp->s_rdma_mr;
1038         if (qp->s_rdma_mr)
1039                 qp->s_rdma_mr = NULL;
1040         tx->hdr_dwords = hdrwords + 2;
1041         ret = build_verbs_tx_desc(sde, ss, len, tx, ahdr, pbc);
1042         if (unlikely(ret))
1043                 goto bail_build;
1044         trace_output_ibhdr(dd_from_ibdev(qp->ibqp.device), &ahdr->ibh);
1045         ret =  sdma_send_txreq(sde, &qp->s_iowait, &tx->txreq);
1046         if (unlikely(ret == -ECOMM))
1047                 goto bail_ecomm;
1048         return ret;
1049
1050 bail_no_sde:
1051         hfi1_put_txreq(tx);
1052 bail_ecomm:
1053         /* The current one got "sent" */
1054         return 0;
1055 bail_build:
1056         /* kmalloc or mapping fail */
1057         hfi1_put_txreq(tx);
1058         return wait_kmem(dev, qp);
1059 bail_tx:
1060         return PTR_ERR(tx);
1061 }
1062
1063 /*
1064  * If we are now in the error state, return zero to flush the
1065  * send work request.
1066  */
1067 static int no_bufs_available(struct hfi1_qp *qp, struct send_context *sc)
1068 {
1069         struct hfi1_devdata *dd = sc->dd;
1070         struct hfi1_ibdev *dev = &dd->verbs_dev;
1071         unsigned long flags;
1072         int ret = 0;
1073
1074         /*
1075          * Note that as soon as want_buffer() is called and
1076          * possibly before it returns, sc_piobufavail()
1077          * could be called. Therefore, put QP on the I/O wait list before
1078          * enabling the PIO avail interrupt.
1079          */
1080         spin_lock_irqsave(&qp->s_lock, flags);
1081         if (ib_hfi1_state_ops[qp->state] & HFI1_PROCESS_RECV_OK) {
1082                 write_seqlock(&dev->iowait_lock);
1083                 if (list_empty(&qp->s_iowait.list)) {
1084                         struct hfi1_ibdev *dev = &dd->verbs_dev;
1085                         int was_empty;
1086
1087                         dev->n_piowait++;
1088                         qp->s_flags |= HFI1_S_WAIT_PIO;
1089                         was_empty = list_empty(&sc->piowait);
1090                         list_add_tail(&qp->s_iowait.list, &sc->piowait);
1091                         trace_hfi1_qpsleep(qp, HFI1_S_WAIT_PIO);
1092                         atomic_inc(&qp->refcount);
1093                         /* counting: only call wantpiobuf_intr if first user */
1094                         if (was_empty)
1095                                 hfi1_sc_wantpiobuf_intr(sc, 1);
1096                 }
1097                 write_sequnlock(&dev->iowait_lock);
1098                 qp->s_flags &= ~HFI1_S_BUSY;
1099                 ret = -EBUSY;
1100         }
1101         spin_unlock_irqrestore(&qp->s_lock, flags);
1102         return ret;
1103 }
1104
1105 struct send_context *qp_to_send_context(struct hfi1_qp *qp, u8 sc5)
1106 {
1107         struct hfi1_devdata *dd = dd_from_ibdev(qp->ibqp.device);
1108         struct hfi1_pportdata *ppd = dd->pport + (qp->port_num - 1);
1109         u8 vl;
1110
1111         vl = sc_to_vlt(dd, sc5);
1112         if (vl >= ppd->vls_supported && vl != 15)
1113                 return NULL;
1114         return dd->vld[vl].sc;
1115 }
1116
1117 int hfi1_verbs_send_pio(struct hfi1_qp *qp, struct ahg_ib_header *ahdr,
1118                         u32 hdrwords, struct hfi1_sge_state *ss, u32 len,
1119                         u32 plen, u32 dwords, u64 pbc)
1120 {
1121         struct hfi1_ibport *ibp = to_iport(qp->ibqp.device, qp->port_num);
1122         struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
1123         u32 *hdr = (u32 *)&ahdr->ibh;
1124         u64 pbc_flags = 0;
1125         u32 sc5;
1126         unsigned long flags = 0;
1127         struct send_context *sc;
1128         struct pio_buf *pbuf;
1129         int wc_status = IB_WC_SUCCESS;
1130
1131         /* vl15 special case taken care of in ud.c */
1132         sc5 = qp->s_sc;
1133         sc = qp_to_send_context(qp, sc5);
1134
1135         if (!sc)
1136                 return -EINVAL;
1137         if (likely(pbc == 0)) {
1138                 u32 vl = sc_to_vlt(dd_from_ibdev(qp->ibqp.device), sc5);
1139                 /* set PBC_DC_INFO bit (aka SC[4]) in pbc_flags */
1140                 pbc_flags |= (!!(sc5 & 0x10)) << PBC_DC_INFO_SHIFT;
1141                 pbc = create_pbc(ppd, pbc_flags, qp->srate_mbps, vl, plen);
1142         }
1143         pbuf = sc_buffer_alloc(sc, plen, NULL, NULL);
1144         if (unlikely(pbuf == NULL)) {
1145                 if (ppd->host_link_state != HLS_UP_ACTIVE) {
1146                         /*
1147                          * If we have filled the PIO buffers to capacity and are
1148                          * not in an active state this request is not going to
1149                          * go out to so just complete it with an error or else a
1150                          * ULP or the core may be stuck waiting.
1151                          */
1152                         hfi1_cdbg(
1153                                 PIO,
1154                                 "alloc failed. state not active, completing");
1155                         wc_status = IB_WC_GENERAL_ERR;
1156                         goto pio_bail;
1157                 } else {
1158                         /*
1159                          * This is a normal occurrence. The PIO buffs are full
1160                          * up but we are still happily sending, well we could be
1161                          * so lets continue to queue the request.
1162                          */
1163                         hfi1_cdbg(PIO, "alloc failed. state active, queuing");
1164                         return no_bufs_available(qp, sc);
1165                 }
1166         }
1167
1168         if (len == 0) {
1169                 pio_copy(ppd->dd, pbuf, pbc, hdr, hdrwords);
1170         } else {
1171                 if (ss) {
1172                         seg_pio_copy_start(pbuf, pbc, hdr, hdrwords*4);
1173                         while (len) {
1174                                 void *addr = ss->sge.vaddr;
1175                                 u32 slen = ss->sge.length;
1176
1177                                 if (slen > len)
1178                                         slen = len;
1179                                 update_sge(ss, slen);
1180                                 seg_pio_copy_mid(pbuf, addr, slen);
1181                                 len -= slen;
1182                         }
1183                         seg_pio_copy_end(pbuf);
1184                 }
1185         }
1186
1187         trace_output_ibhdr(dd_from_ibdev(qp->ibqp.device), &ahdr->ibh);
1188
1189         if (qp->s_rdma_mr) {
1190                 hfi1_put_mr(qp->s_rdma_mr);
1191                 qp->s_rdma_mr = NULL;
1192         }
1193
1194 pio_bail:
1195         if (qp->s_wqe) {
1196                 spin_lock_irqsave(&qp->s_lock, flags);
1197                 hfi1_send_complete(qp, qp->s_wqe, wc_status);
1198                 spin_unlock_irqrestore(&qp->s_lock, flags);
1199         } else if (qp->ibqp.qp_type == IB_QPT_RC) {
1200                 spin_lock_irqsave(&qp->s_lock, flags);
1201                 hfi1_rc_send_complete(qp, &ahdr->ibh);
1202                 spin_unlock_irqrestore(&qp->s_lock, flags);
1203         }
1204         return 0;
1205 }
1206
1207 /*
1208  * egress_pkey_matches_entry - return 1 if the pkey matches ent (ent
1209  * being an entry from the ingress partition key table), return 0
1210  * otherwise. Use the matching criteria for egress partition keys
1211  * specified in the OPAv1 spec., section 9.1l.7.
1212  */
1213 static inline int egress_pkey_matches_entry(u16 pkey, u16 ent)
1214 {
1215         u16 mkey = pkey & PKEY_LOW_15_MASK;
1216         u16 ment = ent & PKEY_LOW_15_MASK;
1217
1218         if (mkey == ment) {
1219                 /*
1220                  * If pkey[15] is set (full partition member),
1221                  * is bit 15 in the corresponding table element
1222                  * clear (limited member)?
1223                  */
1224                 if (pkey & PKEY_MEMBER_MASK)
1225                         return !!(ent & PKEY_MEMBER_MASK);
1226                 return 1;
1227         }
1228         return 0;
1229 }
1230
1231 /*
1232  * egress_pkey_check - return 0 if hdr's pkey matches according to the
1233  * criteria in the OPAv1 spec., section 9.11.7.
1234  */
1235 static inline int egress_pkey_check(struct hfi1_pportdata *ppd,
1236                                     struct hfi1_ib_header *hdr,
1237                                     struct hfi1_qp *qp)
1238 {
1239         struct hfi1_other_headers *ohdr;
1240         struct hfi1_devdata *dd;
1241         int i = 0;
1242         u16 pkey;
1243         u8 lnh, sc5 = qp->s_sc;
1244
1245         if (!(ppd->part_enforce & HFI1_PART_ENFORCE_OUT))
1246                 return 0;
1247
1248         /* locate the pkey within the headers */
1249         lnh = be16_to_cpu(hdr->lrh[0]) & 3;
1250         if (lnh == HFI1_LRH_GRH)
1251                 ohdr = &hdr->u.l.oth;
1252         else
1253                 ohdr = &hdr->u.oth;
1254
1255         pkey = (u16)be32_to_cpu(ohdr->bth[0]);
1256
1257         /* If SC15, pkey[0:14] must be 0x7fff */
1258         if ((sc5 == 0xf) && ((pkey & PKEY_LOW_15_MASK) != PKEY_LOW_15_MASK))
1259                 goto bad;
1260
1261
1262         /* Is the pkey = 0x0, or 0x8000? */
1263         if ((pkey & PKEY_LOW_15_MASK) == 0)
1264                 goto bad;
1265
1266         /* The most likely matching pkey has index qp->s_pkey_index */
1267         if (unlikely(!egress_pkey_matches_entry(pkey,
1268                                         ppd->pkeys[qp->s_pkey_index]))) {
1269                 /* no match - try the entire table */
1270                 for (; i < MAX_PKEY_VALUES; i++) {
1271                         if (egress_pkey_matches_entry(pkey, ppd->pkeys[i]))
1272                                 break;
1273                 }
1274         }
1275
1276         if (i < MAX_PKEY_VALUES)
1277                 return 0;
1278 bad:
1279         incr_cntr64(&ppd->port_xmit_constraint_errors);
1280         dd = ppd->dd;
1281         if (!(dd->err_info_xmit_constraint.status & OPA_EI_STATUS_SMASK)) {
1282                 u16 slid = be16_to_cpu(hdr->lrh[3]);
1283
1284                 dd->err_info_xmit_constraint.status |= OPA_EI_STATUS_SMASK;
1285                 dd->err_info_xmit_constraint.slid = slid;
1286                 dd->err_info_xmit_constraint.pkey = pkey;
1287         }
1288         return 1;
1289 }
1290
1291 /**
1292  * hfi1_verbs_send - send a packet
1293  * @qp: the QP to send on
1294  * @ahdr: the packet header
1295  * @hdrwords: the number of 32-bit words in the header
1296  * @ss: the SGE to send
1297  * @len: the length of the packet in bytes
1298  *
1299  * Return zero if packet is sent or queued OK.
1300  * Return non-zero and clear qp->s_flags HFI1_S_BUSY otherwise.
1301  */
1302 int hfi1_verbs_send(struct hfi1_qp *qp, struct ahg_ib_header *ahdr,
1303                     u32 hdrwords, struct hfi1_sge_state *ss, u32 len)
1304 {
1305         struct hfi1_devdata *dd = dd_from_ibdev(qp->ibqp.device);
1306         u32 plen;
1307         int ret;
1308         int pio = 0;
1309         unsigned long flags = 0;
1310         u32 dwords = (len + 3) >> 2;
1311
1312         /*
1313          * VL15 packets (IB_QPT_SMI) will always use PIO, so we
1314          * can defer SDMA restart until link goes ACTIVE without
1315          * worrying about just how we got there.
1316          */
1317         if ((qp->ibqp.qp_type == IB_QPT_SMI) ||
1318             !(dd->flags & HFI1_HAS_SEND_DMA))
1319                 pio = 1;
1320
1321         ret = egress_pkey_check(dd->pport, &ahdr->ibh, qp);
1322         if (unlikely(ret)) {
1323                 /*
1324                  * The value we are returning here does not get propagated to
1325                  * the verbs caller. Thus we need to complete the request with
1326                  * error otherwise the caller could be sitting waiting on the
1327                  * completion event. Only do this for PIO. SDMA has its own
1328                  * mechanism for handling the errors. So for SDMA we can just
1329                  * return.
1330                  */
1331                 if (pio) {
1332                         hfi1_cdbg(PIO, "%s() Failed. Completing with err",
1333                                   __func__);
1334                         spin_lock_irqsave(&qp->s_lock, flags);
1335                         hfi1_send_complete(qp, qp->s_wqe, IB_WC_GENERAL_ERR);
1336                         spin_unlock_irqrestore(&qp->s_lock, flags);
1337                 }
1338                 return -EINVAL;
1339         }
1340
1341         /*
1342          * Calculate the send buffer trigger address.
1343          * The +2 counts for the pbc control qword
1344          */
1345         plen = hdrwords + dwords + 2;
1346
1347         if (pio) {
1348                 ret = dd->process_pio_send(
1349                         qp, ahdr, hdrwords, ss, len, plen, dwords, 0);
1350         } else {
1351 #ifdef CONFIG_SDMA_VERBOSITY
1352                 dd_dev_err(dd, "CONFIG SDMA %s:%d %s()\n",
1353                            slashstrip(__FILE__), __LINE__, __func__);
1354                 dd_dev_err(dd, "SDMA hdrwords = %u, len = %u\n", hdrwords, len);
1355 #endif
1356                 ret = dd->process_dma_send(
1357                         qp, ahdr, hdrwords, ss, len, plen, dwords, 0);
1358         }
1359
1360         return ret;
1361 }
1362
1363 static int query_device(struct ib_device *ibdev,
1364                         struct ib_device_attr *props,
1365                         struct ib_udata *uhw)
1366 {
1367         struct hfi1_devdata *dd = dd_from_ibdev(ibdev);
1368         struct hfi1_ibdev *dev = to_idev(ibdev);
1369
1370         if (uhw->inlen || uhw->outlen)
1371                 return -EINVAL;
1372         memset(props, 0, sizeof(*props));
1373
1374         props->device_cap_flags = IB_DEVICE_BAD_PKEY_CNTR |
1375                 IB_DEVICE_BAD_QKEY_CNTR | IB_DEVICE_SHUTDOWN_PORT |
1376                 IB_DEVICE_SYS_IMAGE_GUID | IB_DEVICE_RC_RNR_NAK_GEN |
1377                 IB_DEVICE_PORT_ACTIVE_EVENT | IB_DEVICE_SRQ_RESIZE;
1378
1379         props->page_size_cap = PAGE_SIZE;
1380         props->vendor_id =
1381                 dd->oui1 << 16 | dd->oui2 << 8 | dd->oui3;
1382         props->vendor_part_id = dd->pcidev->device;
1383         props->hw_ver = dd->minrev;
1384         props->sys_image_guid = ib_hfi1_sys_image_guid;
1385         props->max_mr_size = ~0ULL;
1386         props->max_qp = hfi1_max_qps;
1387         props->max_qp_wr = hfi1_max_qp_wrs;
1388         props->max_sge = hfi1_max_sges;
1389         props->max_sge_rd = hfi1_max_sges;
1390         props->max_cq = hfi1_max_cqs;
1391         props->max_ah = hfi1_max_ahs;
1392         props->max_cqe = hfi1_max_cqes;
1393         props->max_mr = dev->lk_table.max;
1394         props->max_fmr = dev->lk_table.max;
1395         props->max_map_per_fmr = 32767;
1396         props->max_pd = hfi1_max_pds;
1397         props->max_qp_rd_atom = HFI1_MAX_RDMA_ATOMIC;
1398         props->max_qp_init_rd_atom = 255;
1399         /* props->max_res_rd_atom */
1400         props->max_srq = hfi1_max_srqs;
1401         props->max_srq_wr = hfi1_max_srq_wrs;
1402         props->max_srq_sge = hfi1_max_srq_sges;
1403         /* props->local_ca_ack_delay */
1404         props->atomic_cap = IB_ATOMIC_GLOB;
1405         props->max_pkeys = hfi1_get_npkeys(dd);
1406         props->max_mcast_grp = hfi1_max_mcast_grps;
1407         props->max_mcast_qp_attach = hfi1_max_mcast_qp_attached;
1408         props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
1409                 props->max_mcast_grp;
1410
1411         return 0;
1412 }
1413
1414 static inline u16 opa_speed_to_ib(u16 in)
1415 {
1416         u16 out = 0;
1417
1418         if (in & OPA_LINK_SPEED_25G)
1419                 out |= IB_SPEED_EDR;
1420         if (in & OPA_LINK_SPEED_12_5G)
1421                 out |= IB_SPEED_FDR;
1422
1423         return out;
1424 }
1425
1426 /*
1427  * Convert a single OPA link width (no multiple flags) to an IB value.
1428  * A zero OPA link width means link down, which means the IB width value
1429  * is a don't care.
1430  */
1431 static inline u16 opa_width_to_ib(u16 in)
1432 {
1433         switch (in) {
1434         case OPA_LINK_WIDTH_1X:
1435         /* map 2x and 3x to 1x as they don't exist in IB */
1436         case OPA_LINK_WIDTH_2X:
1437         case OPA_LINK_WIDTH_3X:
1438                 return IB_WIDTH_1X;
1439         default: /* link down or unknown, return our largest width */
1440         case OPA_LINK_WIDTH_4X:
1441                 return IB_WIDTH_4X;
1442         }
1443 }
1444
1445 static int query_port(struct ib_device *ibdev, u8 port,
1446                       struct ib_port_attr *props)
1447 {
1448         struct hfi1_devdata *dd = dd_from_ibdev(ibdev);
1449         struct hfi1_ibport *ibp = to_iport(ibdev, port);
1450         struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
1451         u16 lid = ppd->lid;
1452
1453         memset(props, 0, sizeof(*props));
1454         props->lid = lid ? lid : 0;
1455         props->lmc = ppd->lmc;
1456         props->sm_lid = ibp->sm_lid;
1457         props->sm_sl = ibp->sm_sl;
1458         /* OPA logical states match IB logical states */
1459         props->state = driver_lstate(ppd);
1460         props->phys_state = hfi1_ibphys_portstate(ppd);
1461         props->port_cap_flags = ibp->port_cap_flags;
1462         props->gid_tbl_len = HFI1_GUIDS_PER_PORT;
1463         props->max_msg_sz = 0x80000000;
1464         props->pkey_tbl_len = hfi1_get_npkeys(dd);
1465         props->bad_pkey_cntr = ibp->pkey_violations;
1466         props->qkey_viol_cntr = ibp->qkey_violations;
1467         props->active_width = (u8)opa_width_to_ib(ppd->link_width_active);
1468         /* see rate_show() in ib core/sysfs.c */
1469         props->active_speed = (u8)opa_speed_to_ib(ppd->link_speed_active);
1470         props->max_vl_num = ppd->vls_supported;
1471         props->init_type_reply = 0;
1472
1473         /* Once we are a "first class" citizen and have added the OPA MTUs to
1474          * the core we can advertise the larger MTU enum to the ULPs, for now
1475          * advertise only 4K.
1476          *
1477          * Those applications which are either OPA aware or pass the MTU enum
1478          * from the Path Records to us will get the new 8k MTU.  Those that
1479          * attempt to process the MTU enum may fail in various ways.
1480          */
1481         props->max_mtu = mtu_to_enum((!valid_ib_mtu(hfi1_max_mtu) ?
1482                                       4096 : hfi1_max_mtu), IB_MTU_4096);
1483         props->active_mtu = !valid_ib_mtu(ppd->ibmtu) ? props->max_mtu :
1484                 mtu_to_enum(ppd->ibmtu, IB_MTU_2048);
1485         props->subnet_timeout = ibp->subnet_timeout;
1486
1487         return 0;
1488 }
1489
1490 static int port_immutable(struct ib_device *ibdev, u8 port_num,
1491                           struct ib_port_immutable *immutable)
1492 {
1493         struct ib_port_attr attr;
1494         int err;
1495
1496         err = query_port(ibdev, port_num, &attr);
1497         if (err)
1498                 return err;
1499
1500         memset(immutable, 0, sizeof(*immutable));
1501
1502         immutable->pkey_tbl_len = attr.pkey_tbl_len;
1503         immutable->gid_tbl_len = attr.gid_tbl_len;
1504         immutable->core_cap_flags = RDMA_CORE_PORT_INTEL_OPA;
1505         immutable->max_mad_size = OPA_MGMT_MAD_SIZE;
1506
1507         return 0;
1508 }
1509
1510 static int modify_device(struct ib_device *device,
1511                          int device_modify_mask,
1512                          struct ib_device_modify *device_modify)
1513 {
1514         struct hfi1_devdata *dd = dd_from_ibdev(device);
1515         unsigned i;
1516         int ret;
1517
1518         if (device_modify_mask & ~(IB_DEVICE_MODIFY_SYS_IMAGE_GUID |
1519                                    IB_DEVICE_MODIFY_NODE_DESC)) {
1520                 ret = -EOPNOTSUPP;
1521                 goto bail;
1522         }
1523
1524         if (device_modify_mask & IB_DEVICE_MODIFY_NODE_DESC) {
1525                 memcpy(device->node_desc, device_modify->node_desc, 64);
1526                 for (i = 0; i < dd->num_pports; i++) {
1527                         struct hfi1_ibport *ibp = &dd->pport[i].ibport_data;
1528
1529                         hfi1_node_desc_chg(ibp);
1530                 }
1531         }
1532
1533         if (device_modify_mask & IB_DEVICE_MODIFY_SYS_IMAGE_GUID) {
1534                 ib_hfi1_sys_image_guid =
1535                         cpu_to_be64(device_modify->sys_image_guid);
1536                 for (i = 0; i < dd->num_pports; i++) {
1537                         struct hfi1_ibport *ibp = &dd->pport[i].ibport_data;
1538
1539                         hfi1_sys_guid_chg(ibp);
1540                 }
1541         }
1542
1543         ret = 0;
1544
1545 bail:
1546         return ret;
1547 }
1548
1549 static int modify_port(struct ib_device *ibdev, u8 port,
1550                        int port_modify_mask, struct ib_port_modify *props)
1551 {
1552         struct hfi1_ibport *ibp = to_iport(ibdev, port);
1553         struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
1554         int ret = 0;
1555
1556         ibp->port_cap_flags |= props->set_port_cap_mask;
1557         ibp->port_cap_flags &= ~props->clr_port_cap_mask;
1558         if (props->set_port_cap_mask || props->clr_port_cap_mask)
1559                 hfi1_cap_mask_chg(ibp);
1560         if (port_modify_mask & IB_PORT_SHUTDOWN) {
1561                 set_link_down_reason(ppd, OPA_LINKDOWN_REASON_UNKNOWN, 0,
1562                   OPA_LINKDOWN_REASON_UNKNOWN);
1563                 ret = set_link_state(ppd, HLS_DN_DOWNDEF);
1564         }
1565         if (port_modify_mask & IB_PORT_RESET_QKEY_CNTR)
1566                 ibp->qkey_violations = 0;
1567         return ret;
1568 }
1569
1570 static int query_gid(struct ib_device *ibdev, u8 port,
1571                      int index, union ib_gid *gid)
1572 {
1573         struct hfi1_devdata *dd = dd_from_ibdev(ibdev);
1574         int ret = 0;
1575
1576         if (!port || port > dd->num_pports)
1577                 ret = -EINVAL;
1578         else {
1579                 struct hfi1_ibport *ibp = to_iport(ibdev, port);
1580                 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
1581
1582                 gid->global.subnet_prefix = ibp->gid_prefix;
1583                 if (index == 0)
1584                         gid->global.interface_id = cpu_to_be64(ppd->guid);
1585                 else if (index < HFI1_GUIDS_PER_PORT)
1586                         gid->global.interface_id = ibp->guids[index - 1];
1587                 else
1588                         ret = -EINVAL;
1589         }
1590
1591         return ret;
1592 }
1593
1594 static struct ib_pd *alloc_pd(struct ib_device *ibdev,
1595                               struct ib_ucontext *context,
1596                               struct ib_udata *udata)
1597 {
1598         struct hfi1_ibdev *dev = to_idev(ibdev);
1599         struct hfi1_pd *pd;
1600         struct ib_pd *ret;
1601
1602         /*
1603          * This is actually totally arbitrary.  Some correctness tests
1604          * assume there's a maximum number of PDs that can be allocated.
1605          * We don't actually have this limit, but we fail the test if
1606          * we allow allocations of more than we report for this value.
1607          */
1608
1609         pd = kmalloc(sizeof(*pd), GFP_KERNEL);
1610         if (!pd) {
1611                 ret = ERR_PTR(-ENOMEM);
1612                 goto bail;
1613         }
1614
1615         spin_lock(&dev->n_pds_lock);
1616         if (dev->n_pds_allocated == hfi1_max_pds) {
1617                 spin_unlock(&dev->n_pds_lock);
1618                 kfree(pd);
1619                 ret = ERR_PTR(-ENOMEM);
1620                 goto bail;
1621         }
1622
1623         dev->n_pds_allocated++;
1624         spin_unlock(&dev->n_pds_lock);
1625
1626         /* ib_alloc_pd() will initialize pd->ibpd. */
1627         pd->user = udata != NULL;
1628
1629         ret = &pd->ibpd;
1630
1631 bail:
1632         return ret;
1633 }
1634
1635 static int dealloc_pd(struct ib_pd *ibpd)
1636 {
1637         struct hfi1_pd *pd = to_ipd(ibpd);
1638         struct hfi1_ibdev *dev = to_idev(ibpd->device);
1639
1640         spin_lock(&dev->n_pds_lock);
1641         dev->n_pds_allocated--;
1642         spin_unlock(&dev->n_pds_lock);
1643
1644         kfree(pd);
1645
1646         return 0;
1647 }
1648
1649 /*
1650  * convert ah port,sl to sc
1651  */
1652 u8 ah_to_sc(struct ib_device *ibdev, struct ib_ah_attr *ah)
1653 {
1654         struct hfi1_ibport *ibp = to_iport(ibdev, ah->port_num);
1655
1656         return ibp->sl_to_sc[ah->sl];
1657 }
1658
1659 int hfi1_check_ah(struct ib_device *ibdev, struct ib_ah_attr *ah_attr)
1660 {
1661         struct hfi1_ibport *ibp;
1662         struct hfi1_pportdata *ppd;
1663         struct hfi1_devdata *dd;
1664         u8 sc5;
1665
1666         /* A multicast address requires a GRH (see ch. 8.4.1). */
1667         if (ah_attr->dlid >= HFI1_MULTICAST_LID_BASE &&
1668             ah_attr->dlid != HFI1_PERMISSIVE_LID &&
1669             !(ah_attr->ah_flags & IB_AH_GRH))
1670                 goto bail;
1671         if ((ah_attr->ah_flags & IB_AH_GRH) &&
1672             ah_attr->grh.sgid_index >= HFI1_GUIDS_PER_PORT)
1673                 goto bail;
1674         if (ah_attr->dlid == 0)
1675                 goto bail;
1676         if (ah_attr->port_num < 1 ||
1677             ah_attr->port_num > ibdev->phys_port_cnt)
1678                 goto bail;
1679         if (ah_attr->static_rate != IB_RATE_PORT_CURRENT &&
1680             ib_rate_to_mbps(ah_attr->static_rate) < 0)
1681                 goto bail;
1682         if (ah_attr->sl >= OPA_MAX_SLS)
1683                 goto bail;
1684         /* test the mapping for validity */
1685         ibp = to_iport(ibdev, ah_attr->port_num);
1686         ppd = ppd_from_ibp(ibp);
1687         sc5 = ibp->sl_to_sc[ah_attr->sl];
1688         dd = dd_from_ppd(ppd);
1689         if (sc_to_vlt(dd, sc5) > num_vls && sc_to_vlt(dd, sc5) != 0xf)
1690                 goto bail;
1691         return 0;
1692 bail:
1693         return -EINVAL;
1694 }
1695
1696 /**
1697  * create_ah - create an address handle
1698  * @pd: the protection domain
1699  * @ah_attr: the attributes of the AH
1700  *
1701  * This may be called from interrupt context.
1702  */
1703 static struct ib_ah *create_ah(struct ib_pd *pd,
1704                                struct ib_ah_attr *ah_attr)
1705 {
1706         struct hfi1_ah *ah;
1707         struct ib_ah *ret;
1708         struct hfi1_ibdev *dev = to_idev(pd->device);
1709         unsigned long flags;
1710
1711         if (hfi1_check_ah(pd->device, ah_attr)) {
1712                 ret = ERR_PTR(-EINVAL);
1713                 goto bail;
1714         }
1715
1716         ah = kmalloc(sizeof(*ah), GFP_ATOMIC);
1717         if (!ah) {
1718                 ret = ERR_PTR(-ENOMEM);
1719                 goto bail;
1720         }
1721
1722         spin_lock_irqsave(&dev->n_ahs_lock, flags);
1723         if (dev->n_ahs_allocated == hfi1_max_ahs) {
1724                 spin_unlock_irqrestore(&dev->n_ahs_lock, flags);
1725                 kfree(ah);
1726                 ret = ERR_PTR(-ENOMEM);
1727                 goto bail;
1728         }
1729
1730         dev->n_ahs_allocated++;
1731         spin_unlock_irqrestore(&dev->n_ahs_lock, flags);
1732
1733         /* ib_create_ah() will initialize ah->ibah. */
1734         ah->attr = *ah_attr;
1735         atomic_set(&ah->refcount, 0);
1736
1737         ret = &ah->ibah;
1738
1739 bail:
1740         return ret;
1741 }
1742
1743 struct ib_ah *hfi1_create_qp0_ah(struct hfi1_ibport *ibp, u16 dlid)
1744 {
1745         struct ib_ah_attr attr;
1746         struct ib_ah *ah = ERR_PTR(-EINVAL);
1747         struct hfi1_qp *qp0;
1748
1749         memset(&attr, 0, sizeof(attr));
1750         attr.dlid = dlid;
1751         attr.port_num = ppd_from_ibp(ibp)->port;
1752         rcu_read_lock();
1753         qp0 = rcu_dereference(ibp->qp[0]);
1754         if (qp0)
1755                 ah = ib_create_ah(qp0->ibqp.pd, &attr);
1756         rcu_read_unlock();
1757         return ah;
1758 }
1759
1760 /**
1761  * destroy_ah - destroy an address handle
1762  * @ibah: the AH to destroy
1763  *
1764  * This may be called from interrupt context.
1765  */
1766 static int destroy_ah(struct ib_ah *ibah)
1767 {
1768         struct hfi1_ibdev *dev = to_idev(ibah->device);
1769         struct hfi1_ah *ah = to_iah(ibah);
1770         unsigned long flags;
1771
1772         if (atomic_read(&ah->refcount) != 0)
1773                 return -EBUSY;
1774
1775         spin_lock_irqsave(&dev->n_ahs_lock, flags);
1776         dev->n_ahs_allocated--;
1777         spin_unlock_irqrestore(&dev->n_ahs_lock, flags);
1778
1779         kfree(ah);
1780
1781         return 0;
1782 }
1783
1784 static int modify_ah(struct ib_ah *ibah, struct ib_ah_attr *ah_attr)
1785 {
1786         struct hfi1_ah *ah = to_iah(ibah);
1787
1788         if (hfi1_check_ah(ibah->device, ah_attr))
1789                 return -EINVAL;
1790
1791         ah->attr = *ah_attr;
1792
1793         return 0;
1794 }
1795
1796 static int query_ah(struct ib_ah *ibah, struct ib_ah_attr *ah_attr)
1797 {
1798         struct hfi1_ah *ah = to_iah(ibah);
1799
1800         *ah_attr = ah->attr;
1801
1802         return 0;
1803 }
1804
1805 /**
1806  * hfi1_get_npkeys - return the size of the PKEY table for context 0
1807  * @dd: the hfi1_ib device
1808  */
1809 unsigned hfi1_get_npkeys(struct hfi1_devdata *dd)
1810 {
1811         return ARRAY_SIZE(dd->pport[0].pkeys);
1812 }
1813
1814 static int query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1815                       u16 *pkey)
1816 {
1817         struct hfi1_devdata *dd = dd_from_ibdev(ibdev);
1818         int ret;
1819
1820         if (index >= hfi1_get_npkeys(dd)) {
1821                 ret = -EINVAL;
1822                 goto bail;
1823         }
1824
1825         *pkey = hfi1_get_pkey(to_iport(ibdev, port), index);
1826         ret = 0;
1827
1828 bail:
1829         return ret;
1830 }
1831
1832 /**
1833  * alloc_ucontext - allocate a ucontest
1834  * @ibdev: the infiniband device
1835  * @udata: not used by the driver
1836  */
1837
1838 static struct ib_ucontext *alloc_ucontext(struct ib_device *ibdev,
1839                                           struct ib_udata *udata)
1840 {
1841         struct hfi1_ucontext *context;
1842         struct ib_ucontext *ret;
1843
1844         context = kmalloc(sizeof(*context), GFP_KERNEL);
1845         if (!context) {
1846                 ret = ERR_PTR(-ENOMEM);
1847                 goto bail;
1848         }
1849
1850         ret = &context->ibucontext;
1851
1852 bail:
1853         return ret;
1854 }
1855
1856 static int dealloc_ucontext(struct ib_ucontext *context)
1857 {
1858         kfree(to_iucontext(context));
1859         return 0;
1860 }
1861
1862 static void init_ibport(struct hfi1_pportdata *ppd)
1863 {
1864         struct hfi1_ibport *ibp = &ppd->ibport_data;
1865         size_t sz = ARRAY_SIZE(ibp->sl_to_sc);
1866         int i;
1867
1868         for (i = 0; i < sz; i++) {
1869                 ibp->sl_to_sc[i] = i;
1870                 ibp->sc_to_sl[i] = i;
1871         }
1872
1873         spin_lock_init(&ibp->lock);
1874         /* Set the prefix to the default value (see ch. 4.1.1) */
1875         ibp->gid_prefix = IB_DEFAULT_GID_PREFIX;
1876         ibp->sm_lid = 0;
1877         /* Below should only set bits defined in OPA PortInfo.CapabilityMask */
1878         ibp->port_cap_flags = IB_PORT_AUTO_MIGR_SUP |
1879                 IB_PORT_CAP_MASK_NOTICE_SUP;
1880         ibp->pma_counter_select[0] = IB_PMA_PORT_XMIT_DATA;
1881         ibp->pma_counter_select[1] = IB_PMA_PORT_RCV_DATA;
1882         ibp->pma_counter_select[2] = IB_PMA_PORT_XMIT_PKTS;
1883         ibp->pma_counter_select[3] = IB_PMA_PORT_RCV_PKTS;
1884         ibp->pma_counter_select[4] = IB_PMA_PORT_XMIT_WAIT;
1885
1886         RCU_INIT_POINTER(ibp->qp[0], NULL);
1887         RCU_INIT_POINTER(ibp->qp[1], NULL);
1888 }
1889
1890 static void verbs_txreq_kmem_cache_ctor(void *obj)
1891 {
1892         struct verbs_txreq *tx = obj;
1893
1894         memset(tx, 0, sizeof(*tx));
1895 }
1896
1897 /**
1898  * hfi1_register_ib_device - register our device with the infiniband core
1899  * @dd: the device data structure
1900  * Return 0 if successful, errno if unsuccessful.
1901  */
1902 int hfi1_register_ib_device(struct hfi1_devdata *dd)
1903 {
1904         struct hfi1_ibdev *dev = &dd->verbs_dev;
1905         struct ib_device *ibdev = &dev->ibdev;
1906         struct hfi1_pportdata *ppd = dd->pport;
1907         unsigned i, lk_tab_size;
1908         int ret;
1909         size_t lcpysz = IB_DEVICE_NAME_MAX;
1910         u16 descq_cnt;
1911         char buf[TXREQ_NAME_LEN];
1912
1913         ret = hfi1_qp_init(dev);
1914         if (ret)
1915                 goto err_qp_init;
1916
1917
1918         for (i = 0; i < dd->num_pports; i++)
1919                 init_ibport(ppd + i);
1920
1921         /* Only need to initialize non-zero fields. */
1922         spin_lock_init(&dev->n_pds_lock);
1923         spin_lock_init(&dev->n_ahs_lock);
1924         spin_lock_init(&dev->n_cqs_lock);
1925         spin_lock_init(&dev->n_qps_lock);
1926         spin_lock_init(&dev->n_srqs_lock);
1927         spin_lock_init(&dev->n_mcast_grps_lock);
1928         init_timer(&dev->mem_timer);
1929         dev->mem_timer.function = mem_timer;
1930         dev->mem_timer.data = (unsigned long) dev;
1931
1932         /*
1933          * The top hfi1_lkey_table_size bits are used to index the
1934          * table.  The lower 8 bits can be owned by the user (copied from
1935          * the LKEY).  The remaining bits act as a generation number or tag.
1936          */
1937         spin_lock_init(&dev->lk_table.lock);
1938         dev->lk_table.max = 1 << hfi1_lkey_table_size;
1939         /* ensure generation is at least 4 bits (keys.c) */
1940         if (hfi1_lkey_table_size > MAX_LKEY_TABLE_BITS) {
1941                 dd_dev_warn(dd, "lkey bits %u too large, reduced to %u\n",
1942                               hfi1_lkey_table_size, MAX_LKEY_TABLE_BITS);
1943                 hfi1_lkey_table_size = MAX_LKEY_TABLE_BITS;
1944         }
1945         lk_tab_size = dev->lk_table.max * sizeof(*dev->lk_table.table);
1946         dev->lk_table.table = (struct hfi1_mregion __rcu **)
1947                 vmalloc(lk_tab_size);
1948         if (dev->lk_table.table == NULL) {
1949                 ret = -ENOMEM;
1950                 goto err_lk;
1951         }
1952         RCU_INIT_POINTER(dev->dma_mr, NULL);
1953         for (i = 0; i < dev->lk_table.max; i++)
1954                 RCU_INIT_POINTER(dev->lk_table.table[i], NULL);
1955         INIT_LIST_HEAD(&dev->pending_mmaps);
1956         spin_lock_init(&dev->pending_lock);
1957         seqlock_init(&dev->iowait_lock);
1958         dev->mmap_offset = PAGE_SIZE;
1959         spin_lock_init(&dev->mmap_offset_lock);
1960         INIT_LIST_HEAD(&dev->txwait);
1961         INIT_LIST_HEAD(&dev->memwait);
1962
1963         descq_cnt = sdma_get_descq_cnt();
1964
1965         snprintf(buf, sizeof(buf), "hfi1_%u_vtxreq_cache", dd->unit);
1966         /* SLAB_HWCACHE_ALIGN for AHG */
1967         dev->verbs_txreq_cache = kmem_cache_create(buf,
1968                                                    sizeof(struct verbs_txreq),
1969                                                    0, SLAB_HWCACHE_ALIGN,
1970                                                    verbs_txreq_kmem_cache_ctor);
1971         if (!dev->verbs_txreq_cache) {
1972                 ret = -ENOMEM;
1973                 goto err_verbs_txreq;
1974         }
1975
1976         /*
1977          * The system image GUID is supposed to be the same for all
1978          * HFIs in a single system but since there can be other
1979          * device types in the system, we can't be sure this is unique.
1980          */
1981         if (!ib_hfi1_sys_image_guid)
1982                 ib_hfi1_sys_image_guid = cpu_to_be64(ppd->guid);
1983         lcpysz = strlcpy(ibdev->name, class_name(), lcpysz);
1984         strlcpy(ibdev->name + lcpysz, "_%d", IB_DEVICE_NAME_MAX - lcpysz);
1985         ibdev->owner = THIS_MODULE;
1986         ibdev->node_guid = cpu_to_be64(ppd->guid);
1987         ibdev->uverbs_abi_ver = HFI1_UVERBS_ABI_VERSION;
1988         ibdev->uverbs_cmd_mask =
1989                 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT)         |
1990                 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE)        |
1991                 (1ull << IB_USER_VERBS_CMD_QUERY_PORT)          |
1992                 (1ull << IB_USER_VERBS_CMD_ALLOC_PD)            |
1993                 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD)          |
1994                 (1ull << IB_USER_VERBS_CMD_CREATE_AH)           |
1995                 (1ull << IB_USER_VERBS_CMD_MODIFY_AH)           |
1996                 (1ull << IB_USER_VERBS_CMD_QUERY_AH)            |
1997                 (1ull << IB_USER_VERBS_CMD_DESTROY_AH)          |
1998                 (1ull << IB_USER_VERBS_CMD_REG_MR)              |
1999                 (1ull << IB_USER_VERBS_CMD_DEREG_MR)            |
2000                 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
2001                 (1ull << IB_USER_VERBS_CMD_CREATE_CQ)           |
2002                 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ)           |
2003                 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ)          |
2004                 (1ull << IB_USER_VERBS_CMD_POLL_CQ)             |
2005                 (1ull << IB_USER_VERBS_CMD_REQ_NOTIFY_CQ)       |
2006                 (1ull << IB_USER_VERBS_CMD_CREATE_QP)           |
2007                 (1ull << IB_USER_VERBS_CMD_QUERY_QP)            |
2008                 (1ull << IB_USER_VERBS_CMD_MODIFY_QP)           |
2009                 (1ull << IB_USER_VERBS_CMD_DESTROY_QP)          |
2010                 (1ull << IB_USER_VERBS_CMD_POST_SEND)           |
2011                 (1ull << IB_USER_VERBS_CMD_POST_RECV)           |
2012                 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST)        |
2013                 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST)        |
2014                 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ)          |
2015                 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ)          |
2016                 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ)           |
2017                 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ)         |
2018                 (1ull << IB_USER_VERBS_CMD_POST_SRQ_RECV);
2019         ibdev->node_type = RDMA_NODE_IB_CA;
2020         ibdev->phys_port_cnt = dd->num_pports;
2021         ibdev->num_comp_vectors = 1;
2022         ibdev->dma_device = &dd->pcidev->dev;
2023         ibdev->query_device = query_device;
2024         ibdev->modify_device = modify_device;
2025         ibdev->query_port = query_port;
2026         ibdev->modify_port = modify_port;
2027         ibdev->query_pkey = query_pkey;
2028         ibdev->query_gid = query_gid;
2029         ibdev->alloc_ucontext = alloc_ucontext;
2030         ibdev->dealloc_ucontext = dealloc_ucontext;
2031         ibdev->alloc_pd = alloc_pd;
2032         ibdev->dealloc_pd = dealloc_pd;
2033         ibdev->create_ah = create_ah;
2034         ibdev->destroy_ah = destroy_ah;
2035         ibdev->modify_ah = modify_ah;
2036         ibdev->query_ah = query_ah;
2037         ibdev->create_srq = hfi1_create_srq;
2038         ibdev->modify_srq = hfi1_modify_srq;
2039         ibdev->query_srq = hfi1_query_srq;
2040         ibdev->destroy_srq = hfi1_destroy_srq;
2041         ibdev->create_qp = hfi1_create_qp;
2042         ibdev->modify_qp = hfi1_modify_qp;
2043         ibdev->query_qp = hfi1_query_qp;
2044         ibdev->destroy_qp = hfi1_destroy_qp;
2045         ibdev->post_send = post_send;
2046         ibdev->post_recv = post_receive;
2047         ibdev->post_srq_recv = hfi1_post_srq_receive;
2048         ibdev->create_cq = hfi1_create_cq;
2049         ibdev->destroy_cq = hfi1_destroy_cq;
2050         ibdev->resize_cq = hfi1_resize_cq;
2051         ibdev->poll_cq = hfi1_poll_cq;
2052         ibdev->req_notify_cq = hfi1_req_notify_cq;
2053         ibdev->get_dma_mr = hfi1_get_dma_mr;
2054         ibdev->reg_phys_mr = hfi1_reg_phys_mr;
2055         ibdev->reg_user_mr = hfi1_reg_user_mr;
2056         ibdev->dereg_mr = hfi1_dereg_mr;
2057         ibdev->alloc_mr = hfi1_alloc_mr;
2058         ibdev->alloc_fast_reg_page_list = hfi1_alloc_fast_reg_page_list;
2059         ibdev->free_fast_reg_page_list = hfi1_free_fast_reg_page_list;
2060         ibdev->alloc_fmr = hfi1_alloc_fmr;
2061         ibdev->map_phys_fmr = hfi1_map_phys_fmr;
2062         ibdev->unmap_fmr = hfi1_unmap_fmr;
2063         ibdev->dealloc_fmr = hfi1_dealloc_fmr;
2064         ibdev->attach_mcast = hfi1_multicast_attach;
2065         ibdev->detach_mcast = hfi1_multicast_detach;
2066         ibdev->process_mad = hfi1_process_mad;
2067         ibdev->mmap = hfi1_mmap;
2068         ibdev->dma_ops = &hfi1_dma_mapping_ops;
2069         ibdev->get_port_immutable = port_immutable;
2070
2071         strncpy(ibdev->node_desc, init_utsname()->nodename,
2072                 sizeof(ibdev->node_desc));
2073
2074         ret = ib_register_device(ibdev, hfi1_create_port_files);
2075         if (ret)
2076                 goto err_reg;
2077
2078         ret = hfi1_create_agents(dev);
2079         if (ret)
2080                 goto err_agents;
2081
2082         ret = hfi1_verbs_register_sysfs(dd);
2083         if (ret)
2084                 goto err_class;
2085
2086         goto bail;
2087
2088 err_class:
2089         hfi1_free_agents(dev);
2090 err_agents:
2091         ib_unregister_device(ibdev);
2092 err_reg:
2093 err_verbs_txreq:
2094         kmem_cache_destroy(dev->verbs_txreq_cache);
2095         vfree(dev->lk_table.table);
2096 err_lk:
2097         hfi1_qp_exit(dev);
2098 err_qp_init:
2099         dd_dev_err(dd, "cannot register verbs: %d!\n", -ret);
2100 bail:
2101         return ret;
2102 }
2103
2104 void hfi1_unregister_ib_device(struct hfi1_devdata *dd)
2105 {
2106         struct hfi1_ibdev *dev = &dd->verbs_dev;
2107         struct ib_device *ibdev = &dev->ibdev;
2108
2109         hfi1_verbs_unregister_sysfs(dd);
2110
2111         hfi1_free_agents(dev);
2112
2113         ib_unregister_device(ibdev);
2114
2115         if (!list_empty(&dev->txwait))
2116                 dd_dev_err(dd, "txwait list not empty!\n");
2117         if (!list_empty(&dev->memwait))
2118                 dd_dev_err(dd, "memwait list not empty!\n");
2119         if (dev->dma_mr)
2120                 dd_dev_err(dd, "DMA MR not NULL!\n");
2121
2122         hfi1_qp_exit(dev);
2123         del_timer_sync(&dev->mem_timer);
2124         kmem_cache_destroy(dev->verbs_txreq_cache);
2125         vfree(dev->lk_table.table);
2126 }
2127
2128 /*
2129  * This must be called with s_lock held.
2130  */
2131 void hfi1_schedule_send(struct hfi1_qp *qp)
2132 {
2133         if (hfi1_send_ok(qp)) {
2134                 struct hfi1_ibport *ibp =
2135                         to_iport(qp->ibqp.device, qp->port_num);
2136                 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
2137
2138                 iowait_schedule(&qp->s_iowait, ppd->hfi1_wq);
2139         }
2140 }
2141
2142 void hfi1_cnp_rcv(struct hfi1_packet *packet)
2143 {
2144         struct hfi1_ibport *ibp = &packet->rcd->ppd->ibport_data;
2145
2146         if (packet->qp->ibqp.qp_type == IB_QPT_UC)
2147                 hfi1_uc_rcv(packet);
2148         else if (packet->qp->ibqp.qp_type == IB_QPT_UD)
2149                 hfi1_ud_rcv(packet);
2150         else
2151                 ibp->n_pkt_drops++;
2152 }