drivers/pinctrl/pinctrl-rockchip.c

   1 /*
   2  * Pinctrl driver for Rockchip SoCs
   3  *
   4  * Copyright (c) 2013 MundoReader S.L.
   5  * Author: Heiko Stuebner <heiko@sntech.de>
   6  *
   7  * With some ideas taken from pinctrl-samsung:
   8  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   9  *              http://www.samsung.com
  10  * Copyright (c) 2012 Linaro Ltd
  11  *              http://www.linaro.org
  12  *
  13  * and pinctrl-at91:
  14  * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as published
  18  * by the Free Software Foundation.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  */
  25
  26 #include <linux/module.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/io.h>
  29 #include <linux/bitops.h>
  30 #include <linux/gpio.h>
  31 #include <linux/of_address.h>
  32 #include <linux/of_irq.h>
  33 #include <linux/pinctrl/machine.h>
  34 #include <linux/pinctrl/pinconf.h>
  35 #include <linux/pinctrl/pinctrl.h>
  36 #include <linux/pinctrl/pinmux.h>
  37 #include <linux/pinctrl/pinconf-generic.h>
  38 #include <linux/irqchip/chained_irq.h>
  39 #include <linux/clk.h>
  40 #include <dt-bindings/pinctrl/rockchip.h>
  41
  42 #include "core.h"
  43 #include "pinconf.h"
  44
  45 /* GPIO control registers */
  46 #define GPIO_SWPORT_DR          0x00
  47 #define GPIO_SWPORT_DDR         0x04
  48 #define GPIO_INTEN              0x30
  49 #define GPIO_INTMASK            0x34
  50 #define GPIO_INTTYPE_LEVEL      0x38
  51 #define GPIO_INT_POLARITY       0x3c
  52 #define GPIO_INT_STATUS         0x40
  53 #define GPIO_INT_RAWSTATUS      0x44
  54 #define GPIO_DEBOUNCE           0x48
  55 #define GPIO_PORTS_EOI          0x4c
  56 #define GPIO_EXT_PORT           0x50
  57 #define GPIO_LS_SYNC            0x60
  58
  59 enum rockchip_pinctrl_type {
  60         RK2928,
  61         RK3066B,
  62         RK3188,
  63 };
  64
  65 enum rockchip_pin_bank_type {
  66         COMMON_BANK,
  67         RK3188_BANK0,
  68 };
  69
  70 /**
  71  * @reg_base: register base of the gpio bank
  72  * @reg_pull: optional separate register for additional pull settings
  73  * @clk: clock of the gpio bank
  74  * @irq: interrupt of the gpio bank
  75  * @pin_base: first pin number
  76  * @nr_pins: number of pins in this bank
  77  * @name: name of the bank
  78  * @bank_num: number of the bank, to account for holes
  79  * @valid: are all necessary informations present
  80  * @of_node: dt node of this bank
  81  * @drvdata: common pinctrl basedata
  82  * @domain: irqdomain of the gpio bank
  83  * @gpio_chip: gpiolib chip
  84  * @grange: gpio range
  85  * @slock: spinlock for the gpio bank
  86  */
  87 struct rockchip_pin_bank {
  88         void __iomem                    *reg_base;
  89         void __iomem                    *reg_pull;
  90         struct clk                      *clk;
  91         int                             irq;
  92         u32                             pin_base;
  93         u8                              nr_pins;
  94         char                            *name;
  95         u8                              bank_num;
  96         enum rockchip_pin_bank_type     bank_type;
  97         bool                            valid;
  98         struct device_node              *of_node;
  99         struct rockchip_pinctrl         *drvdata;
 100         struct irq_domain               *domain;
 101         struct gpio_chip                gpio_chip;
 102         struct pinctrl_gpio_range       grange;
 103         spinlock_t                      slock;
 104         u32                             toggle_edge_mode;
 105 };
 106
 107 #define PIN_BANK(id, pins, label)                       \
 108         {                                               \
 109                 .bank_num       = id,                   \
 110                 .nr_pins        = pins,                 \
 111                 .name           = label,                \
 112         }
 113
 114 /**
 115  */
 116 struct rockchip_pin_ctrl {
 117         struct rockchip_pin_bank        *pin_banks;
 118         u32                             nr_banks;
 119         u32                             nr_pins;
 120         char                            *label;
 121         enum rockchip_pinctrl_type      type;
 122         int                             mux_offset;
 123         void    (*pull_calc_reg)(struct rockchip_pin_bank *bank, int pin_num,
 124                                  void __iomem **reg, u8 *bit);
 125 };
 126
 127 struct rockchip_pin_config {
 128         unsigned int            func;
 129         unsigned long           *configs;
 130         unsigned int            nconfigs;
 131 };
 132
 133 /**
 134  * struct rockchip_pin_group: represent group of pins of a pinmux function.
 135  * @name: name of the pin group, used to lookup the group.
 136  * @pins: the pins included in this group.
 137  * @npins: number of pins included in this group.
 138  * @func: the mux function number to be programmed when selected.
 139  * @configs: the config values to be set for each pin
 140  * @nconfigs: number of configs for each pin
 141  */
 142 struct rockchip_pin_group {
 143         const char                      *name;
 144         unsigned int                    npins;
 145         unsigned int                    *pins;
 146         struct rockchip_pin_config      *data;
 147 };
 148
 149 /**
 150  * struct rockchip_pmx_func: represent a pin function.
 151  * @name: name of the pin function, used to lookup the function.
 152  * @groups: one or more names of pin groups that provide this function.
 153  * @num_groups: number of groups included in @groups.
 154  */
 155 struct rockchip_pmx_func {
 156         const char              *name;
 157         const char              **groups;
 158         u8                      ngroups;
 159 };
 160
 161 struct rockchip_pinctrl {
 162         void __iomem                    *reg_base;
 163         void __iomem                    *reg_pull;
 164         struct device                   *dev;
 165         struct rockchip_pin_ctrl        *ctrl;
 166         struct pinctrl_desc             pctl;
 167         struct pinctrl_dev              *pctl_dev;
 168         struct rockchip_pin_group       *groups;
 169         unsigned int                    ngroups;
 170         struct rockchip_pmx_func        *functions;
 171         unsigned int                    nfunctions;
 172 };
 173
 174 static inline struct rockchip_pin_bank *gc_to_pin_bank(struct gpio_chip *gc)
 175 {
 176         return container_of(gc, struct rockchip_pin_bank, gpio_chip);
 177 }
 178
 179 static const inline struct rockchip_pin_group *pinctrl_name_to_group(
 180                                         const struct rockchip_pinctrl *info,
 181                                         const char *name)
 182 {
 183         int i;
 184
 185         for (i = 0; i < info->ngroups; i++) {
 186                 if (!strcmp(info->groups[i].name, name))
 187                         return &info->groups[i];
 188         }
 189
 190         return NULL;
 191 }
 192
 193 /*
 194  * given a pin number that is local to a pin controller, find out the pin bank
 195  * and the register base of the pin bank.
 196  */
 197 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
 198                                                                 unsigned pin)
 199 {
 200         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 201
 202         while (pin >= (b->pin_base + b->nr_pins))
 203                 b++;
 204
 205         return b;
 206 }
 207
 208 static struct rockchip_pin_bank *bank_num_to_bank(
 209                                         struct rockchip_pinctrl *info,
 210                                         unsigned num)
 211 {
 212         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 213         int i;
 214
 215         for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
 216                 if (b->bank_num == num)
 217                         return b;
 218         }
 219
 220         return ERR_PTR(-EINVAL);
 221 }
 222
 223 /*
 224  * Pinctrl_ops handling
 225  */
 226
 227 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
 228 {
 229         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 230
 231         return info->ngroups;
 232 }
 233
 234 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
 235                                                         unsigned selector)
 236 {
 237         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 238
 239         return info->groups[selector].name;
 240 }
 241
 242 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
 243                                       unsigned selector, const unsigned **pins,
 244                                       unsigned *npins)
 245 {
 246         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 247
 248         if (selector >= info->ngroups)
 249                 return -EINVAL;
 250
 251         *pins = info->groups[selector].pins;
 252         *npins = info->groups[selector].npins;
 253
 254         return 0;
 255 }
 256
 257 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
 258                                  struct device_node *np,
 259                                  struct pinctrl_map **map, unsigned *num_maps)
 260 {
 261         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 262         const struct rockchip_pin_group *grp;
 263         struct pinctrl_map *new_map;
 264         struct device_node *parent;
 265         int map_num = 1;
 266         int i;
 267
 268         /*
 269          * first find the group of this node and check if we need to create
 270          * config maps for pins
 271          */
 272         grp = pinctrl_name_to_group(info, np->name);
 273         if (!grp) {
 274                 dev_err(info->dev, "unable to find group for node %s\n",
 275                         np->name);
 276                 return -EINVAL;
 277         }
 278
 279         map_num += grp->npins;
 280         new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num,
 281                                                                 GFP_KERNEL);
 282         if (!new_map)
 283                 return -ENOMEM;
 284
 285         *map = new_map;
 286         *num_maps = map_num;
 287
 288         /* create mux map */
 289         parent = of_get_parent(np);
 290         if (!parent) {
 291                 devm_kfree(pctldev->dev, new_map);
 292                 return -EINVAL;
 293         }
 294         new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
 295         new_map[0].data.mux.function = parent->name;
 296         new_map[0].data.mux.group = np->name;
 297         of_node_put(parent);
 298
 299         /* create config map */
 300         new_map++;
 301         for (i = 0; i < grp->npins; i++) {
 302                 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
 303                 new_map[i].data.configs.group_or_pin =
 304                                 pin_get_name(pctldev, grp->pins[i]);
 305                 new_map[i].data.configs.configs = grp->data[i].configs;
 306                 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
 307         }
 308
 309         dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
 310                 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
 311
 312         return 0;
 313 }
 314
 315 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
 316                                     struct pinctrl_map *map, unsigned num_maps)
 317 {
 318 }
 319
 320 static const struct pinctrl_ops rockchip_pctrl_ops = {
 321         .get_groups_count       = rockchip_get_groups_count,
 322         .get_group_name         = rockchip_get_group_name,
 323         .get_group_pins         = rockchip_get_group_pins,
 324         .dt_node_to_map         = rockchip_dt_node_to_map,
 325         .dt_free_map            = rockchip_dt_free_map,
 326 };
 327
 328 /*
 329  * Hardware access
 330  */
 331
 332 /*
 333  * Set a new mux function for a pin.
 334  *
 335  * The register is divided into the upper and lower 16 bit. When changing
 336  * a value, the previous register value is not read and changed. Instead
 337  * it seems the changed bits are marked in the upper 16 bit, while the
 338  * changed value gets set in the same offset in the lower 16 bit.
 339  * All pin settings seem to be 2 bit wide in both the upper and lower
 340  * parts.
 341  * @bank: pin bank to change
 342  * @pin: pin to change
 343  * @mux: new mux function to set
 344  */
 345 static void rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
 346 {
 347         struct rockchip_pinctrl *info = bank->drvdata;
 348         void __iomem *reg = info->reg_base + info->ctrl->mux_offset;
 349         unsigned long flags;
 350         u8 bit;
 351         u32 data;
 352
 353         dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
 354                                                 bank->bank_num, pin, mux);
 355
 356         /* get basic quadrupel of mux registers and the correct reg inside */
 357         reg += bank->bank_num * 0x10;
 358         reg += (pin / 8) * 4;
 359         bit = (pin % 8) * 2;
 360
 361         spin_lock_irqsave(&bank->slock, flags);
 362
 363         data = (3 << (bit + 16));
 364         data |= (mux & 3) << bit;
 365         writel(data, reg);
 366
 367         spin_unlock_irqrestore(&bank->slock, flags);
 368 }
 369
 370 #define RK2928_PULL_OFFSET              0x118
 371 #define RK2928_PULL_PINS_PER_REG        16
 372 #define RK2928_PULL_BANK_STRIDE         8
 373
 374 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 375                                     int pin_num, void __iomem **reg, u8 *bit)
 376 {
 377         struct rockchip_pinctrl *info = bank->drvdata;
 378
 379         *reg = info->reg_base + RK2928_PULL_OFFSET;
 380         *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
 381         *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
 382
 383         *bit = pin_num % RK2928_PULL_PINS_PER_REG;
 384 };
 385
 386 #define RK3188_PULL_BITS_PER_PIN        2
 387 #define RK3188_PULL_PINS_PER_REG        8
 388 #define RK3188_PULL_BANK_STRIDE         16
 389
 390 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 391                                     int pin_num, void __iomem **reg, u8 *bit)
 392 {
 393         struct rockchip_pinctrl *info = bank->drvdata;
 394
 395         /* The first 12 pins of the first bank are located elsewhere */
 396         if (bank->bank_type == RK3188_BANK0 && pin_num < 12) {
 397                 *reg = bank->reg_pull +
 398                                 ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 399                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
 400                 *bit *= RK3188_PULL_BITS_PER_PIN;
 401         } else {
 402                 *reg = info->reg_pull - 4;
 403                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
 404                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 405
 406                 /*
 407                  * The bits in these registers have an inverse ordering
 408                  * with the lowest pin being in bits 15:14 and the highest
 409                  * pin in bits 1:0
 410                  */
 411                 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
 412                 *bit *= RK3188_PULL_BITS_PER_PIN;
 413         }
 414 }
 415
 416 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
 417 {
 418         struct rockchip_pinctrl *info = bank->drvdata;
 419         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 420         void __iomem *reg;
 421         u8 bit;
 422         u32 data;
 423
 424         /* rk3066b does support any pulls */
 425         if (ctrl->type == RK3066B)
 426                 return PIN_CONFIG_BIAS_DISABLE;
 427
 428         ctrl->pull_calc_reg(bank, pin_num, &reg, &bit);
 429
 430         switch (ctrl->type) {
 431         case RK2928:
 432                 return !(readl_relaxed(reg) & BIT(bit))
 433                                 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
 434                                 : PIN_CONFIG_BIAS_DISABLE;
 435         case RK3188:
 436                 data = readl_relaxed(reg) >> bit;
 437                 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
 438
 439                 switch (data) {
 440                 case 0:
 441                         return PIN_CONFIG_BIAS_DISABLE;
 442                 case 1:
 443                         return PIN_CONFIG_BIAS_PULL_UP;
 444                 case 2:
 445                         return PIN_CONFIG_BIAS_PULL_DOWN;
 446                 case 3:
 447                         return PIN_CONFIG_BIAS_BUS_HOLD;
 448                 }
 449
 450                 dev_err(info->dev, "unknown pull setting\n");
 451                 return -EIO;
 452         default:
 453                 dev_err(info->dev, "unsupported pinctrl type\n");
 454                 return -EINVAL;
 455         };
 456 }
 457
 458 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
 459                                         int pin_num, int pull)
 460 {
 461         struct rockchip_pinctrl *info = bank->drvdata;
 462         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 463         void __iomem *reg;
 464         unsigned long flags;
 465         u8 bit;
 466         u32 data;
 467
 468         dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
 469                  bank->bank_num, pin_num, pull);
 470
 471         /* rk3066b does support any pulls */
 472         if (ctrl->type == RK3066B)
 473                 return pull ? -EINVAL : 0;
 474
 475         ctrl->pull_calc_reg(bank, pin_num, &reg, &bit);
 476
 477         switch (ctrl->type) {
 478         case RK2928:
 479                 spin_lock_irqsave(&bank->slock, flags);
 480
 481                 data = BIT(bit + 16);
 482                 if (pull == PIN_CONFIG_BIAS_DISABLE)
 483                         data |= BIT(bit);
 484                 writel(data, reg);
 485
 486                 spin_unlock_irqrestore(&bank->slock, flags);
 487                 break;
 488         case RK3188:
 489                 spin_lock_irqsave(&bank->slock, flags);
 490
 491                 /* enable the write to the equivalent lower bits */
 492                 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
 493
 494                 switch (pull) {
 495                 case PIN_CONFIG_BIAS_DISABLE:
 496                         break;
 497                 case PIN_CONFIG_BIAS_PULL_UP:
 498                         data |= (1 << bit);
 499                         break;
 500                 case PIN_CONFIG_BIAS_PULL_DOWN:
 501                         data |= (2 << bit);
 502                         break;
 503                 case PIN_CONFIG_BIAS_BUS_HOLD:
 504                         data |= (3 << bit);
 505                         break;
 506                 default:
 507                         dev_err(info->dev, "unsupported pull setting %d\n",
 508                                 pull);
 509                         return -EINVAL;
 510                 }
 511
 512                 writel(data, reg);
 513
 514                 spin_unlock_irqrestore(&bank->slock, flags);
 515                 break;
 516         default:
 517                 dev_err(info->dev, "unsupported pinctrl type\n");
 518                 return -EINVAL;
 519         }
 520
 521         return 0;
 522 }
 523
 524 /*
 525  * Pinmux_ops handling
 526  */
 527
 528 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
 529 {
 530         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 531
 532         return info->nfunctions;
 533 }
 534
 535 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
 536                                           unsigned selector)
 537 {
 538         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 539
 540         return info->functions[selector].name;
 541 }
 542
 543 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
 544                                 unsigned selector, const char * const **groups,
 545                                 unsigned * const num_groups)
 546 {
 547         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 548
 549         *groups = info->functions[selector].groups;
 550         *num_groups = info->functions[selector].ngroups;
 551
 552         return 0;
 553 }
 554
 555 static int rockchip_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
 556                                                             unsigned group)
 557 {
 558         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 559         const unsigned int *pins = info->groups[group].pins;
 560         const struct rockchip_pin_config *data = info->groups[group].data;
 561         struct rockchip_pin_bank *bank;
 562         int cnt;
 563
 564         dev_dbg(info->dev, "enable function %s group %s\n",
 565                 info->functions[selector].name, info->groups[group].name);
 566
 567         /*
 568          * for each pin in the pin group selected, program the correspoding pin
 569          * pin function number in the config register.
 570          */
 571         for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
 572                 bank = pin_to_bank(info, pins[cnt]);
 573                 rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
 574                                  data[cnt].func);
 575         }
 576
 577         return 0;
 578 }
 579
 580 static void rockchip_pmx_disable(struct pinctrl_dev *pctldev,
 581                                         unsigned selector, unsigned group)
 582 {
 583         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 584         const unsigned int *pins = info->groups[group].pins;
 585         struct rockchip_pin_bank *bank;
 586         int cnt;
 587
 588         dev_dbg(info->dev, "disable function %s group %s\n",
 589                 info->functions[selector].name, info->groups[group].name);
 590
 591         for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
 592                 bank = pin_to_bank(info, pins[cnt]);
 593                 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
 594         }
 595 }
 596
 597 /*
 598  * The calls to gpio_direction_output() and gpio_direction_input()
 599  * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
 600  * function called from the gpiolib interface).
 601  */
 602 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
 603                                               struct pinctrl_gpio_range *range,
 604                                               unsigned offset, bool input)
 605 {
 606         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 607         struct rockchip_pin_bank *bank;
 608         struct gpio_chip *chip;
 609         int pin;
 610         u32 data;
 611
 612         chip = range->gc;
 613         bank = gc_to_pin_bank(chip);
 614         pin = offset - chip->base;
 615
 616         dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
 617                  offset, range->name, pin, input ? "input" : "output");
 618
 619         rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
 620
 621         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
 622         /* set bit to 1 for output, 0 for input */
 623         if (!input)
 624                 data |= BIT(pin);
 625         else
 626                 data &= ~BIT(pin);
 627         writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
 628
 629         return 0;
 630 }
 631
 632 static const struct pinmux_ops rockchip_pmx_ops = {
 633         .get_functions_count    = rockchip_pmx_get_funcs_count,
 634         .get_function_name      = rockchip_pmx_get_func_name,
 635         .get_function_groups    = rockchip_pmx_get_groups,
 636         .enable                 = rockchip_pmx_enable,
 637         .disable                = rockchip_pmx_disable,
 638         .gpio_set_direction     = rockchip_pmx_gpio_set_direction,
 639 };
 640
 641 /*
 642  * Pinconf_ops handling
 643  */
 644
 645 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
 646                                         enum pin_config_param pull)
 647 {
 648         switch (ctrl->type) {
 649         case RK2928:
 650                 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
 651                                         pull == PIN_CONFIG_BIAS_DISABLE);
 652         case RK3066B:
 653                 return pull ? false : true;
 654         case RK3188:
 655                 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
 656         }
 657
 658         return false;
 659 }
 660
 661 /* set the pin config settings for a specified pin */
 662 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
 663                                 unsigned long *configs, unsigned num_configs)
 664 {
 665         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 666         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
 667         enum pin_config_param param;
 668         u16 arg;
 669         int i;
 670         int rc;
 671
 672         for (i = 0; i < num_configs; i++) {
 673                 param = pinconf_to_config_param(configs[i]);
 674                 arg = pinconf_to_config_argument(configs[i]);
 675
 676                 switch (param) {
 677                 case PIN_CONFIG_BIAS_DISABLE:
 678                         rc =  rockchip_set_pull(bank, pin - bank->pin_base,
 679                                 param);
 680                         if (rc)
 681                                 return rc;
 682                         break;
 683                 case PIN_CONFIG_BIAS_PULL_UP:
 684                 case PIN_CONFIG_BIAS_PULL_DOWN:
 685                 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
 686                 case PIN_CONFIG_BIAS_BUS_HOLD:
 687                         if (!rockchip_pinconf_pull_valid(info->ctrl, param))
 688                                 return -ENOTSUPP;
 689
 690                         if (!arg)
 691                                 return -EINVAL;
 692
 693                         rc = rockchip_set_pull(bank, pin - bank->pin_base,
 694                                 param);
 695                         if (rc)
 696                                 return rc;
 697                         break;
 698                 default:
 699                         return -ENOTSUPP;
 700                         break;
 701                 }
 702         } /* for each config */
 703
 704         return 0;
 705 }
 706
 707 /* get the pin config settings for a specified pin */
 708 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
 709                                                         unsigned long *config)
 710 {
 711         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 712         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
 713         enum pin_config_param param = pinconf_to_config_param(*config);
 714
 715         switch (param) {
 716         case PIN_CONFIG_BIAS_DISABLE:
 717                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
 718                         return -EINVAL;
 719
 720                 *config = 0;
 721                 break;
 722         case PIN_CONFIG_BIAS_PULL_UP:
 723         case PIN_CONFIG_BIAS_PULL_DOWN:
 724         case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
 725         case PIN_CONFIG_BIAS_BUS_HOLD:
 726                 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
 727                         return -ENOTSUPP;
 728
 729                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
 730                         return -EINVAL;
 731
 732                 *config = 1;
 733                 break;
 734         default:
 735                 return -ENOTSUPP;
 736                 break;
 737         }
 738
 739         return 0;
 740 }
 741
 742 static const struct pinconf_ops rockchip_pinconf_ops = {
 743         .pin_config_get                 = rockchip_pinconf_get,
 744         .pin_config_set                 = rockchip_pinconf_set,
 745 };
 746
 747 static const struct of_device_id rockchip_bank_match[] = {
 748         { .compatible = "rockchip,gpio-bank" },
 749         { .compatible = "rockchip,rk3188-gpio-bank0" },
 750         {},
 751 };
 752
 753 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
 754                                                 struct device_node *np)
 755 {
 756         struct device_node *child;
 757
 758         for_each_child_of_node(np, child) {
 759                 if (of_match_node(rockchip_bank_match, child))
 760                         continue;
 761
 762                 info->nfunctions++;
 763                 info->ngroups += of_get_child_count(child);
 764         }
 765 }
 766
 767 static int rockchip_pinctrl_parse_groups(struct device_node *np,
 768                                               struct rockchip_pin_group *grp,
 769                                               struct rockchip_pinctrl *info,
 770                                               u32 index)
 771 {
 772         struct rockchip_pin_bank *bank;
 773         int size;
 774         const __be32 *list;
 775         int num;
 776         int i, j;
 777         int ret;
 778
 779         dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
 780
 781         /* Initialise group */
 782         grp->name = np->name;
 783
 784         /*
 785          * the binding format is rockchip,pins = <bank pin mux CONFIG>,
 786          * do sanity check and calculate pins number
 787          */
 788         list = of_get_property(np, "rockchip,pins", &size);
 789         /* we do not check return since it's safe node passed down */
 790         size /= sizeof(*list);
 791         if (!size || size % 4) {
 792                 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
 793                 return -EINVAL;
 794         }
 795
 796         grp->npins = size / 4;
 797
 798         grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
 799                                                 GFP_KERNEL);
 800         grp->data = devm_kzalloc(info->dev, grp->npins *
 801                                           sizeof(struct rockchip_pin_config),
 802                                         GFP_KERNEL);
 803         if (!grp->pins || !grp->data)
 804                 return -ENOMEM;
 805
 806         for (i = 0, j = 0; i < size; i += 4, j++) {
 807                 const __be32 *phandle;
 808                 struct device_node *np_config;
 809
 810                 num = be32_to_cpu(*list++);
 811                 bank = bank_num_to_bank(info, num);
 812                 if (IS_ERR(bank))
 813                         return PTR_ERR(bank);
 814
 815                 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
 816                 grp->data[j].func = be32_to_cpu(*list++);
 817
 818                 phandle = list++;
 819                 if (!phandle)
 820                         return -EINVAL;
 821
 822                 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
 823                 ret = pinconf_generic_parse_dt_config(np_config,
 824                                 &grp->data[j].configs, &grp->data[j].nconfigs);
 825                 if (ret)
 826                         return ret;
 827         }
 828
 829         return 0;
 830 }
 831
 832 static int rockchip_pinctrl_parse_functions(struct device_node *np,
 833                                                 struct rockchip_pinctrl *info,
 834                                                 u32 index)
 835 {
 836         struct device_node *child;
 837         struct rockchip_pmx_func *func;
 838         struct rockchip_pin_group *grp;
 839         int ret;
 840         static u32 grp_index;
 841         u32 i = 0;
 842
 843         dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
 844
 845         func = &info->functions[index];
 846
 847         /* Initialise function */
 848         func->name = np->name;
 849         func->ngroups = of_get_child_count(np);
 850         if (func->ngroups <= 0)
 851                 return 0;
 852
 853         func->groups = devm_kzalloc(info->dev,
 854                         func->ngroups * sizeof(char *), GFP_KERNEL);
 855         if (!func->groups)
 856                 return -ENOMEM;
 857
 858         for_each_child_of_node(np, child) {
 859                 func->groups[i] = child->name;
 860                 grp = &info->groups[grp_index++];
 861                 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
 862                 if (ret)
 863                         return ret;
 864         }
 865
 866         return 0;
 867 }
 868
 869 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
 870                                               struct rockchip_pinctrl *info)
 871 {
 872         struct device *dev = &pdev->dev;
 873         struct device_node *np = dev->of_node;
 874         struct device_node *child;
 875         int ret;
 876         int i;
 877
 878         rockchip_pinctrl_child_count(info, np);
 879
 880         dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
 881         dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
 882
 883         info->functions = devm_kzalloc(dev, info->nfunctions *
 884                                               sizeof(struct rockchip_pmx_func),
 885                                               GFP_KERNEL);
 886         if (!info->functions) {
 887                 dev_err(dev, "failed to allocate memory for function list\n");
 888                 return -EINVAL;
 889         }
 890
 891         info->groups = devm_kzalloc(dev, info->ngroups *
 892                                             sizeof(struct rockchip_pin_group),
 893                                             GFP_KERNEL);
 894         if (!info->groups) {
 895                 dev_err(dev, "failed allocate memory for ping group list\n");
 896                 return -EINVAL;
 897         }
 898
 899         i = 0;
 900
 901         for_each_child_of_node(np, child) {
 902                 if (of_match_node(rockchip_bank_match, child))
 903                         continue;
 904
 905                 ret = rockchip_pinctrl_parse_functions(child, info, i++);
 906                 if (ret) {
 907                         dev_err(&pdev->dev, "failed to parse function\n");
 908                         return ret;
 909                 }
 910         }
 911
 912         return 0;
 913 }
 914
 915 static int rockchip_pinctrl_register(struct platform_device *pdev,
 916                                         struct rockchip_pinctrl *info)
 917 {
 918         struct pinctrl_desc *ctrldesc = &info->pctl;
 919         struct pinctrl_pin_desc *pindesc, *pdesc;
 920         struct rockchip_pin_bank *pin_bank;
 921         int pin, bank, ret;
 922         int k;
 923
 924         ctrldesc->name = "rockchip-pinctrl";
 925         ctrldesc->owner = THIS_MODULE;
 926         ctrldesc->pctlops = &rockchip_pctrl_ops;
 927         ctrldesc->pmxops = &rockchip_pmx_ops;
 928         ctrldesc->confops = &rockchip_pinconf_ops;
 929
 930         pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
 931                         info->ctrl->nr_pins, GFP_KERNEL);
 932         if (!pindesc) {
 933                 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
 934                 return -ENOMEM;
 935         }
 936         ctrldesc->pins = pindesc;
 937         ctrldesc->npins = info->ctrl->nr_pins;
 938
 939         pdesc = pindesc;
 940         for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
 941                 pin_bank = &info->ctrl->pin_banks[bank];
 942                 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
 943                         pdesc->number = k;
 944                         pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
 945                                                 pin_bank->name, pin);
 946                         pdesc++;
 947                 }
 948         }
 949
 950         info->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, info);
 951         if (!info->pctl_dev) {
 952                 dev_err(&pdev->dev, "could not register pinctrl driver\n");
 953                 return -EINVAL;
 954         }
 955
 956         for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
 957                 pin_bank = &info->ctrl->pin_banks[bank];
 958                 pin_bank->grange.name = pin_bank->name;
 959                 pin_bank->grange.id = bank;
 960                 pin_bank->grange.pin_base = pin_bank->pin_base;
 961                 pin_bank->grange.base = pin_bank->gpio_chip.base;
 962                 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
 963                 pin_bank->grange.gc = &pin_bank->gpio_chip;
 964                 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
 965         }
 966
 967         ret = rockchip_pinctrl_parse_dt(pdev, info);
 968         if (ret) {
 969                 pinctrl_unregister(info->pctl_dev);
 970                 return ret;
 971         }
 972
 973         return 0;
 974 }
 975
 976 /*
 977  * GPIO handling
 978  */
 979
 980 static int rockchip_gpio_request(struct gpio_chip *chip, unsigned offset)
 981 {
 982         return pinctrl_request_gpio(chip->base + offset);
 983 }
 984
 985 static void rockchip_gpio_free(struct gpio_chip *chip, unsigned offset)
 986 {
 987         pinctrl_free_gpio(chip->base + offset);
 988 }
 989
 990 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
 991 {
 992         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
 993         void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
 994         unsigned long flags;
 995         u32 data;
 996
 997         spin_lock_irqsave(&bank->slock, flags);
 998
 999         data = readl(reg);
1000         data &= ~BIT(offset);
1001         if (value)
1002                 data |= BIT(offset);
1003         writel(data, reg);
1004
1005         spin_unlock_irqrestore(&bank->slock, flags);
1006 }
1007
1008 /*
1009  * Returns the level of the pin for input direction and setting of the DR
1010  * register for output gpios.
1011  */
1012 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
1013 {
1014         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1015         u32 data;
1016
1017         data = readl(bank->reg_base + GPIO_EXT_PORT);
1018         data >>= offset;
1019         data &= 1;
1020         return data;
1021 }
1022
1023 /*
1024  * gpiolib gpio_direction_input callback function. The setting of the pin
1025  * mux function as 'gpio input' will be handled by the pinctrl susbsystem
1026  * interface.
1027  */
1028 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
1029 {
1030         return pinctrl_gpio_direction_input(gc->base + offset);
1031 }
1032
1033 /*
1034  * gpiolib gpio_direction_output callback function. The setting of the pin
1035  * mux function as 'gpio output' will be handled by the pinctrl susbsystem
1036  * interface.
1037  */
1038 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
1039                                           unsigned offset, int value)
1040 {
1041         rockchip_gpio_set(gc, offset, value);
1042         return pinctrl_gpio_direction_output(gc->base + offset);
1043 }
1044
1045 /*
1046  * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
1047  * and a virtual IRQ, if not already present.
1048  */
1049 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
1050 {
1051         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1052         unsigned int virq;
1053
1054         if (!bank->domain)
1055                 return -ENXIO;
1056
1057         virq = irq_create_mapping(bank->domain, offset);
1058
1059         return (virq) ? : -ENXIO;
1060 }
1061
1062 static const struct gpio_chip rockchip_gpiolib_chip = {
1063         .request = rockchip_gpio_request,
1064         .free = rockchip_gpio_free,
1065         .set = rockchip_gpio_set,
1066         .get = rockchip_gpio_get,
1067         .direction_input = rockchip_gpio_direction_input,
1068         .direction_output = rockchip_gpio_direction_output,
1069         .to_irq = rockchip_gpio_to_irq,
1070         .owner = THIS_MODULE,
1071 };
1072
1073 /*
1074  * Interrupt handling
1075  */
1076
1077 static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc)
1078 {
1079         struct irq_chip *chip = irq_get_chip(irq);
1080         struct rockchip_pin_bank *bank = irq_get_handler_data(irq);
1081         u32 polarity = 0, data = 0;
1082         u32 pend;
1083         bool edge_changed = false;
1084
1085         dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
1086
1087         chained_irq_enter(chip, desc);
1088
1089         pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
1090
1091         if (bank->toggle_edge_mode) {
1092                 polarity = readl_relaxed(bank->reg_base +
1093                                          GPIO_INT_POLARITY);
1094                 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
1095         }
1096
1097         while (pend) {
1098                 unsigned int virq;
1099
1100                 irq = __ffs(pend);
1101                 pend &= ~BIT(irq);
1102                 virq = irq_linear_revmap(bank->domain, irq);
1103
1104                 if (!virq) {
1105                         dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
1106                         continue;
1107                 }
1108
1109                 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
1110
1111                 /*
1112                  * Triggering IRQ on both rising and falling edge
1113                  * needs manual intervention.
1114                  */
1115                 if (bank->toggle_edge_mode & BIT(irq)) {
1116                         if (data & BIT(irq))
1117                                 polarity &= ~BIT(irq);
1118                         else
1119                                 polarity |= BIT(irq);
1120
1121                         edge_changed = true;
1122                 }
1123
1124                 generic_handle_irq(virq);
1125         }
1126
1127         if (bank->toggle_edge_mode && edge_changed) {
1128                 /* Interrupt params should only be set with ints disabled */
1129                 data = readl_relaxed(bank->reg_base + GPIO_INTEN);
1130                 writel_relaxed(0, bank->reg_base + GPIO_INTEN);
1131                 writel(polarity, bank->reg_base + GPIO_INT_POLARITY);
1132                 writel(data, bank->reg_base + GPIO_INTEN);
1133         }
1134
1135         chained_irq_exit(chip, desc);
1136 }
1137
1138 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
1139 {
1140         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1141         struct rockchip_pin_bank *bank = gc->private;
1142         u32 mask = BIT(d->hwirq);
1143         u32 polarity;
1144         u32 level;
1145         u32 data;
1146
1147         /* make sure the pin is configured as gpio input */
1148         rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
1149         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1150         data &= ~mask;
1151         writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
1152
1153         if (type & IRQ_TYPE_EDGE_BOTH)
1154                 __irq_set_handler_locked(d->irq, handle_edge_irq);
1155         else
1156                 __irq_set_handler_locked(d->irq, handle_level_irq);
1157
1158         irq_gc_lock(gc);
1159
1160         level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
1161         polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
1162
1163         switch (type) {
1164         case IRQ_TYPE_EDGE_BOTH:
1165                 bank->toggle_edge_mode |= mask;
1166                 level |= mask;
1167
1168                 /*
1169                  * Determine gpio state. If 1 next interrupt should be falling
1170                  * otherwise rising.
1171                  */
1172                 data = readl(bank->reg_base + GPIO_EXT_PORT);
1173                 if (data & mask)
1174                         polarity &= ~mask;
1175                 else
1176                         polarity |= mask;
1177                 break;
1178         case IRQ_TYPE_EDGE_RISING:
1179                 bank->toggle_edge_mode &= ~mask;
1180                 level |= mask;
1181                 polarity |= mask;
1182                 break;
1183         case IRQ_TYPE_EDGE_FALLING:
1184                 bank->toggle_edge_mode &= ~mask;
1185                 level |= mask;
1186                 polarity &= ~mask;
1187                 break;
1188         case IRQ_TYPE_LEVEL_HIGH:
1189                 bank->toggle_edge_mode &= ~mask;
1190                 level &= ~mask;
1191                 polarity |= mask;
1192                 break;
1193         case IRQ_TYPE_LEVEL_LOW:
1194                 bank->toggle_edge_mode &= ~mask;
1195                 level &= ~mask;
1196                 polarity &= ~mask;
1197                 break;
1198         default:
1199                 irq_gc_unlock(gc);
1200                 return -EINVAL;
1201         }
1202
1203         writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
1204         writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
1205
1206         irq_gc_unlock(gc);
1207
1208         return 0;
1209 }
1210
1211 static int rockchip_interrupts_register(struct platform_device *pdev,
1212                                                 struct rockchip_pinctrl *info)
1213 {
1214         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1215         struct rockchip_pin_bank *bank = ctrl->pin_banks;
1216         unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
1217         struct irq_chip_generic *gc;
1218         int ret;
1219         int i;
1220
1221         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1222                 if (!bank->valid) {
1223                         dev_warn(&pdev->dev, "bank %s is not valid\n",
1224                                  bank->name);
1225                         continue;
1226                 }
1227
1228                 bank->domain = irq_domain_add_linear(bank->of_node, 32,
1229                                                 &irq_generic_chip_ops, NULL);
1230                 if (!bank->domain) {
1231                         dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
1232                                  bank->name);
1233                         continue;
1234                 }
1235
1236                 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
1237                                          "rockchip_gpio_irq", handle_level_irq,
1238                                          clr, 0, IRQ_GC_INIT_MASK_CACHE);
1239                 if (ret) {
1240                         dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
1241                                 bank->name);
1242                         irq_domain_remove(bank->domain);
1243                         continue;
1244                 }
1245
1246                 gc = irq_get_domain_generic_chip(bank->domain, 0);
1247                 gc->reg_base = bank->reg_base;
1248                 gc->private = bank;
1249                 gc->chip_types[0].regs.mask = GPIO_INTEN;
1250                 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
1251                 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
1252                 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
1253                 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
1254                 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
1255                 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
1256
1257                 irq_set_handler_data(bank->irq, bank);
1258                 irq_set_chained_handler(bank->irq, rockchip_irq_demux);
1259         }
1260
1261         return 0;
1262 }
1263
1264 static int rockchip_gpiolib_register(struct platform_device *pdev,
1265                                                 struct rockchip_pinctrl *info)
1266 {
1267         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1268         struct rockchip_pin_bank *bank = ctrl->pin_banks;
1269         struct gpio_chip *gc;
1270         int ret;
1271         int i;
1272
1273         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1274                 if (!bank->valid) {
1275                         dev_warn(&pdev->dev, "bank %s is not valid\n",
1276                                  bank->name);
1277                         continue;
1278                 }
1279
1280                 bank->gpio_chip = rockchip_gpiolib_chip;
1281
1282                 gc = &bank->gpio_chip;
1283                 gc->base = bank->pin_base;
1284                 gc->ngpio = bank->nr_pins;
1285                 gc->dev = &pdev->dev;
1286                 gc->of_node = bank->of_node;
1287                 gc->label = bank->name;
1288
1289                 ret = gpiochip_add(gc);
1290                 if (ret) {
1291                         dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
1292                                                         gc->label, ret);
1293                         goto fail;
1294                 }
1295         }
1296
1297         rockchip_interrupts_register(pdev, info);
1298
1299         return 0;
1300
1301 fail:
1302         for (--i, --bank; i >= 0; --i, --bank) {
1303                 if (!bank->valid)
1304                         continue;
1305
1306                 if (gpiochip_remove(&bank->gpio_chip))
1307                         dev_err(&pdev->dev, "gpio chip %s remove failed\n",
1308                                                         bank->gpio_chip.label);
1309         }
1310         return ret;
1311 }
1312
1313 static int rockchip_gpiolib_unregister(struct platform_device *pdev,
1314                                                 struct rockchip_pinctrl *info)
1315 {
1316         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1317         struct rockchip_pin_bank *bank = ctrl->pin_banks;
1318         int ret = 0;
1319         int i;
1320
1321         for (i = 0; !ret && i < ctrl->nr_banks; ++i, ++bank) {
1322                 if (!bank->valid)
1323                         continue;
1324
1325                 ret = gpiochip_remove(&bank->gpio_chip);
1326         }
1327
1328         if (ret)
1329                 dev_err(&pdev->dev, "gpio chip remove failed\n");
1330
1331         return ret;
1332 }
1333
1334 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
1335                                   struct device *dev)
1336 {
1337         struct resource res;
1338
1339         if (of_address_to_resource(bank->of_node, 0, &res)) {
1340                 dev_err(dev, "cannot find IO resource for bank\n");
1341                 return -ENOENT;
1342         }
1343
1344         bank->reg_base = devm_ioremap_resource(dev, &res);
1345         if (IS_ERR(bank->reg_base))
1346                 return PTR_ERR(bank->reg_base);
1347
1348         /*
1349          * special case, where parts of the pull setting-registers are
1350          * part of the PMU register space
1351          */
1352         if (of_device_is_compatible(bank->of_node,
1353                                     "rockchip,rk3188-gpio-bank0")) {
1354                 bank->bank_type = RK3188_BANK0;
1355
1356                 if (of_address_to_resource(bank->of_node, 1, &res)) {
1357                         dev_err(dev, "cannot find IO resource for bank\n");
1358                         return -ENOENT;
1359                 }
1360
1361                 bank->reg_pull = devm_ioremap_resource(dev, &res);
1362                 if (IS_ERR(bank->reg_pull))
1363                         return PTR_ERR(bank->reg_pull);
1364         } else {
1365                 bank->bank_type = COMMON_BANK;
1366         }
1367
1368         bank->irq = irq_of_parse_and_map(bank->of_node, 0);
1369
1370         bank->clk = of_clk_get(bank->of_node, 0);
1371         if (IS_ERR(bank->clk))
1372                 return PTR_ERR(bank->clk);
1373
1374         return clk_prepare_enable(bank->clk);
1375 }
1376
1377 static const struct of_device_id rockchip_pinctrl_dt_match[];
1378
1379 /* retrieve the soc specific data */
1380 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
1381                                                 struct rockchip_pinctrl *d,
1382                                                 struct platform_device *pdev)
1383 {
1384         const struct of_device_id *match;
1385         struct device_node *node = pdev->dev.of_node;
1386         struct device_node *np;
1387         struct rockchip_pin_ctrl *ctrl;
1388         struct rockchip_pin_bank *bank;
1389         int i;
1390
1391         match = of_match_node(rockchip_pinctrl_dt_match, node);
1392         ctrl = (struct rockchip_pin_ctrl *)match->data;
1393
1394         for_each_child_of_node(node, np) {
1395                 if (!of_find_property(np, "gpio-controller", NULL))
1396                         continue;
1397
1398                 bank = ctrl->pin_banks;
1399                 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1400                         if (!strcmp(bank->name, np->name)) {
1401                                 bank->of_node = np;
1402
1403                                 if (!rockchip_get_bank_data(bank, &pdev->dev))
1404                                         bank->valid = true;
1405
1406                                 break;
1407                         }
1408                 }
1409         }
1410
1411         bank = ctrl->pin_banks;
1412         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1413                 spin_lock_init(&bank->slock);
1414                 bank->drvdata = d;
1415                 bank->pin_base = ctrl->nr_pins;
1416                 ctrl->nr_pins += bank->nr_pins;
1417         }
1418
1419         return ctrl;
1420 }
1421
1422 static int rockchip_pinctrl_probe(struct platform_device *pdev)
1423 {
1424         struct rockchip_pinctrl *info;
1425         struct device *dev = &pdev->dev;
1426         struct rockchip_pin_ctrl *ctrl;
1427         struct resource *res;
1428         int ret;
1429
1430         if (!dev->of_node) {
1431                 dev_err(dev, "device tree node not found\n");
1432                 return -ENODEV;
1433         }
1434
1435         info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL);
1436         if (!info)
1437                 return -ENOMEM;
1438
1439         ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
1440         if (!ctrl) {
1441                 dev_err(dev, "driver data not available\n");
1442                 return -EINVAL;
1443         }
1444         info->ctrl = ctrl;
1445         info->dev = dev;
1446
1447         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1448         info->reg_base = devm_ioremap_resource(&pdev->dev, res);
1449         if (IS_ERR(info->reg_base))
1450                 return PTR_ERR(info->reg_base);
1451
1452         /* The RK3188 has its pull registers in a separate place */
1453         if (ctrl->type == RK3188) {
1454                 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1455                 info->reg_pull = devm_ioremap_resource(&pdev->dev, res);
1456                 if (IS_ERR(info->reg_base))
1457                         return PTR_ERR(info->reg_base);
1458         }
1459
1460         ret = rockchip_gpiolib_register(pdev, info);
1461         if (ret)
1462                 return ret;
1463
1464         ret = rockchip_pinctrl_register(pdev, info);
1465         if (ret) {
1466                 rockchip_gpiolib_unregister(pdev, info);
1467                 return ret;
1468         }
1469
1470         platform_set_drvdata(pdev, info);
1471
1472         return 0;
1473 }
1474
1475 static struct rockchip_pin_bank rk2928_pin_banks[] = {
1476         PIN_BANK(0, 32, "gpio0"),
1477         PIN_BANK(1, 32, "gpio1"),
1478         PIN_BANK(2, 32, "gpio2"),
1479         PIN_BANK(3, 32, "gpio3"),
1480 };
1481
1482 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
1483                 .pin_banks              = rk2928_pin_banks,
1484                 .nr_banks               = ARRAY_SIZE(rk2928_pin_banks),
1485                 .label                  = "RK2928-GPIO",
1486                 .type                   = RK2928,
1487                 .mux_offset             = 0xa8,
1488                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
1489 };
1490
1491 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
1492         PIN_BANK(0, 32, "gpio0"),
1493         PIN_BANK(1, 32, "gpio1"),
1494         PIN_BANK(2, 32, "gpio2"),
1495         PIN_BANK(3, 32, "gpio3"),
1496         PIN_BANK(4, 32, "gpio4"),
1497         PIN_BANK(6, 16, "gpio6"),
1498 };
1499
1500 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
1501                 .pin_banks              = rk3066a_pin_banks,
1502                 .nr_banks               = ARRAY_SIZE(rk3066a_pin_banks),
1503                 .label                  = "RK3066a-GPIO",
1504                 .type                   = RK2928,
1505                 .mux_offset             = 0xa8,
1506                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
1507 };
1508
1509 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
1510         PIN_BANK(0, 32, "gpio0"),
1511         PIN_BANK(1, 32, "gpio1"),
1512         PIN_BANK(2, 32, "gpio2"),
1513         PIN_BANK(3, 32, "gpio3"),
1514 };
1515
1516 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
1517                 .pin_banks      = rk3066b_pin_banks,
1518                 .nr_banks       = ARRAY_SIZE(rk3066b_pin_banks),
1519                 .label          = "RK3066b-GPIO",
1520                 .type           = RK3066B,
1521                 .mux_offset     = 0x60,
1522 };
1523
1524 static struct rockchip_pin_bank rk3188_pin_banks[] = {
1525         PIN_BANK(0, 32, "gpio0"),
1526         PIN_BANK(1, 32, "gpio1"),
1527         PIN_BANK(2, 32, "gpio2"),
1528         PIN_BANK(3, 32, "gpio3"),
1529 };
1530
1531 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
1532                 .pin_banks              = rk3188_pin_banks,
1533                 .nr_banks               = ARRAY_SIZE(rk3188_pin_banks),
1534                 .label                  = "RK3188-GPIO",
1535                 .type                   = RK3188,
1536                 .mux_offset             = 0x68,
1537                 .pull_calc_reg          = rk3188_calc_pull_reg_and_bit,
1538 };
1539
1540 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
1541         { .compatible = "rockchip,rk2928-pinctrl",
1542                 .data = (void *)&rk2928_pin_ctrl },
1543         { .compatible = "rockchip,rk3066a-pinctrl",
1544                 .data = (void *)&rk3066a_pin_ctrl },
1545         { .compatible = "rockchip,rk3066b-pinctrl",
1546                 .data = (void *)&rk3066b_pin_ctrl },
1547         { .compatible = "rockchip,rk3188-pinctrl",
1548                 .data = (void *)&rk3188_pin_ctrl },
1549         {},
1550 };
1551 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
1552
1553 static struct platform_driver rockchip_pinctrl_driver = {
1554         .probe          = rockchip_pinctrl_probe,
1555         .driver = {
1556                 .name   = "rockchip-pinctrl",
1557                 .owner  = THIS_MODULE,
1558                 .of_match_table = rockchip_pinctrl_dt_match,
1559         },
1560 };
1561
1562 static int __init rockchip_pinctrl_drv_register(void)
1563 {
1564         return platform_driver_register(&rockchip_pinctrl_driver);
1565 }
1566 postcore_initcall(rockchip_pinctrl_drv_register);
1567
1568 MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
1569 MODULE_DESCRIPTION("Rockchip pinctrl driver");
1570 MODULE_LICENSE("GPL v2");