2 * Synopsys Designware PCIe host controller driver
4 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * Author: Jingoo Han <jg1.han@samsung.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/irq.h>
15 #include <linux/irqdomain.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/msi.h>
19 #include <linux/of_address.h>
20 #include <linux/of_pci.h>
21 #include <linux/pci.h>
22 #include <linux/pci_regs.h>
23 #include <linux/platform_device.h>
24 #include <linux/types.h>
26 #include "pcie-designware.h"
28 /* Synopsis specific PCIE configuration registers */
29 #define PCIE_PORT_LINK_CONTROL 0x710
30 #define PORT_LINK_MODE_MASK (0x3f << 16)
31 #define PORT_LINK_MODE_1_LANES (0x1 << 16)
32 #define PORT_LINK_MODE_2_LANES (0x3 << 16)
33 #define PORT_LINK_MODE_4_LANES (0x7 << 16)
35 #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
36 #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
37 #define PORT_LOGIC_LINK_WIDTH_MASK (0x1ff << 8)
38 #define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8)
39 #define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8)
40 #define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8)
42 #define PCIE_MSI_ADDR_LO 0x820
43 #define PCIE_MSI_ADDR_HI 0x824
44 #define PCIE_MSI_INTR0_ENABLE 0x828
45 #define PCIE_MSI_INTR0_MASK 0x82C
46 #define PCIE_MSI_INTR0_STATUS 0x830
48 #define PCIE_ATU_VIEWPORT 0x900
49 #define PCIE_ATU_REGION_INBOUND (0x1 << 31)
50 #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
51 #define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
52 #define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
53 #define PCIE_ATU_CR1 0x904
54 #define PCIE_ATU_TYPE_MEM (0x0 << 0)
55 #define PCIE_ATU_TYPE_IO (0x2 << 0)
56 #define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
57 #define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
58 #define PCIE_ATU_CR2 0x908
59 #define PCIE_ATU_ENABLE (0x1 << 31)
60 #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
61 #define PCIE_ATU_LOWER_BASE 0x90C
62 #define PCIE_ATU_UPPER_BASE 0x910
63 #define PCIE_ATU_LIMIT 0x914
64 #define PCIE_ATU_LOWER_TARGET 0x918
65 #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
66 #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
67 #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
68 #define PCIE_ATU_UPPER_TARGET 0x91C
70 static struct hw_pci dw_pci;
72 static unsigned long global_io_offset;
74 static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys)
76 BUG_ON(!sys->private_data);
78 return sys->private_data;
81 int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val)
86 *val = (*val >> (8 * (where & 3))) & 0xff;
88 *val = (*val >> (8 * (where & 3))) & 0xffff;
90 return PCIBIOS_BAD_REGISTER_NUMBER;
92 return PCIBIOS_SUCCESSFUL;
95 int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val)
100 writew(val, addr + (where & 2));
102 writeb(val, addr + (where & 3));
104 return PCIBIOS_BAD_REGISTER_NUMBER;
106 return PCIBIOS_SUCCESSFUL;
109 static inline void dw_pcie_readl_rc(struct pcie_port *pp, u32 reg, u32 *val)
111 if (pp->ops->readl_rc)
112 pp->ops->readl_rc(pp, pp->dbi_base + reg, val);
114 *val = readl(pp->dbi_base + reg);
117 static inline void dw_pcie_writel_rc(struct pcie_port *pp, u32 val, u32 reg)
119 if (pp->ops->writel_rc)
120 pp->ops->writel_rc(pp, val, pp->dbi_base + reg);
122 writel(val, pp->dbi_base + reg);
125 static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
130 if (pp->ops->rd_own_conf)
131 ret = pp->ops->rd_own_conf(pp, where, size, val);
133 ret = dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where,
139 static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
144 if (pp->ops->wr_own_conf)
145 ret = pp->ops->wr_own_conf(pp, where, size, val);
147 ret = dw_pcie_cfg_write(pp->dbi_base + (where & ~0x3), where,
153 static struct irq_chip dw_msi_irq_chip = {
155 .irq_enable = pci_msi_unmask_irq,
156 .irq_disable = pci_msi_mask_irq,
157 .irq_mask = pci_msi_mask_irq,
158 .irq_unmask = pci_msi_unmask_irq,
161 /* MSI int handler */
162 irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
166 irqreturn_t ret = IRQ_NONE;
168 for (i = 0; i < MAX_MSI_CTRLS; i++) {
169 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4,
174 while ((pos = find_next_bit(&val, 32, pos)) != 32) {
175 irq = irq_find_mapping(pp->irq_domain,
177 dw_pcie_wr_own_conf(pp,
178 PCIE_MSI_INTR0_STATUS + i * 12,
180 generic_handle_irq(irq);
189 void dw_pcie_msi_init(struct pcie_port *pp)
191 pp->msi_data = __get_free_pages(GFP_KERNEL, 0);
193 /* program the msi_data */
194 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4,
195 virt_to_phys((void *)pp->msi_data));
196 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, 0);
199 static void dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq)
201 unsigned int res, bit, val;
203 res = (irq / 32) * 12;
205 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
207 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
210 static void clear_irq_range(struct pcie_port *pp, unsigned int irq_base,
211 unsigned int nvec, unsigned int pos)
215 for (i = 0; i < nvec; i++) {
216 irq_set_msi_desc_off(irq_base, i, NULL);
217 /* Disable corresponding interrupt on MSI controller */
218 if (pp->ops->msi_clear_irq)
219 pp->ops->msi_clear_irq(pp, pos + i);
221 dw_pcie_msi_clear_irq(pp, pos + i);
224 bitmap_release_region(pp->msi_irq_in_use, pos, order_base_2(nvec));
227 static void dw_pcie_msi_set_irq(struct pcie_port *pp, int irq)
229 unsigned int res, bit, val;
231 res = (irq / 32) * 12;
233 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
235 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
238 static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos)
241 struct pcie_port *pp = sys_to_pcie(desc->dev->bus->sysdata);
243 pos0 = bitmap_find_free_region(pp->msi_irq_in_use, MAX_MSI_IRQS,
244 order_base_2(no_irqs));
248 irq = irq_find_mapping(pp->irq_domain, pos0);
253 * irq_create_mapping (called from dw_pcie_host_init) pre-allocates
254 * descs so there is no need to allocate descs here. We can therefore
255 * assume that if irq_find_mapping above returns non-zero, then the
256 * descs are also successfully allocated.
259 for (i = 0; i < no_irqs; i++) {
260 if (irq_set_msi_desc_off(irq, i, desc) != 0) {
261 clear_irq_range(pp, irq, i, pos0);
264 /*Enable corresponding interrupt in MSI interrupt controller */
265 if (pp->ops->msi_set_irq)
266 pp->ops->msi_set_irq(pp, pos0 + i);
268 dw_pcie_msi_set_irq(pp, pos0 + i);
279 static int dw_msi_setup_irq(struct msi_controller *chip, struct pci_dev *pdev,
280 struct msi_desc *desc)
284 struct pcie_port *pp = sys_to_pcie(pdev->bus->sysdata);
286 if (desc->msi_attrib.is_msix)
289 irq = assign_irq(1, desc, &pos);
293 if (pp->ops->get_msi_addr)
294 msg.address_lo = pp->ops->get_msi_addr(pp);
296 msg.address_lo = virt_to_phys((void *)pp->msi_data);
297 msg.address_hi = 0x0;
299 if (pp->ops->get_msi_data)
300 msg.data = pp->ops->get_msi_data(pp, pos);
304 pci_write_msi_msg(irq, &msg);
309 static void dw_msi_teardown_irq(struct msi_controller *chip, unsigned int irq)
311 struct irq_data *data = irq_get_irq_data(irq);
312 struct msi_desc *msi = irq_data_get_msi(data);
313 struct pcie_port *pp = sys_to_pcie(msi->dev->bus->sysdata);
315 clear_irq_range(pp, irq, 1, data->hwirq);
318 static struct msi_controller dw_pcie_msi_chip = {
319 .setup_irq = dw_msi_setup_irq,
320 .teardown_irq = dw_msi_teardown_irq,
323 int dw_pcie_link_up(struct pcie_port *pp)
325 if (pp->ops->link_up)
326 return pp->ops->link_up(pp);
331 static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
332 irq_hw_number_t hwirq)
334 irq_set_chip_and_handler(irq, &dw_msi_irq_chip, handle_simple_irq);
335 irq_set_chip_data(irq, domain->host_data);
336 set_irq_flags(irq, IRQF_VALID);
341 static const struct irq_domain_ops msi_domain_ops = {
342 .map = dw_pcie_msi_map,
345 int __init dw_pcie_host_init(struct pcie_port *pp)
347 struct device_node *np = pp->dev->of_node;
348 struct platform_device *pdev = to_platform_device(pp->dev);
349 struct of_pci_range range;
350 struct of_pci_range_parser parser;
351 struct resource *cfg_res;
356 /* Find the address cell size and the number of cells in order to get
357 * the untranslated address.
359 of_property_read_u32(np, "#address-cells", &na);
360 ns = of_n_size_cells(np);
362 cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
364 pp->cfg0_size = resource_size(cfg_res)/2;
365 pp->cfg1_size = resource_size(cfg_res)/2;
366 pp->cfg0_base = cfg_res->start;
367 pp->cfg1_base = cfg_res->start + pp->cfg0_size;
369 /* Find the untranslated configuration space address */
370 index = of_property_match_string(np, "reg-names", "config");
371 addrp = of_get_address(np, index, NULL, NULL);
372 pp->cfg0_mod_base = of_read_number(addrp, ns);
373 pp->cfg1_mod_base = pp->cfg0_mod_base + pp->cfg0_size;
375 dev_err(pp->dev, "missing *config* reg space\n");
378 if (of_pci_range_parser_init(&parser, np)) {
379 dev_err(pp->dev, "missing ranges property\n");
383 /* Get the I/O and memory ranges from DT */
384 for_each_of_pci_range(&parser, &range) {
385 unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
387 if (restype == IORESOURCE_IO) {
388 of_pci_range_to_resource(&range, np, &pp->io);
390 pp->io.start = max_t(resource_size_t,
392 range.pci_addr + global_io_offset);
393 pp->io.end = min_t(resource_size_t,
395 range.pci_addr + range.size
396 + global_io_offset - 1);
397 pp->io_size = resource_size(&pp->io);
398 pp->io_bus_addr = range.pci_addr;
399 pp->io_base = range.cpu_addr;
401 /* Find the untranslated IO space address */
402 pp->io_mod_base = of_read_number(parser.range -
405 if (restype == IORESOURCE_MEM) {
406 of_pci_range_to_resource(&range, np, &pp->mem);
407 pp->mem.name = "MEM";
408 pp->mem_size = resource_size(&pp->mem);
409 pp->mem_bus_addr = range.pci_addr;
411 /* Find the untranslated MEM space address */
412 pp->mem_mod_base = of_read_number(parser.range -
416 of_pci_range_to_resource(&range, np, &pp->cfg);
417 pp->cfg0_size = resource_size(&pp->cfg)/2;
418 pp->cfg1_size = resource_size(&pp->cfg)/2;
419 pp->cfg0_base = pp->cfg.start;
420 pp->cfg1_base = pp->cfg.start + pp->cfg0_size;
422 /* Find the untranslated configuration space address */
423 pp->cfg0_mod_base = of_read_number(parser.range -
425 pp->cfg1_mod_base = pp->cfg0_mod_base +
430 ret = of_pci_parse_bus_range(np, &pp->busn);
432 pp->busn.name = np->name;
435 pp->busn.flags = IORESOURCE_BUS;
436 dev_dbg(pp->dev, "failed to parse bus-range property: %d, using default %pR\n",
441 pp->dbi_base = devm_ioremap(pp->dev, pp->cfg.start,
442 resource_size(&pp->cfg));
444 dev_err(pp->dev, "error with ioremap\n");
449 pp->mem_base = pp->mem.start;
451 if (!pp->va_cfg0_base) {
452 pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
454 if (!pp->va_cfg0_base) {
455 dev_err(pp->dev, "error with ioremap in function\n");
460 if (!pp->va_cfg1_base) {
461 pp->va_cfg1_base = devm_ioremap(pp->dev, pp->cfg1_base,
463 if (!pp->va_cfg1_base) {
464 dev_err(pp->dev, "error with ioremap\n");
469 if (of_property_read_u32(np, "num-lanes", &pp->lanes)) {
470 dev_err(pp->dev, "Failed to parse the number of lanes\n");
474 if (IS_ENABLED(CONFIG_PCI_MSI)) {
475 if (!pp->ops->msi_host_init) {
476 pp->irq_domain = irq_domain_add_linear(pp->dev->of_node,
477 MAX_MSI_IRQS, &msi_domain_ops,
479 if (!pp->irq_domain) {
480 dev_err(pp->dev, "irq domain init failed\n");
484 for (i = 0; i < MAX_MSI_IRQS; i++)
485 irq_create_mapping(pp->irq_domain, i);
487 ret = pp->ops->msi_host_init(pp, &dw_pcie_msi_chip);
493 if (pp->ops->host_init)
494 pp->ops->host_init(pp);
496 dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
498 /* program correct class for RC */
499 dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
501 dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
502 val |= PORT_LOGIC_SPEED_CHANGE;
503 dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
505 #ifdef CONFIG_PCI_MSI
506 dw_pcie_msi_chip.dev = pp->dev;
507 dw_pci.msi_ctrl = &dw_pcie_msi_chip;
510 dw_pci.nr_controllers = 1;
511 dw_pci.private_data = (void **)&pp;
513 pci_common_init_dev(pp->dev, &dw_pci);
514 #ifdef CONFIG_PCI_DOMAINS
521 static void dw_pcie_prog_viewport_cfg0(struct pcie_port *pp, u32 busdev)
523 /* Program viewport 0 : OUTBOUND : CFG0 */
524 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
526 dw_pcie_writel_rc(pp, pp->cfg0_mod_base, PCIE_ATU_LOWER_BASE);
527 dw_pcie_writel_rc(pp, (pp->cfg0_mod_base >> 32), PCIE_ATU_UPPER_BASE);
528 dw_pcie_writel_rc(pp, pp->cfg0_mod_base + pp->cfg0_size - 1,
530 dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
531 dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
532 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG0, PCIE_ATU_CR1);
533 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
536 static void dw_pcie_prog_viewport_cfg1(struct pcie_port *pp, u32 busdev)
538 /* Program viewport 1 : OUTBOUND : CFG1 */
539 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
541 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG1, PCIE_ATU_CR1);
542 dw_pcie_writel_rc(pp, pp->cfg1_mod_base, PCIE_ATU_LOWER_BASE);
543 dw_pcie_writel_rc(pp, (pp->cfg1_mod_base >> 32), PCIE_ATU_UPPER_BASE);
544 dw_pcie_writel_rc(pp, pp->cfg1_mod_base + pp->cfg1_size - 1,
546 dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
547 dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
548 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
551 static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
553 /* Program viewport 0 : OUTBOUND : MEM */
554 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
556 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1);
557 dw_pcie_writel_rc(pp, pp->mem_mod_base, PCIE_ATU_LOWER_BASE);
558 dw_pcie_writel_rc(pp, (pp->mem_mod_base >> 32), PCIE_ATU_UPPER_BASE);
559 dw_pcie_writel_rc(pp, pp->mem_mod_base + pp->mem_size - 1,
561 dw_pcie_writel_rc(pp, pp->mem_bus_addr, PCIE_ATU_LOWER_TARGET);
562 dw_pcie_writel_rc(pp, upper_32_bits(pp->mem_bus_addr),
563 PCIE_ATU_UPPER_TARGET);
564 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
567 static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp)
569 /* Program viewport 1 : OUTBOUND : IO */
570 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
572 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_IO, PCIE_ATU_CR1);
573 dw_pcie_writel_rc(pp, pp->io_mod_base, PCIE_ATU_LOWER_BASE);
574 dw_pcie_writel_rc(pp, (pp->io_mod_base >> 32), PCIE_ATU_UPPER_BASE);
575 dw_pcie_writel_rc(pp, pp->io_mod_base + pp->io_size - 1,
577 dw_pcie_writel_rc(pp, pp->io_bus_addr, PCIE_ATU_LOWER_TARGET);
578 dw_pcie_writel_rc(pp, upper_32_bits(pp->io_bus_addr),
579 PCIE_ATU_UPPER_TARGET);
580 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
583 static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
584 u32 devfn, int where, int size, u32 *val)
586 int ret = PCIBIOS_SUCCESSFUL;
589 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
590 PCIE_ATU_FUNC(PCI_FUNC(devfn));
591 address = where & ~0x3;
593 if (bus->parent->number == pp->root_bus_nr) {
594 dw_pcie_prog_viewport_cfg0(pp, busdev);
595 ret = dw_pcie_cfg_read(pp->va_cfg0_base + address, where, size,
597 dw_pcie_prog_viewport_mem_outbound(pp);
599 dw_pcie_prog_viewport_cfg1(pp, busdev);
600 ret = dw_pcie_cfg_read(pp->va_cfg1_base + address, where, size,
602 dw_pcie_prog_viewport_io_outbound(pp);
608 static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
609 u32 devfn, int where, int size, u32 val)
611 int ret = PCIBIOS_SUCCESSFUL;
614 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
615 PCIE_ATU_FUNC(PCI_FUNC(devfn));
616 address = where & ~0x3;
618 if (bus->parent->number == pp->root_bus_nr) {
619 dw_pcie_prog_viewport_cfg0(pp, busdev);
620 ret = dw_pcie_cfg_write(pp->va_cfg0_base + address, where, size,
622 dw_pcie_prog_viewport_mem_outbound(pp);
624 dw_pcie_prog_viewport_cfg1(pp, busdev);
625 ret = dw_pcie_cfg_write(pp->va_cfg1_base + address, where, size,
627 dw_pcie_prog_viewport_io_outbound(pp);
633 static int dw_pcie_valid_config(struct pcie_port *pp,
634 struct pci_bus *bus, int dev)
636 /* If there is no link, then there is no device */
637 if (bus->number != pp->root_bus_nr) {
638 if (!dw_pcie_link_up(pp))
642 /* access only one slot on each root port */
643 if (bus->number == pp->root_bus_nr && dev > 0)
647 * do not read more than one device on the bus directly attached
648 * to RC's (Virtual Bridge's) DS side.
650 if (bus->primary == pp->root_bus_nr && dev > 0)
656 static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
659 struct pcie_port *pp = sys_to_pcie(bus->sysdata);
662 if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) {
664 return PCIBIOS_DEVICE_NOT_FOUND;
667 if (bus->number != pp->root_bus_nr)
668 if (pp->ops->rd_other_conf)
669 ret = pp->ops->rd_other_conf(pp, bus, devfn,
672 ret = dw_pcie_rd_other_conf(pp, bus, devfn,
675 ret = dw_pcie_rd_own_conf(pp, where, size, val);
680 static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
681 int where, int size, u32 val)
683 struct pcie_port *pp = sys_to_pcie(bus->sysdata);
686 if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0)
687 return PCIBIOS_DEVICE_NOT_FOUND;
689 if (bus->number != pp->root_bus_nr)
690 if (pp->ops->wr_other_conf)
691 ret = pp->ops->wr_other_conf(pp, bus, devfn,
694 ret = dw_pcie_wr_other_conf(pp, bus, devfn,
697 ret = dw_pcie_wr_own_conf(pp, where, size, val);
702 static struct pci_ops dw_pcie_ops = {
703 .read = dw_pcie_rd_conf,
704 .write = dw_pcie_wr_conf,
707 static int dw_pcie_setup(int nr, struct pci_sys_data *sys)
709 struct pcie_port *pp;
711 pp = sys_to_pcie(sys);
713 if (global_io_offset < SZ_1M && pp->io_size > 0) {
714 sys->io_offset = global_io_offset - pp->io_bus_addr;
715 pci_ioremap_io(global_io_offset, pp->io_base);
716 global_io_offset += SZ_64K;
717 pci_add_resource_offset(&sys->resources, &pp->io,
721 sys->mem_offset = pp->mem.start - pp->mem_bus_addr;
722 pci_add_resource_offset(&sys->resources, &pp->mem, sys->mem_offset);
723 pci_add_resource(&sys->resources, &pp->busn);
728 static struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys)
731 struct pcie_port *pp = sys_to_pcie(sys);
733 pp->root_bus_nr = sys->busnr;
734 bus = pci_create_root_bus(pp->dev, sys->busnr,
735 &dw_pcie_ops, sys, &sys->resources);
739 pci_scan_child_bus(bus);
741 if (bus && pp->ops->scan_bus)
742 pp->ops->scan_bus(pp);
747 static int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
749 struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata);
752 irq = of_irq_parse_and_map_pci(dev, slot, pin);
759 static struct hw_pci dw_pci = {
760 .setup = dw_pcie_setup,
761 .scan = dw_pcie_scan_bus,
762 .map_irq = dw_pcie_map_irq,
765 void dw_pcie_setup_rc(struct pcie_port *pp)
771 /* set the number of lanes */
772 dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val);
773 val &= ~PORT_LINK_MODE_MASK;
776 val |= PORT_LINK_MODE_1_LANES;
779 val |= PORT_LINK_MODE_2_LANES;
782 val |= PORT_LINK_MODE_4_LANES;
785 dw_pcie_writel_rc(pp, val, PCIE_PORT_LINK_CONTROL);
787 /* set link width speed control register */
788 dw_pcie_readl_rc(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, &val);
789 val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
792 val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
795 val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
798 val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
801 dw_pcie_writel_rc(pp, val, PCIE_LINK_WIDTH_SPEED_CONTROL);
804 dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_0);
805 dw_pcie_writel_rc(pp, 0x00000000, PCI_BASE_ADDRESS_1);
807 /* setup interrupt pins */
808 dw_pcie_readl_rc(pp, PCI_INTERRUPT_LINE, &val);
811 dw_pcie_writel_rc(pp, val, PCI_INTERRUPT_LINE);
813 /* setup bus numbers */
814 dw_pcie_readl_rc(pp, PCI_PRIMARY_BUS, &val);
817 dw_pcie_writel_rc(pp, val, PCI_PRIMARY_BUS);
819 /* setup memory base, memory limit */
820 membase = ((u32)pp->mem_base & 0xfff00000) >> 16;
821 memlimit = (pp->mem_size + (u32)pp->mem_base) & 0xfff00000;
822 val = memlimit | membase;
823 dw_pcie_writel_rc(pp, val, PCI_MEMORY_BASE);
825 /* setup command register */
826 dw_pcie_readl_rc(pp, PCI_COMMAND, &val);
828 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
829 PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
830 dw_pcie_writel_rc(pp, val, PCI_COMMAND);
833 MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
834 MODULE_DESCRIPTION("Designware PCIe host controller driver");
835 MODULE_LICENSE("GPL v2");