drivers/net/wireless/iwlwifi/pcie/trans.c

   1 /******************************************************************************
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  51  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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  53  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  54  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  60  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  61  *
  62  *****************************************************************************/
  63 #include <linux/pci.h>
  64 #include <linux/pci-aspm.h>
  65 #include <linux/interrupt.h>
  66 #include <linux/debugfs.h>
  67 #include <linux/sched.h>
  68 #include <linux/bitops.h>
  69 #include <linux/gfp.h>
  70
  71 #include "iwl-drv.h"
  72 #include "iwl-trans.h"
  73 #include "iwl-csr.h"
  74 #include "iwl-prph.h"
  75 #include "iwl-agn-hw.h"
  76 #include "internal.h"
  77
  78 static void __iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans,
  79                                                   u32 reg, u32 mask, u32 value)
  80 {
  81         u32 v;
  82
  83 #ifdef CONFIG_IWLWIFI_DEBUG
  84         WARN_ON_ONCE(value & ~mask);
  85 #endif
  86
  87         v = iwl_read32(trans, reg);
  88         v &= ~mask;
  89         v |= value;
  90         iwl_write32(trans, reg, v);
  91 }
  92
  93 static inline void __iwl_trans_pcie_clear_bit(struct iwl_trans *trans,
  94                                               u32 reg, u32 mask)
  95 {
  96         __iwl_trans_pcie_set_bits_mask(trans, reg, mask, 0);
  97 }
  98
  99 static inline void __iwl_trans_pcie_set_bit(struct iwl_trans *trans,
 100                                             u32 reg, u32 mask)
 101 {
 102         __iwl_trans_pcie_set_bits_mask(trans, reg, mask, mask);
 103 }
 104
 105 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
 106 {
 107         if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
 108                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 109                                        APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 110                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 111         else
 112                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 113                                        APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 114                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 115 }
 116
 117 /* PCI registers */
 118 #define PCI_CFG_RETRY_TIMEOUT   0x041
 119
 120 static void iwl_pcie_apm_config(struct iwl_trans *trans)
 121 {
 122         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 123         u16 lctl;
 124
 125         /*
 126          * HW bug W/A for instability in PCIe bus L0S->L1 transition.
 127          * Check if BIOS (or OS) enabled L1-ASPM on this device.
 128          * If so (likely), disable L0S, so device moves directly L0->L1;
 129          *    costs negligible amount of power savings.
 130          * If not (unlikely), enable L0S, so there is at least some
 131          *    power savings, even without L1.
 132          */
 133         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
 134         if (lctl & PCI_EXP_LNKCTL_ASPM_L1) {
 135                 /* L1-ASPM enabled; disable(!) L0S */
 136                 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 137                 dev_info(trans->dev, "L1 Enabled; Disabling L0S\n");
 138         } else {
 139                 /* L1-ASPM disabled; enable(!) L0S */
 140                 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 141                 dev_info(trans->dev, "L1 Disabled; Enabling L0S\n");
 142         }
 143         trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
 144 }
 145
 146 /*
 147  * Start up NIC's basic functionality after it has been reset
 148  * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
 149  * NOTE:  This does not load uCode nor start the embedded processor
 150  */
 151 static int iwl_pcie_apm_init(struct iwl_trans *trans)
 152 {
 153         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 154         int ret = 0;
 155         IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
 156
 157         /*
 158          * Use "set_bit" below rather than "write", to preserve any hardware
 159          * bits already set by default after reset.
 160          */
 161
 162         /* Disable L0S exit timer (platform NMI Work/Around) */
 163         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 164                     CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 165
 166         /*
 167          * Disable L0s without affecting L1;
 168          *  don't wait for ICH L0s (ICH bug W/A)
 169          */
 170         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 171                     CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 172
 173         /* Set FH wait threshold to maximum (HW error during stress W/A) */
 174         iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 175
 176         /*
 177          * Enable HAP INTA (interrupt from management bus) to
 178          * wake device's PCI Express link L1a -> L0s
 179          */
 180         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 181                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 182
 183         iwl_pcie_apm_config(trans);
 184
 185         /* Configure analog phase-lock-loop before activating to D0A */
 186         if (trans->cfg->base_params->pll_cfg_val)
 187                 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
 188                             trans->cfg->base_params->pll_cfg_val);
 189
 190         /*
 191          * Set "initialization complete" bit to move adapter from
 192          * D0U* --> D0A* (powered-up active) state.
 193          */
 194         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 195
 196         /*
 197          * Wait for clock stabilization; once stabilized, access to
 198          * device-internal resources is supported, e.g. iwl_write_prph()
 199          * and accesses to uCode SRAM.
 200          */
 201         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 202                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 203                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 204         if (ret < 0) {
 205                 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
 206                 goto out;
 207         }
 208
 209         /*
 210          * Enable DMA clock and wait for it to stabilize.
 211          *
 212          * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
 213          * do not disable clocks.  This preserves any hardware bits already
 214          * set by default in "CLK_CTRL_REG" after reset.
 215          */
 216         iwl_write_prph(trans, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
 217         udelay(20);
 218
 219         /* Disable L1-Active */
 220         iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 221                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 222
 223         /* Clear the interrupt in APMG if the NIC is in RFKILL */
 224         iwl_write_prph(trans, APMG_RTC_INT_STT_REG, APMG_RTC_INT_STT_RFKILL);
 225
 226         set_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
 227
 228 out:
 229         return ret;
 230 }
 231
 232 static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
 233 {
 234         int ret = 0;
 235
 236         /* stop device's busmaster DMA activity */
 237         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
 238
 239         ret = iwl_poll_bit(trans, CSR_RESET,
 240                            CSR_RESET_REG_FLAG_MASTER_DISABLED,
 241                            CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
 242         if (ret)
 243                 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
 244
 245         IWL_DEBUG_INFO(trans, "stop master\n");
 246
 247         return ret;
 248 }
 249
 250 static void iwl_pcie_apm_stop(struct iwl_trans *trans)
 251 {
 252         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 253         IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
 254
 255         clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
 256
 257         /* Stop device's DMA activity */
 258         iwl_pcie_apm_stop_master(trans);
 259
 260         /* Reset the entire device */
 261         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 262
 263         udelay(10);
 264
 265         /*
 266          * Clear "initialization complete" bit to move adapter from
 267          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 268          */
 269         iwl_clear_bit(trans, CSR_GP_CNTRL,
 270                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 271 }
 272
 273 static int iwl_pcie_nic_init(struct iwl_trans *trans)
 274 {
 275         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 276         unsigned long flags;
 277
 278         /* nic_init */
 279         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 280         iwl_pcie_apm_init(trans);
 281
 282         /* Set interrupt coalescing calibration timer to default (512 usecs) */
 283         iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
 284
 285         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 286
 287         iwl_pcie_set_pwr(trans, false);
 288
 289         iwl_op_mode_nic_config(trans->op_mode);
 290
 291         /* Allocate the RX queue, or reset if it is already allocated */
 292         iwl_pcie_rx_init(trans);
 293
 294         /* Allocate or reset and init all Tx and Command queues */
 295         if (iwl_pcie_tx_init(trans))
 296                 return -ENOMEM;
 297
 298         if (trans->cfg->base_params->shadow_reg_enable) {
 299                 /* enable shadow regs in HW */
 300                 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
 301                 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
 302         }
 303
 304         return 0;
 305 }
 306
 307 #define HW_READY_TIMEOUT (50)
 308
 309 /* Note: returns poll_bit return value, which is >= 0 if success */
 310 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
 311 {
 312         int ret;
 313
 314         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 315                     CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
 316
 317         /* See if we got it */
 318         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 319                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 320                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 321                            HW_READY_TIMEOUT);
 322
 323         IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
 324         return ret;
 325 }
 326
 327 /* Note: returns standard 0/-ERROR code */
 328 static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
 329 {
 330         int ret;
 331         int t = 0;
 332
 333         IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
 334
 335         ret = iwl_pcie_set_hw_ready(trans);
 336         /* If the card is ready, exit 0 */
 337         if (ret >= 0)
 338                 return 0;
 339
 340         /* If HW is not ready, prepare the conditions to check again */
 341         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 342                     CSR_HW_IF_CONFIG_REG_PREPARE);
 343
 344         do {
 345                 ret = iwl_pcie_set_hw_ready(trans);
 346                 if (ret >= 0)
 347                         return 0;
 348
 349                 usleep_range(200, 1000);
 350                 t += 200;
 351         } while (t < 150000);
 352
 353         return ret;
 354 }
 355
 356 /*
 357  * ucode
 358  */
 359 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
 360                                    dma_addr_t phy_addr, u32 byte_cnt)
 361 {
 362         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 363         int ret;
 364
 365         trans_pcie->ucode_write_complete = false;
 366
 367         iwl_write_direct32(trans,
 368                            FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 369                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 370
 371         iwl_write_direct32(trans,
 372                            FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
 373                            dst_addr);
 374
 375         iwl_write_direct32(trans,
 376                            FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 377                            phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 378
 379         iwl_write_direct32(trans,
 380                            FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 381                            (iwl_get_dma_hi_addr(phy_addr)
 382                                 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 383
 384         iwl_write_direct32(trans,
 385                            FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 386                            1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
 387                            1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
 388                            FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 389
 390         iwl_write_direct32(trans,
 391                            FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 392                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE    |
 393                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
 394                            FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 395
 396         ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
 397                                  trans_pcie->ucode_write_complete, 5 * HZ);
 398         if (!ret) {
 399                 IWL_ERR(trans, "Failed to load firmware chunk!\n");
 400                 return -ETIMEDOUT;
 401         }
 402
 403         return 0;
 404 }
 405
 406 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
 407                             const struct fw_desc *section)
 408 {
 409         u8 *v_addr;
 410         dma_addr_t p_addr;
 411         u32 offset, chunk_sz = section->len;
 412         int ret = 0;
 413
 414         IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
 415                      section_num);
 416
 417         v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
 418                                     GFP_KERNEL | __GFP_NOWARN);
 419         if (!v_addr) {
 420                 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
 421                 chunk_sz = PAGE_SIZE;
 422                 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
 423                                             &p_addr, GFP_KERNEL);
 424                 if (!v_addr)
 425                         return -ENOMEM;
 426         }
 427
 428         for (offset = 0; offset < section->len; offset += chunk_sz) {
 429                 u32 copy_size;
 430
 431                 copy_size = min_t(u32, chunk_sz, section->len - offset);
 432
 433                 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
 434                 ret = iwl_pcie_load_firmware_chunk(trans,
 435                                                    section->offset + offset,
 436                                                    p_addr, copy_size);
 437                 if (ret) {
 438                         IWL_ERR(trans,
 439                                 "Could not load the [%d] uCode section\n",
 440                                 section_num);
 441                         break;
 442                 }
 443         }
 444
 445         dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
 446         return ret;
 447 }
 448
 449 static int iwl_pcie_secure_set(struct iwl_trans *trans, int cpu)
 450 {
 451         int shift_param;
 452         u32 address;
 453         int ret = 0;
 454
 455         if (cpu == 1) {
 456                 shift_param = 0;
 457                 address = CSR_SECURE_BOOT_CPU1_STATUS_ADDR;
 458         } else {
 459                 shift_param = 16;
 460                 address = CSR_SECURE_BOOT_CPU2_STATUS_ADDR;
 461         }
 462
 463         /* set CPU to started */
 464         iwl_trans_set_bits_mask(trans,
 465                                 CSR_UCODE_LOAD_STATUS_ADDR,
 466                                 CSR_CPU_STATUS_LOADING_STARTED << shift_param,
 467                                 1);
 468
 469         /* set last complete descriptor number */
 470         iwl_trans_set_bits_mask(trans,
 471                                 CSR_UCODE_LOAD_STATUS_ADDR,
 472                                 CSR_CPU_STATUS_NUM_OF_LAST_COMPLETED
 473                                 << shift_param,
 474                                 1);
 475
 476         /* set last loaded block */
 477         iwl_trans_set_bits_mask(trans,
 478                                 CSR_UCODE_LOAD_STATUS_ADDR,
 479                                 CSR_CPU_STATUS_NUM_OF_LAST_LOADED_BLOCK
 480                                 << shift_param,
 481                                 1);
 482
 483         /* image loading complete */
 484         iwl_trans_set_bits_mask(trans,
 485                                 CSR_UCODE_LOAD_STATUS_ADDR,
 486                                 CSR_CPU_STATUS_LOADING_COMPLETED
 487                                 << shift_param,
 488                                 1);
 489
 490         /* set FH_TCSR_0_REG  */
 491         iwl_trans_set_bits_mask(trans, FH_TCSR_0_REG0, 0x00400000, 1);
 492
 493         /* verify image verification started  */
 494         ret = iwl_poll_bit(trans, address,
 495                            CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS,
 496                            CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS,
 497                            CSR_SECURE_TIME_OUT);
 498         if (ret < 0) {
 499                 IWL_ERR(trans, "secure boot process didn't start\n");
 500                 return ret;
 501         }
 502
 503         /* wait for image verification to complete  */
 504         ret = iwl_poll_bit(trans, address,
 505                            CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED,
 506                            CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED,
 507                            CSR_SECURE_TIME_OUT);
 508
 509         if (ret < 0) {
 510                 IWL_ERR(trans, "Time out on secure boot process\n");
 511                 return ret;
 512         }
 513
 514         return 0;
 515 }
 516
 517 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
 518                                 const struct fw_img *image)
 519 {
 520         int i, ret = 0;
 521
 522         IWL_DEBUG_FW(trans,
 523                      "working with %s image\n",
 524                      image->is_secure ? "Secured" : "Non Secured");
 525         IWL_DEBUG_FW(trans,
 526                      "working with %s CPU\n",
 527                      image->is_dual_cpus ? "Dual" : "Single");
 528
 529         /* configure the ucode to be ready to get the secured image */
 530         if (image->is_secure) {
 531                 /* set secure boot inspector addresses */
 532                 iwl_write32(trans, CSR_SECURE_INSPECTOR_CODE_ADDR, 0);
 533                 iwl_write32(trans, CSR_SECURE_INSPECTOR_DATA_ADDR, 0);
 534
 535                 /* release CPU1 reset if secure inspector image burned in OTP */
 536                 iwl_write32(trans, CSR_RESET, 0);
 537         }
 538
 539         /* load to FW the binary sections of CPU1 */
 540         IWL_DEBUG_INFO(trans, "Loading CPU1\n");
 541         for (i = 0;
 542              i < IWL_UCODE_FIRST_SECTION_OF_SECOND_CPU;
 543              i++) {
 544                 if (!image->sec[i].data)
 545                         break;
 546                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 547                 if (ret)
 548                         return ret;
 549         }
 550
 551         /* configure the ucode to start secure process on CPU1 */
 552         if (image->is_secure) {
 553                 /* config CPU1 to start secure protocol */
 554                 ret = iwl_pcie_secure_set(trans, 1);
 555                 if (ret)
 556                         return ret;
 557         } else {
 558                 /* Remove all resets to allow NIC to operate */
 559                 iwl_write32(trans, CSR_RESET, 0);
 560         }
 561
 562         if (image->is_dual_cpus) {
 563                 /* load to FW the binary sections of CPU2 */
 564                 IWL_DEBUG_INFO(trans, "working w/ DUAL CPUs - Loading CPU2\n");
 565                 for (i = IWL_UCODE_FIRST_SECTION_OF_SECOND_CPU;
 566                         i < IWL_UCODE_SECTION_MAX; i++) {
 567                         if (!image->sec[i].data)
 568                                 break;
 569                         ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 570                         if (ret)
 571                                 return ret;
 572                 }
 573
 574                 if (image->is_secure) {
 575                         /* set CPU2 for secure protocol */
 576                         ret = iwl_pcie_secure_set(trans, 2);
 577                         if (ret)
 578                                 return ret;
 579                 }
 580         }
 581
 582         return 0;
 583 }
 584
 585 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
 586                                    const struct fw_img *fw, bool run_in_rfkill)
 587 {
 588         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 589         int ret;
 590         bool hw_rfkill;
 591
 592         /* This may fail if AMT took ownership of the device */
 593         if (iwl_pcie_prepare_card_hw(trans)) {
 594                 IWL_WARN(trans, "Exit HW not ready\n");
 595                 return -EIO;
 596         }
 597
 598         clear_bit(STATUS_FW_ERROR, &trans_pcie->status);
 599
 600         iwl_enable_rfkill_int(trans);
 601
 602         /* If platform's RF_KILL switch is NOT set to KILL */
 603         hw_rfkill = iwl_is_rfkill_set(trans);
 604         if (hw_rfkill)
 605                 set_bit(STATUS_RFKILL, &trans_pcie->status);
 606         else
 607                 clear_bit(STATUS_RFKILL, &trans_pcie->status);
 608         iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
 609         if (hw_rfkill && !run_in_rfkill)
 610                 return -ERFKILL;
 611
 612         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
 613
 614         ret = iwl_pcie_nic_init(trans);
 615         if (ret) {
 616                 IWL_ERR(trans, "Unable to init nic\n");
 617                 return ret;
 618         }
 619
 620         /* make sure rfkill handshake bits are cleared */
 621         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 622         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
 623                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
 624
 625         /* clear (again), then enable host interrupts */
 626         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
 627         iwl_enable_interrupts(trans);
 628
 629         /* really make sure rfkill handshake bits are cleared */
 630         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 631         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 632
 633         /* Load the given image to the HW */
 634         return iwl_pcie_load_given_ucode(trans, fw);
 635 }
 636
 637 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
 638 {
 639         iwl_pcie_reset_ict(trans);
 640         iwl_pcie_tx_start(trans, scd_addr);
 641 }
 642
 643 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
 644 {
 645         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 646         unsigned long flags;
 647
 648         /* tell the device to stop sending interrupts */
 649         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 650         iwl_disable_interrupts(trans);
 651         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 652
 653         /* device going down, Stop using ICT table */
 654         iwl_pcie_disable_ict(trans);
 655
 656         /*
 657          * If a HW restart happens during firmware loading,
 658          * then the firmware loading might call this function
 659          * and later it might be called again due to the
 660          * restart. So don't process again if the device is
 661          * already dead.
 662          */
 663         if (test_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status)) {
 664                 iwl_pcie_tx_stop(trans);
 665                 iwl_pcie_rx_stop(trans);
 666
 667                 /* Power-down device's busmaster DMA clocks */
 668                 iwl_write_prph(trans, APMG_CLK_DIS_REG,
 669                                APMG_CLK_VAL_DMA_CLK_RQT);
 670                 udelay(5);
 671         }
 672
 673         /* Make sure (redundant) we've released our request to stay awake */
 674         iwl_clear_bit(trans, CSR_GP_CNTRL,
 675                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 676
 677         /* Stop the device, and put it in low power state */
 678         iwl_pcie_apm_stop(trans);
 679
 680         /* Upon stop, the APM issues an interrupt if HW RF kill is set.
 681          * Clean again the interrupt here
 682          */
 683         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 684         iwl_disable_interrupts(trans);
 685         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 686
 687         iwl_enable_rfkill_int(trans);
 688
 689         /* stop and reset the on-board processor */
 690         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
 691
 692         /* clear all status bits */
 693         clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
 694         clear_bit(STATUS_INT_ENABLED, &trans_pcie->status);
 695         clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
 696         clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
 697         clear_bit(STATUS_RFKILL, &trans_pcie->status);
 698 }
 699
 700 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test)
 701 {
 702         iwl_disable_interrupts(trans);
 703
 704         /*
 705          * in testing mode, the host stays awake and the
 706          * hardware won't be reset (not even partially)
 707          */
 708         if (test)
 709                 return;
 710
 711         iwl_pcie_disable_ict(trans);
 712
 713         iwl_clear_bit(trans, CSR_GP_CNTRL,
 714                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 715         iwl_clear_bit(trans, CSR_GP_CNTRL,
 716                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 717
 718         /*
 719          * reset TX queues -- some of their registers reset during S3
 720          * so if we don't reset everything here the D3 image would try
 721          * to execute some invalid memory upon resume
 722          */
 723         iwl_trans_pcie_tx_reset(trans);
 724
 725         iwl_pcie_set_pwr(trans, true);
 726 }
 727
 728 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
 729                                     enum iwl_d3_status *status,
 730                                     bool test)
 731 {
 732         u32 val;
 733         int ret;
 734
 735         if (test) {
 736                 iwl_enable_interrupts(trans);
 737                 *status = IWL_D3_STATUS_ALIVE;
 738                 return 0;
 739         }
 740
 741         iwl_pcie_set_pwr(trans, false);
 742
 743         val = iwl_read32(trans, CSR_RESET);
 744         if (val & CSR_RESET_REG_FLAG_NEVO_RESET) {
 745                 *status = IWL_D3_STATUS_RESET;
 746                 return 0;
 747         }
 748
 749         /*
 750          * Also enables interrupts - none will happen as the device doesn't
 751          * know we're waking it up, only when the opmode actually tells it
 752          * after this call.
 753          */
 754         iwl_pcie_reset_ict(trans);
 755
 756         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 757         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 758
 759         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 760                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 761                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 762                            25000);
 763         if (ret) {
 764                 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
 765                 return ret;
 766         }
 767
 768         iwl_trans_pcie_tx_reset(trans);
 769
 770         ret = iwl_pcie_rx_init(trans);
 771         if (ret) {
 772                 IWL_ERR(trans, "Failed to resume the device (RX reset)\n");
 773                 return ret;
 774         }
 775
 776         *status = IWL_D3_STATUS_ALIVE;
 777         return 0;
 778 }
 779
 780 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
 781 {
 782         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 783         bool hw_rfkill;
 784         int err;
 785
 786         err = iwl_pcie_prepare_card_hw(trans);
 787         if (err) {
 788                 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
 789                 return err;
 790         }
 791
 792         /* Reset the entire device */
 793         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 794
 795         usleep_range(10, 15);
 796
 797         iwl_pcie_apm_init(trans);
 798
 799         /* From now on, the op_mode will be kept updated about RF kill state */
 800         iwl_enable_rfkill_int(trans);
 801
 802         hw_rfkill = iwl_is_rfkill_set(trans);
 803         if (hw_rfkill)
 804                 set_bit(STATUS_RFKILL, &trans_pcie->status);
 805         else
 806                 clear_bit(STATUS_RFKILL, &trans_pcie->status);
 807         iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
 808
 809         return 0;
 810 }
 811
 812 static void iwl_trans_pcie_stop_hw(struct iwl_trans *trans,
 813                                    bool op_mode_leaving)
 814 {
 815         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 816         bool hw_rfkill;
 817         unsigned long flags;
 818
 819         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 820         iwl_disable_interrupts(trans);
 821         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 822
 823         iwl_pcie_apm_stop(trans);
 824
 825         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 826         iwl_disable_interrupts(trans);
 827         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 828
 829         iwl_pcie_disable_ict(trans);
 830
 831         if (!op_mode_leaving) {
 832                 /*
 833                  * Even if we stop the HW, we still want the RF kill
 834                  * interrupt
 835                  */
 836                 iwl_enable_rfkill_int(trans);
 837
 838                 /*
 839                  * Check again since the RF kill state may have changed while
 840                  * all the interrupts were disabled, in this case we couldn't
 841                  * receive the RF kill interrupt and update the state in the
 842                  * op_mode.
 843                  */
 844                 hw_rfkill = iwl_is_rfkill_set(trans);
 845                 if (hw_rfkill)
 846                         set_bit(STATUS_RFKILL, &trans_pcie->status);
 847                 else
 848                         clear_bit(STATUS_RFKILL, &trans_pcie->status);
 849                 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
 850         }
 851 }
 852
 853 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
 854 {
 855         writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
 856 }
 857
 858 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
 859 {
 860         writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
 861 }
 862
 863 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
 864 {
 865         return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
 866 }
 867
 868 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
 869 {
 870         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
 871                                ((reg & 0x000FFFFF) | (3 << 24)));
 872         return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
 873 }
 874
 875 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
 876                                       u32 val)
 877 {
 878         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
 879                                ((addr & 0x000FFFFF) | (3 << 24)));
 880         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
 881 }
 882
 883 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
 884                                      const struct iwl_trans_config *trans_cfg)
 885 {
 886         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 887
 888         trans_pcie->cmd_queue = trans_cfg->cmd_queue;
 889         trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
 890         if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
 891                 trans_pcie->n_no_reclaim_cmds = 0;
 892         else
 893                 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
 894         if (trans_pcie->n_no_reclaim_cmds)
 895                 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
 896                        trans_pcie->n_no_reclaim_cmds * sizeof(u8));
 897
 898         trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
 899         if (trans_pcie->rx_buf_size_8k)
 900                 trans_pcie->rx_page_order = get_order(8 * 1024);
 901         else
 902                 trans_pcie->rx_page_order = get_order(4 * 1024);
 903
 904         trans_pcie->wd_timeout =
 905                 msecs_to_jiffies(trans_cfg->queue_watchdog_timeout);
 906
 907         trans_pcie->command_names = trans_cfg->command_names;
 908         trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
 909 }
 910
 911 void iwl_trans_pcie_free(struct iwl_trans *trans)
 912 {
 913         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 914
 915         synchronize_irq(trans_pcie->pci_dev->irq);
 916
 917         iwl_pcie_tx_free(trans);
 918         iwl_pcie_rx_free(trans);
 919
 920         free_irq(trans_pcie->pci_dev->irq, trans);
 921         iwl_pcie_free_ict(trans);
 922
 923         pci_disable_msi(trans_pcie->pci_dev);
 924         iounmap(trans_pcie->hw_base);
 925         pci_release_regions(trans_pcie->pci_dev);
 926         pci_disable_device(trans_pcie->pci_dev);
 927         kmem_cache_destroy(trans->dev_cmd_pool);
 928
 929         kfree(trans);
 930 }
 931
 932 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
 933 {
 934         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 935
 936         if (state)
 937                 set_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
 938         else
 939                 clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
 940 }
 941
 942 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent,
 943                                                 unsigned long *flags)
 944 {
 945         int ret;
 946         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 947
 948         spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
 949
 950         /* this bit wakes up the NIC */
 951         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
 952                                  CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 953
 954         /*
 955          * These bits say the device is running, and should keep running for
 956          * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
 957          * but they do not indicate that embedded SRAM is restored yet;
 958          * 3945 and 4965 have volatile SRAM, and must save/restore contents
 959          * to/from host DRAM when sleeping/waking for power-saving.
 960          * Each direction takes approximately 1/4 millisecond; with this
 961          * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
 962          * series of register accesses are expected (e.g. reading Event Log),
 963          * to keep device from sleeping.
 964          *
 965          * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
 966          * SRAM is okay/restored.  We don't check that here because this call
 967          * is just for hardware register access; but GP1 MAC_SLEEP check is a
 968          * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
 969          *
 970          * 5000 series and later (including 1000 series) have non-volatile SRAM,
 971          * and do not save/restore SRAM when power cycling.
 972          */
 973         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 974                            CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
 975                            (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
 976                             CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
 977         if (unlikely(ret < 0)) {
 978                 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
 979                 if (!silent) {
 980                         u32 val = iwl_read32(trans, CSR_GP_CNTRL);
 981                         WARN_ONCE(1,
 982                                   "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
 983                                   val);
 984                         spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
 985                         return false;
 986                 }
 987         }
 988
 989         /*
 990          * Fool sparse by faking we release the lock - sparse will
 991          * track nic_access anyway.
 992          */
 993         __release(&trans_pcie->reg_lock);
 994         return true;
 995 }
 996
 997 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
 998                                               unsigned long *flags)
 999 {
1000         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1001
1002         lockdep_assert_held(&trans_pcie->reg_lock);
1003
1004         /*
1005          * Fool sparse by faking we acquiring the lock - sparse will
1006          * track nic_access anyway.
1007          */
1008         __acquire(&trans_pcie->reg_lock);
1009
1010         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1011                                    CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1012         /*
1013          * Above we read the CSR_GP_CNTRL register, which will flush
1014          * any previous writes, but we need the write that clears the
1015          * MAC_ACCESS_REQ bit to be performed before any other writes
1016          * scheduled on different CPUs (after we drop reg_lock).
1017          */
1018         mmiowb();
1019         spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1020 }
1021
1022 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1023                                    void *buf, int dwords)
1024 {
1025         unsigned long flags;
1026         int offs, ret = 0;
1027         u32 *vals = buf;
1028
1029         if (iwl_trans_grab_nic_access(trans, false, &flags)) {
1030                 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
1031                 for (offs = 0; offs < dwords; offs++)
1032                         vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
1033                 iwl_trans_release_nic_access(trans, &flags);
1034         } else {
1035                 ret = -EBUSY;
1036         }
1037         return ret;
1038 }
1039
1040 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
1041                                     const void *buf, int dwords)
1042 {
1043         unsigned long flags;
1044         int offs, ret = 0;
1045         const u32 *vals = buf;
1046
1047         if (iwl_trans_grab_nic_access(trans, false, &flags)) {
1048                 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
1049                 for (offs = 0; offs < dwords; offs++)
1050                         iwl_write32(trans, HBUS_TARG_MEM_WDAT,
1051                                     vals ? vals[offs] : 0);
1052                 iwl_trans_release_nic_access(trans, &flags);
1053         } else {
1054                 ret = -EBUSY;
1055         }
1056         return ret;
1057 }
1058
1059 #define IWL_FLUSH_WAIT_MS       2000
1060
1061 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans)
1062 {
1063         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1064         struct iwl_txq *txq;
1065         struct iwl_queue *q;
1066         int cnt;
1067         unsigned long now = jiffies;
1068         u32 scd_sram_addr;
1069         u8 buf[16];
1070         int ret = 0;
1071
1072         /* waiting for all the tx frames complete might take a while */
1073         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1074                 if (cnt == trans_pcie->cmd_queue)
1075                         continue;
1076                 txq = &trans_pcie->txq[cnt];
1077                 q = &txq->q;
1078                 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1079                        now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1080                         msleep(1);
1081
1082                 if (q->read_ptr != q->write_ptr) {
1083                         IWL_ERR(trans,
1084                                 "fail to flush all tx fifo queues Q %d\n", cnt);
1085                         ret = -ETIMEDOUT;
1086                         break;
1087                 }
1088         }
1089
1090         if (!ret)
1091                 return 0;
1092
1093         IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1094                 txq->q.read_ptr, txq->q.write_ptr);
1095
1096         scd_sram_addr = trans_pcie->scd_base_addr +
1097                         SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
1098         iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
1099
1100         iwl_print_hex_error(trans, buf, sizeof(buf));
1101
1102         for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
1103                 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
1104                         iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
1105
1106         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1107                 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
1108                 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
1109                 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
1110                 u32 tbl_dw =
1111                         iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
1112                                              SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
1113
1114                 if (cnt & 0x1)
1115                         tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
1116                 else
1117                         tbl_dw = tbl_dw & 0x0000FFFF;
1118
1119                 IWL_ERR(trans,
1120                         "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
1121                         cnt, active ? "" : "in", fifo, tbl_dw,
1122                         iwl_read_prph(trans,
1123                                       SCD_QUEUE_RDPTR(cnt)) & (txq->q.n_bd - 1),
1124                         iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1125         }
1126
1127         return ret;
1128 }
1129
1130 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
1131                                          u32 mask, u32 value)
1132 {
1133         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1134         unsigned long flags;
1135
1136         spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1137         __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
1138         spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1139 }
1140
1141 static const char *get_csr_string(int cmd)
1142 {
1143 #define IWL_CMD(x) case x: return #x
1144         switch (cmd) {
1145         IWL_CMD(CSR_HW_IF_CONFIG_REG);
1146         IWL_CMD(CSR_INT_COALESCING);
1147         IWL_CMD(CSR_INT);
1148         IWL_CMD(CSR_INT_MASK);
1149         IWL_CMD(CSR_FH_INT_STATUS);
1150         IWL_CMD(CSR_GPIO_IN);
1151         IWL_CMD(CSR_RESET);
1152         IWL_CMD(CSR_GP_CNTRL);
1153         IWL_CMD(CSR_HW_REV);
1154         IWL_CMD(CSR_EEPROM_REG);
1155         IWL_CMD(CSR_EEPROM_GP);
1156         IWL_CMD(CSR_OTP_GP_REG);
1157         IWL_CMD(CSR_GIO_REG);
1158         IWL_CMD(CSR_GP_UCODE_REG);
1159         IWL_CMD(CSR_GP_DRIVER_REG);
1160         IWL_CMD(CSR_UCODE_DRV_GP1);
1161         IWL_CMD(CSR_UCODE_DRV_GP2);
1162         IWL_CMD(CSR_LED_REG);
1163         IWL_CMD(CSR_DRAM_INT_TBL_REG);
1164         IWL_CMD(CSR_GIO_CHICKEN_BITS);
1165         IWL_CMD(CSR_ANA_PLL_CFG);
1166         IWL_CMD(CSR_HW_REV_WA_REG);
1167         IWL_CMD(CSR_DBG_HPET_MEM_REG);
1168         default:
1169                 return "UNKNOWN";
1170         }
1171 #undef IWL_CMD
1172 }
1173
1174 void iwl_pcie_dump_csr(struct iwl_trans *trans)
1175 {
1176         int i;
1177         static const u32 csr_tbl[] = {
1178                 CSR_HW_IF_CONFIG_REG,
1179                 CSR_INT_COALESCING,
1180                 CSR_INT,
1181                 CSR_INT_MASK,
1182                 CSR_FH_INT_STATUS,
1183                 CSR_GPIO_IN,
1184                 CSR_RESET,
1185                 CSR_GP_CNTRL,
1186                 CSR_HW_REV,
1187                 CSR_EEPROM_REG,
1188                 CSR_EEPROM_GP,
1189                 CSR_OTP_GP_REG,
1190                 CSR_GIO_REG,
1191                 CSR_GP_UCODE_REG,
1192                 CSR_GP_DRIVER_REG,
1193                 CSR_UCODE_DRV_GP1,
1194                 CSR_UCODE_DRV_GP2,
1195                 CSR_LED_REG,
1196                 CSR_DRAM_INT_TBL_REG,
1197                 CSR_GIO_CHICKEN_BITS,
1198                 CSR_ANA_PLL_CFG,
1199                 CSR_HW_REV_WA_REG,
1200                 CSR_DBG_HPET_MEM_REG
1201         };
1202         IWL_ERR(trans, "CSR values:\n");
1203         IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1204                 "CSR_INT_PERIODIC_REG)\n");
1205         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
1206                 IWL_ERR(trans, "  %25s: 0X%08x\n",
1207                         get_csr_string(csr_tbl[i]),
1208                         iwl_read32(trans, csr_tbl[i]));
1209         }
1210 }
1211
1212 #ifdef CONFIG_IWLWIFI_DEBUGFS
1213 /* create and remove of files */
1214 #define DEBUGFS_ADD_FILE(name, parent, mode) do {                       \
1215         if (!debugfs_create_file(#name, mode, parent, trans,            \
1216                                  &iwl_dbgfs_##name##_ops))              \
1217                 goto err;                                               \
1218 } while (0)
1219
1220 /* file operation */
1221 #define DEBUGFS_READ_FILE_OPS(name)                                     \
1222 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1223         .read = iwl_dbgfs_##name##_read,                                \
1224         .open = simple_open,                                            \
1225         .llseek = generic_file_llseek,                                  \
1226 };
1227
1228 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
1229 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1230         .write = iwl_dbgfs_##name##_write,                              \
1231         .open = simple_open,                                            \
1232         .llseek = generic_file_llseek,                                  \
1233 };
1234
1235 #define DEBUGFS_READ_WRITE_FILE_OPS(name)                               \
1236 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1237         .write = iwl_dbgfs_##name##_write,                              \
1238         .read = iwl_dbgfs_##name##_read,                                \
1239         .open = simple_open,                                            \
1240         .llseek = generic_file_llseek,                                  \
1241 };
1242
1243 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1244                                        char __user *user_buf,
1245                                        size_t count, loff_t *ppos)
1246 {
1247         struct iwl_trans *trans = file->private_data;
1248         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1249         struct iwl_txq *txq;
1250         struct iwl_queue *q;
1251         char *buf;
1252         int pos = 0;
1253         int cnt;
1254         int ret;
1255         size_t bufsz;
1256
1257         bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues;
1258
1259         if (!trans_pcie->txq)
1260                 return -EAGAIN;
1261
1262         buf = kzalloc(bufsz, GFP_KERNEL);
1263         if (!buf)
1264                 return -ENOMEM;
1265
1266         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1267                 txq = &trans_pcie->txq[cnt];
1268                 q = &txq->q;
1269                 pos += scnprintf(buf + pos, bufsz - pos,
1270                                 "hwq %.2d: read=%u write=%u use=%d stop=%d\n",
1271                                 cnt, q->read_ptr, q->write_ptr,
1272                                 !!test_bit(cnt, trans_pcie->queue_used),
1273                                 !!test_bit(cnt, trans_pcie->queue_stopped));
1274         }
1275         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1276         kfree(buf);
1277         return ret;
1278 }
1279
1280 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1281                                        char __user *user_buf,
1282                                        size_t count, loff_t *ppos)
1283 {
1284         struct iwl_trans *trans = file->private_data;
1285         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1286         struct iwl_rxq *rxq = &trans_pcie->rxq;
1287         char buf[256];
1288         int pos = 0;
1289         const size_t bufsz = sizeof(buf);
1290
1291         pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1292                                                 rxq->read);
1293         pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1294                                                 rxq->write);
1295         pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1296                                                 rxq->free_count);
1297         if (rxq->rb_stts) {
1298                 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1299                          le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF);
1300         } else {
1301                 pos += scnprintf(buf + pos, bufsz - pos,
1302                                         "closed_rb_num: Not Allocated\n");
1303         }
1304         return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1305 }
1306
1307 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1308                                         char __user *user_buf,
1309                                         size_t count, loff_t *ppos)
1310 {
1311         struct iwl_trans *trans = file->private_data;
1312         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1313         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1314
1315         int pos = 0;
1316         char *buf;
1317         int bufsz = 24 * 64; /* 24 items * 64 char per item */
1318         ssize_t ret;
1319
1320         buf = kzalloc(bufsz, GFP_KERNEL);
1321         if (!buf)
1322                 return -ENOMEM;
1323
1324         pos += scnprintf(buf + pos, bufsz - pos,
1325                         "Interrupt Statistics Report:\n");
1326
1327         pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1328                 isr_stats->hw);
1329         pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1330                 isr_stats->sw);
1331         if (isr_stats->sw || isr_stats->hw) {
1332                 pos += scnprintf(buf + pos, bufsz - pos,
1333                         "\tLast Restarting Code:  0x%X\n",
1334                         isr_stats->err_code);
1335         }
1336 #ifdef CONFIG_IWLWIFI_DEBUG
1337         pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1338                 isr_stats->sch);
1339         pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1340                 isr_stats->alive);
1341 #endif
1342         pos += scnprintf(buf + pos, bufsz - pos,
1343                 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1344
1345         pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1346                 isr_stats->ctkill);
1347
1348         pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1349                 isr_stats->wakeup);
1350
1351         pos += scnprintf(buf + pos, bufsz - pos,
1352                 "Rx command responses:\t\t %u\n", isr_stats->rx);
1353
1354         pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1355                 isr_stats->tx);
1356
1357         pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1358                 isr_stats->unhandled);
1359
1360         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1361         kfree(buf);
1362         return ret;
1363 }
1364
1365 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1366                                          const char __user *user_buf,
1367                                          size_t count, loff_t *ppos)
1368 {
1369         struct iwl_trans *trans = file->private_data;
1370         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1371         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1372
1373         char buf[8];
1374         int buf_size;
1375         u32 reset_flag;
1376
1377         memset(buf, 0, sizeof(buf));
1378         buf_size = min(count, sizeof(buf) -  1);
1379         if (copy_from_user(buf, user_buf, buf_size))
1380                 return -EFAULT;
1381         if (sscanf(buf, "%x", &reset_flag) != 1)
1382                 return -EFAULT;
1383         if (reset_flag == 0)
1384                 memset(isr_stats, 0, sizeof(*isr_stats));
1385
1386         return count;
1387 }
1388
1389 static ssize_t iwl_dbgfs_csr_write(struct file *file,
1390                                    const char __user *user_buf,
1391                                    size_t count, loff_t *ppos)
1392 {
1393         struct iwl_trans *trans = file->private_data;
1394         char buf[8];
1395         int buf_size;
1396         int csr;
1397
1398         memset(buf, 0, sizeof(buf));
1399         buf_size = min(count, sizeof(buf) -  1);
1400         if (copy_from_user(buf, user_buf, buf_size))
1401                 return -EFAULT;
1402         if (sscanf(buf, "%d", &csr) != 1)
1403                 return -EFAULT;
1404
1405         iwl_pcie_dump_csr(trans);
1406
1407         return count;
1408 }
1409
1410 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
1411                                      char __user *user_buf,
1412                                      size_t count, loff_t *ppos)
1413 {
1414         struct iwl_trans *trans = file->private_data;
1415         char *buf = NULL;
1416         int pos = 0;
1417         ssize_t ret = -EFAULT;
1418
1419         ret = pos = iwl_dump_fh(trans, &buf);
1420         if (buf) {
1421                 ret = simple_read_from_buffer(user_buf,
1422                                               count, ppos, buf, pos);
1423                 kfree(buf);
1424         }
1425
1426         return ret;
1427 }
1428
1429 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
1430 DEBUGFS_READ_FILE_OPS(fh_reg);
1431 DEBUGFS_READ_FILE_OPS(rx_queue);
1432 DEBUGFS_READ_FILE_OPS(tx_queue);
1433 DEBUGFS_WRITE_FILE_OPS(csr);
1434
1435 /*
1436  * Create the debugfs files and directories
1437  *
1438  */
1439 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1440                                          struct dentry *dir)
1441 {
1442         DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
1443         DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1444         DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
1445         DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
1446         DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
1447         return 0;
1448
1449 err:
1450         IWL_ERR(trans, "failed to create the trans debugfs entry\n");
1451         return -ENOMEM;
1452 }
1453 #else
1454 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1455                                          struct dentry *dir)
1456 {
1457         return 0;
1458 }
1459 #endif /*CONFIG_IWLWIFI_DEBUGFS */
1460
1461 static const struct iwl_trans_ops trans_ops_pcie = {
1462         .start_hw = iwl_trans_pcie_start_hw,
1463         .stop_hw = iwl_trans_pcie_stop_hw,
1464         .fw_alive = iwl_trans_pcie_fw_alive,
1465         .start_fw = iwl_trans_pcie_start_fw,
1466         .stop_device = iwl_trans_pcie_stop_device,
1467
1468         .d3_suspend = iwl_trans_pcie_d3_suspend,
1469         .d3_resume = iwl_trans_pcie_d3_resume,
1470
1471         .send_cmd = iwl_trans_pcie_send_hcmd,
1472
1473         .tx = iwl_trans_pcie_tx,
1474         .reclaim = iwl_trans_pcie_reclaim,
1475
1476         .txq_disable = iwl_trans_pcie_txq_disable,
1477         .txq_enable = iwl_trans_pcie_txq_enable,
1478
1479         .dbgfs_register = iwl_trans_pcie_dbgfs_register,
1480
1481         .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
1482
1483         .write8 = iwl_trans_pcie_write8,
1484         .write32 = iwl_trans_pcie_write32,
1485         .read32 = iwl_trans_pcie_read32,
1486         .read_prph = iwl_trans_pcie_read_prph,
1487         .write_prph = iwl_trans_pcie_write_prph,
1488         .read_mem = iwl_trans_pcie_read_mem,
1489         .write_mem = iwl_trans_pcie_write_mem,
1490         .configure = iwl_trans_pcie_configure,
1491         .set_pmi = iwl_trans_pcie_set_pmi,
1492         .grab_nic_access = iwl_trans_pcie_grab_nic_access,
1493         .release_nic_access = iwl_trans_pcie_release_nic_access,
1494         .set_bits_mask = iwl_trans_pcie_set_bits_mask,
1495 };
1496
1497 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
1498                                        const struct pci_device_id *ent,
1499                                        const struct iwl_cfg *cfg)
1500 {
1501         struct iwl_trans_pcie *trans_pcie;
1502         struct iwl_trans *trans;
1503         u16 pci_cmd;
1504         int err;
1505
1506         trans = kzalloc(sizeof(struct iwl_trans) +
1507                         sizeof(struct iwl_trans_pcie), GFP_KERNEL);
1508         if (!trans) {
1509                 err = -ENOMEM;
1510                 goto out;
1511         }
1512
1513         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1514
1515         trans->ops = &trans_ops_pcie;
1516         trans->cfg = cfg;
1517         trans_lockdep_init(trans);
1518         trans_pcie->trans = trans;
1519         spin_lock_init(&trans_pcie->irq_lock);
1520         spin_lock_init(&trans_pcie->reg_lock);
1521         init_waitqueue_head(&trans_pcie->ucode_write_waitq);
1522
1523         err = pci_enable_device(pdev);
1524         if (err)
1525                 goto out_no_pci;
1526
1527         if (!cfg->base_params->pcie_l1_allowed) {
1528                 /*
1529                  * W/A - seems to solve weird behavior. We need to remove this
1530                  * if we don't want to stay in L1 all the time. This wastes a
1531                  * lot of power.
1532                  */
1533                 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
1534                                        PCIE_LINK_STATE_L1 |
1535                                        PCIE_LINK_STATE_CLKPM);
1536         }
1537
1538         pci_set_master(pdev);
1539
1540         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
1541         if (!err)
1542                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
1543         if (err) {
1544                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1545                 if (!err)
1546                         err = pci_set_consistent_dma_mask(pdev,
1547                                                           DMA_BIT_MASK(32));
1548                 /* both attempts failed: */
1549                 if (err) {
1550                         dev_err(&pdev->dev, "No suitable DMA available\n");
1551                         goto out_pci_disable_device;
1552                 }
1553         }
1554
1555         err = pci_request_regions(pdev, DRV_NAME);
1556         if (err) {
1557                 dev_err(&pdev->dev, "pci_request_regions failed\n");
1558                 goto out_pci_disable_device;
1559         }
1560
1561         trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
1562         if (!trans_pcie->hw_base) {
1563                 dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
1564                 err = -ENODEV;
1565                 goto out_pci_release_regions;
1566         }
1567
1568         /* We disable the RETRY_TIMEOUT register (0x41) to keep
1569          * PCI Tx retries from interfering with C3 CPU state */
1570         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
1571
1572         err = pci_enable_msi(pdev);
1573         if (err) {
1574                 dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", err);
1575                 /* enable rfkill interrupt: hw bug w/a */
1576                 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1577                 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1578                         pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1579                         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1580                 }
1581         }
1582
1583         trans->dev = &pdev->dev;
1584         trans_pcie->pci_dev = pdev;
1585         trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
1586         trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
1587         snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
1588                  "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
1589
1590         /* Initialize the wait queue for commands */
1591         init_waitqueue_head(&trans_pcie->wait_command_queue);
1592
1593         snprintf(trans->dev_cmd_pool_name, sizeof(trans->dev_cmd_pool_name),
1594                  "iwl_cmd_pool:%s", dev_name(trans->dev));
1595
1596         trans->dev_cmd_headroom = 0;
1597         trans->dev_cmd_pool =
1598                 kmem_cache_create(trans->dev_cmd_pool_name,
1599                                   sizeof(struct iwl_device_cmd)
1600                                   + trans->dev_cmd_headroom,
1601                                   sizeof(void *),
1602                                   SLAB_HWCACHE_ALIGN,
1603                                   NULL);
1604
1605         if (!trans->dev_cmd_pool) {
1606                 err = -ENOMEM;
1607                 goto out_pci_disable_msi;
1608         }
1609
1610         trans_pcie->inta_mask = CSR_INI_SET_MASK;
1611
1612         if (iwl_pcie_alloc_ict(trans))
1613                 goto out_free_cmd_pool;
1614
1615         err = request_threaded_irq(pdev->irq, iwl_pcie_isr_ict,
1616                                    iwl_pcie_irq_handler,
1617                                    IRQF_SHARED, DRV_NAME, trans);
1618         if (err) {
1619                 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
1620                 goto out_free_ict;
1621         }
1622
1623         return trans;
1624
1625 out_free_ict:
1626         iwl_pcie_free_ict(trans);
1627 out_free_cmd_pool:
1628         kmem_cache_destroy(trans->dev_cmd_pool);
1629 out_pci_disable_msi:
1630         pci_disable_msi(pdev);
1631 out_pci_release_regions:
1632         pci_release_regions(pdev);
1633 out_pci_disable_device:
1634         pci_disable_device(pdev);
1635 out_no_pci:
1636         kfree(trans);
1637 out:
1638         return ERR_PTR(err);
1639 }