Merge remote-tracking branches 'regulator/fix/88pm800', 'regulator/fix/max8973',...
[linux-drm-fsl-dcu.git] / drivers / net / usb / r8152.c
1 /*
2  *  Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License
6  * version 2 as published by the Free Software Foundation.
7  *
8  */
9
10 #include <linux/signal.h>
11 #include <linux/slab.h>
12 #include <linux/module.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/mii.h>
16 #include <linux/ethtool.h>
17 #include <linux/usb.h>
18 #include <linux/crc32.h>
19 #include <linux/if_vlan.h>
20 #include <linux/uaccess.h>
21 #include <linux/list.h>
22 #include <linux/ip.h>
23 #include <linux/ipv6.h>
24 #include <net/ip6_checksum.h>
25 #include <uapi/linux/mdio.h>
26 #include <linux/mdio.h>
27 #include <linux/usb/cdc.h>
28
29 /* Version Information */
30 #define DRIVER_VERSION "v1.08.0 (2015/01/13)"
31 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
32 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
33 #define MODULENAME "r8152"
34
35 #define R8152_PHY_ID            32
36
37 #define PLA_IDR                 0xc000
38 #define PLA_RCR                 0xc010
39 #define PLA_RMS                 0xc016
40 #define PLA_RXFIFO_CTRL0        0xc0a0
41 #define PLA_RXFIFO_CTRL1        0xc0a4
42 #define PLA_RXFIFO_CTRL2        0xc0a8
43 #define PLA_DMY_REG0            0xc0b0
44 #define PLA_FMC                 0xc0b4
45 #define PLA_CFG_WOL             0xc0b6
46 #define PLA_TEREDO_CFG          0xc0bc
47 #define PLA_MAR                 0xcd00
48 #define PLA_BACKUP              0xd000
49 #define PAL_BDC_CR              0xd1a0
50 #define PLA_TEREDO_TIMER        0xd2cc
51 #define PLA_REALWOW_TIMER       0xd2e8
52 #define PLA_LEDSEL              0xdd90
53 #define PLA_LED_FEATURE         0xdd92
54 #define PLA_PHYAR               0xde00
55 #define PLA_BOOT_CTRL           0xe004
56 #define PLA_GPHY_INTR_IMR       0xe022
57 #define PLA_EEE_CR              0xe040
58 #define PLA_EEEP_CR             0xe080
59 #define PLA_MAC_PWR_CTRL        0xe0c0
60 #define PLA_MAC_PWR_CTRL2       0xe0ca
61 #define PLA_MAC_PWR_CTRL3       0xe0cc
62 #define PLA_MAC_PWR_CTRL4       0xe0ce
63 #define PLA_WDT6_CTRL           0xe428
64 #define PLA_TCR0                0xe610
65 #define PLA_TCR1                0xe612
66 #define PLA_MTPS                0xe615
67 #define PLA_TXFIFO_CTRL         0xe618
68 #define PLA_RSTTALLY            0xe800
69 #define PLA_CR                  0xe813
70 #define PLA_CRWECR              0xe81c
71 #define PLA_CONFIG12            0xe81e  /* CONFIG1, CONFIG2 */
72 #define PLA_CONFIG34            0xe820  /* CONFIG3, CONFIG4 */
73 #define PLA_CONFIG5             0xe822
74 #define PLA_PHY_PWR             0xe84c
75 #define PLA_OOB_CTRL            0xe84f
76 #define PLA_CPCR                0xe854
77 #define PLA_MISC_0              0xe858
78 #define PLA_MISC_1              0xe85a
79 #define PLA_OCP_GPHY_BASE       0xe86c
80 #define PLA_TALLYCNT            0xe890
81 #define PLA_SFF_STS_7           0xe8de
82 #define PLA_PHYSTATUS           0xe908
83 #define PLA_BP_BA               0xfc26
84 #define PLA_BP_0                0xfc28
85 #define PLA_BP_1                0xfc2a
86 #define PLA_BP_2                0xfc2c
87 #define PLA_BP_3                0xfc2e
88 #define PLA_BP_4                0xfc30
89 #define PLA_BP_5                0xfc32
90 #define PLA_BP_6                0xfc34
91 #define PLA_BP_7                0xfc36
92 #define PLA_BP_EN               0xfc38
93
94 #define USB_USB2PHY             0xb41e
95 #define USB_SSPHYLINK2          0xb428
96 #define USB_U2P3_CTRL           0xb460
97 #define USB_CSR_DUMMY1          0xb464
98 #define USB_CSR_DUMMY2          0xb466
99 #define USB_DEV_STAT            0xb808
100 #define USB_CONNECT_TIMER       0xcbf8
101 #define USB_BURST_SIZE          0xcfc0
102 #define USB_USB_CTRL            0xd406
103 #define USB_PHY_CTRL            0xd408
104 #define USB_TX_AGG              0xd40a
105 #define USB_RX_BUF_TH           0xd40c
106 #define USB_USB_TIMER           0xd428
107 #define USB_RX_EARLY_TIMEOUT    0xd42c
108 #define USB_RX_EARLY_SIZE       0xd42e
109 #define USB_PM_CTRL_STATUS      0xd432
110 #define USB_TX_DMA              0xd434
111 #define USB_TOLERANCE           0xd490
112 #define USB_LPM_CTRL            0xd41a
113 #define USB_UPS_CTRL            0xd800
114 #define USB_MISC_0              0xd81a
115 #define USB_POWER_CUT           0xd80a
116 #define USB_AFE_CTRL2           0xd824
117 #define USB_WDT11_CTRL          0xe43c
118 #define USB_BP_BA               0xfc26
119 #define USB_BP_0                0xfc28
120 #define USB_BP_1                0xfc2a
121 #define USB_BP_2                0xfc2c
122 #define USB_BP_3                0xfc2e
123 #define USB_BP_4                0xfc30
124 #define USB_BP_5                0xfc32
125 #define USB_BP_6                0xfc34
126 #define USB_BP_7                0xfc36
127 #define USB_BP_EN               0xfc38
128
129 /* OCP Registers */
130 #define OCP_ALDPS_CONFIG        0x2010
131 #define OCP_EEE_CONFIG1         0x2080
132 #define OCP_EEE_CONFIG2         0x2092
133 #define OCP_EEE_CONFIG3         0x2094
134 #define OCP_BASE_MII            0xa400
135 #define OCP_EEE_AR              0xa41a
136 #define OCP_EEE_DATA            0xa41c
137 #define OCP_PHY_STATUS          0xa420
138 #define OCP_POWER_CFG           0xa430
139 #define OCP_EEE_CFG             0xa432
140 #define OCP_SRAM_ADDR           0xa436
141 #define OCP_SRAM_DATA           0xa438
142 #define OCP_DOWN_SPEED          0xa442
143 #define OCP_EEE_ABLE            0xa5c4
144 #define OCP_EEE_ADV             0xa5d0
145 #define OCP_EEE_LPABLE          0xa5d2
146 #define OCP_ADC_CFG             0xbc06
147
148 /* SRAM Register */
149 #define SRAM_LPF_CFG            0x8012
150 #define SRAM_10M_AMP1           0x8080
151 #define SRAM_10M_AMP2           0x8082
152 #define SRAM_IMPEDANCE          0x8084
153
154 /* PLA_RCR */
155 #define RCR_AAP                 0x00000001
156 #define RCR_APM                 0x00000002
157 #define RCR_AM                  0x00000004
158 #define RCR_AB                  0x00000008
159 #define RCR_ACPT_ALL            (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
160
161 /* PLA_RXFIFO_CTRL0 */
162 #define RXFIFO_THR1_NORMAL      0x00080002
163 #define RXFIFO_THR1_OOB         0x01800003
164
165 /* PLA_RXFIFO_CTRL1 */
166 #define RXFIFO_THR2_FULL        0x00000060
167 #define RXFIFO_THR2_HIGH        0x00000038
168 #define RXFIFO_THR2_OOB         0x0000004a
169 #define RXFIFO_THR2_NORMAL      0x00a0
170
171 /* PLA_RXFIFO_CTRL2 */
172 #define RXFIFO_THR3_FULL        0x00000078
173 #define RXFIFO_THR3_HIGH        0x00000048
174 #define RXFIFO_THR3_OOB         0x0000005a
175 #define RXFIFO_THR3_NORMAL      0x0110
176
177 /* PLA_TXFIFO_CTRL */
178 #define TXFIFO_THR_NORMAL       0x00400008
179 #define TXFIFO_THR_NORMAL2      0x01000008
180
181 /* PLA_DMY_REG0 */
182 #define ECM_ALDPS               0x0002
183
184 /* PLA_FMC */
185 #define FMC_FCR_MCU_EN          0x0001
186
187 /* PLA_EEEP_CR */
188 #define EEEP_CR_EEEP_TX         0x0002
189
190 /* PLA_WDT6_CTRL */
191 #define WDT6_SET_MODE           0x0010
192
193 /* PLA_TCR0 */
194 #define TCR0_TX_EMPTY           0x0800
195 #define TCR0_AUTO_FIFO          0x0080
196
197 /* PLA_TCR1 */
198 #define VERSION_MASK            0x7cf0
199
200 /* PLA_MTPS */
201 #define MTPS_JUMBO              (12 * 1024 / 64)
202 #define MTPS_DEFAULT            (6 * 1024 / 64)
203
204 /* PLA_RSTTALLY */
205 #define TALLY_RESET             0x0001
206
207 /* PLA_CR */
208 #define CR_RST                  0x10
209 #define CR_RE                   0x08
210 #define CR_TE                   0x04
211
212 /* PLA_CRWECR */
213 #define CRWECR_NORAML           0x00
214 #define CRWECR_CONFIG           0xc0
215
216 /* PLA_OOB_CTRL */
217 #define NOW_IS_OOB              0x80
218 #define TXFIFO_EMPTY            0x20
219 #define RXFIFO_EMPTY            0x10
220 #define LINK_LIST_READY         0x02
221 #define DIS_MCU_CLROOB          0x01
222 #define FIFO_EMPTY              (TXFIFO_EMPTY | RXFIFO_EMPTY)
223
224 /* PLA_MISC_1 */
225 #define RXDY_GATED_EN           0x0008
226
227 /* PLA_SFF_STS_7 */
228 #define RE_INIT_LL              0x8000
229 #define MCU_BORW_EN             0x4000
230
231 /* PLA_CPCR */
232 #define CPCR_RX_VLAN            0x0040
233
234 /* PLA_CFG_WOL */
235 #define MAGIC_EN                0x0001
236
237 /* PLA_TEREDO_CFG */
238 #define TEREDO_SEL              0x8000
239 #define TEREDO_WAKE_MASK        0x7f00
240 #define TEREDO_RS_EVENT_MASK    0x00fe
241 #define OOB_TEREDO_EN           0x0001
242
243 /* PAL_BDC_CR */
244 #define ALDPS_PROXY_MODE        0x0001
245
246 /* PLA_CONFIG34 */
247 #define LINK_ON_WAKE_EN         0x0010
248 #define LINK_OFF_WAKE_EN        0x0008
249
250 /* PLA_CONFIG5 */
251 #define BWF_EN                  0x0040
252 #define MWF_EN                  0x0020
253 #define UWF_EN                  0x0010
254 #define LAN_WAKE_EN             0x0002
255
256 /* PLA_LED_FEATURE */
257 #define LED_MODE_MASK           0x0700
258
259 /* PLA_PHY_PWR */
260 #define TX_10M_IDLE_EN          0x0080
261 #define PFM_PWM_SWITCH          0x0040
262
263 /* PLA_MAC_PWR_CTRL */
264 #define D3_CLK_GATED_EN         0x00004000
265 #define MCU_CLK_RATIO           0x07010f07
266 #define MCU_CLK_RATIO_MASK      0x0f0f0f0f
267 #define ALDPS_SPDWN_RATIO       0x0f87
268
269 /* PLA_MAC_PWR_CTRL2 */
270 #define EEE_SPDWN_RATIO         0x8007
271
272 /* PLA_MAC_PWR_CTRL3 */
273 #define PKT_AVAIL_SPDWN_EN      0x0100
274 #define SUSPEND_SPDWN_EN        0x0004
275 #define U1U2_SPDWN_EN           0x0002
276 #define L1_SPDWN_EN             0x0001
277
278 /* PLA_MAC_PWR_CTRL4 */
279 #define PWRSAVE_SPDWN_EN        0x1000
280 #define RXDV_SPDWN_EN           0x0800
281 #define TX10MIDLE_EN            0x0100
282 #define TP100_SPDWN_EN          0x0020
283 #define TP500_SPDWN_EN          0x0010
284 #define TP1000_SPDWN_EN         0x0008
285 #define EEE_SPDWN_EN            0x0001
286
287 /* PLA_GPHY_INTR_IMR */
288 #define GPHY_STS_MSK            0x0001
289 #define SPEED_DOWN_MSK          0x0002
290 #define SPDWN_RXDV_MSK          0x0004
291 #define SPDWN_LINKCHG_MSK       0x0008
292
293 /* PLA_PHYAR */
294 #define PHYAR_FLAG              0x80000000
295
296 /* PLA_EEE_CR */
297 #define EEE_RX_EN               0x0001
298 #define EEE_TX_EN               0x0002
299
300 /* PLA_BOOT_CTRL */
301 #define AUTOLOAD_DONE           0x0002
302
303 /* USB_USB2PHY */
304 #define USB2PHY_SUSPEND         0x0001
305 #define USB2PHY_L1              0x0002
306
307 /* USB_SSPHYLINK2 */
308 #define pwd_dn_scale_mask       0x3ffe
309 #define pwd_dn_scale(x)         ((x) << 1)
310
311 /* USB_CSR_DUMMY1 */
312 #define DYNAMIC_BURST           0x0001
313
314 /* USB_CSR_DUMMY2 */
315 #define EP4_FULL_FC             0x0001
316
317 /* USB_DEV_STAT */
318 #define STAT_SPEED_MASK         0x0006
319 #define STAT_SPEED_HIGH         0x0000
320 #define STAT_SPEED_FULL         0x0002
321
322 /* USB_TX_AGG */
323 #define TX_AGG_MAX_THRESHOLD    0x03
324
325 /* USB_RX_BUF_TH */
326 #define RX_THR_SUPPER           0x0c350180
327 #define RX_THR_HIGH             0x7a120180
328 #define RX_THR_SLOW             0xffff0180
329
330 /* USB_TX_DMA */
331 #define TEST_MODE_DISABLE       0x00000001
332 #define TX_SIZE_ADJUST1         0x00000100
333
334 /* USB_UPS_CTRL */
335 #define POWER_CUT               0x0100
336
337 /* USB_PM_CTRL_STATUS */
338 #define RESUME_INDICATE         0x0001
339
340 /* USB_USB_CTRL */
341 #define RX_AGG_DISABLE          0x0010
342
343 /* USB_U2P3_CTRL */
344 #define U2P3_ENABLE             0x0001
345
346 /* USB_POWER_CUT */
347 #define PWR_EN                  0x0001
348 #define PHASE2_EN               0x0008
349
350 /* USB_MISC_0 */
351 #define PCUT_STATUS             0x0001
352
353 /* USB_RX_EARLY_TIMEOUT */
354 #define COALESCE_SUPER           85000U
355 #define COALESCE_HIGH           250000U
356 #define COALESCE_SLOW           524280U
357
358 /* USB_WDT11_CTRL */
359 #define TIMER11_EN              0x0001
360
361 /* USB_LPM_CTRL */
362 /* bit 4 ~ 5: fifo empty boundary */
363 #define FIFO_EMPTY_1FB          0x30    /* 0x1fb * 64 = 32448 bytes */
364 /* bit 2 ~ 3: LMP timer */
365 #define LPM_TIMER_MASK          0x0c
366 #define LPM_TIMER_500MS         0x04    /* 500 ms */
367 #define LPM_TIMER_500US         0x0c    /* 500 us */
368 #define ROK_EXIT_LPM            0x02
369
370 /* USB_AFE_CTRL2 */
371 #define SEN_VAL_MASK            0xf800
372 #define SEN_VAL_NORMAL          0xa000
373 #define SEL_RXIDLE              0x0100
374
375 /* OCP_ALDPS_CONFIG */
376 #define ENPWRSAVE               0x8000
377 #define ENPDNPS                 0x0200
378 #define LINKENA                 0x0100
379 #define DIS_SDSAVE              0x0010
380
381 /* OCP_PHY_STATUS */
382 #define PHY_STAT_MASK           0x0007
383 #define PHY_STAT_LAN_ON         3
384 #define PHY_STAT_PWRDN          5
385
386 /* OCP_POWER_CFG */
387 #define EEE_CLKDIV_EN           0x8000
388 #define EN_ALDPS                0x0004
389 #define EN_10M_PLLOFF           0x0001
390
391 /* OCP_EEE_CONFIG1 */
392 #define RG_TXLPI_MSK_HFDUP      0x8000
393 #define RG_MATCLR_EN            0x4000
394 #define EEE_10_CAP              0x2000
395 #define EEE_NWAY_EN             0x1000
396 #define TX_QUIET_EN             0x0200
397 #define RX_QUIET_EN             0x0100
398 #define sd_rise_time_mask       0x0070
399 #define sd_rise_time(x)         (min(x, 7) << 4)        /* bit 4 ~ 6 */
400 #define RG_RXLPI_MSK_HFDUP      0x0008
401 #define SDFALLTIME              0x0007  /* bit 0 ~ 2 */
402
403 /* OCP_EEE_CONFIG2 */
404 #define RG_LPIHYS_NUM           0x7000  /* bit 12 ~ 15 */
405 #define RG_DACQUIET_EN          0x0400
406 #define RG_LDVQUIET_EN          0x0200
407 #define RG_CKRSEL               0x0020
408 #define RG_EEEPRG_EN            0x0010
409
410 /* OCP_EEE_CONFIG3 */
411 #define fast_snr_mask           0xff80
412 #define fast_snr(x)             (min(x, 0x1ff) << 7)    /* bit 7 ~ 15 */
413 #define RG_LFS_SEL              0x0060  /* bit 6 ~ 5 */
414 #define MSK_PH                  0x0006  /* bit 0 ~ 3 */
415
416 /* OCP_EEE_AR */
417 /* bit[15:14] function */
418 #define FUN_ADDR                0x0000
419 #define FUN_DATA                0x4000
420 /* bit[4:0] device addr */
421
422 /* OCP_EEE_CFG */
423 #define CTAP_SHORT_EN           0x0040
424 #define EEE10_EN                0x0010
425
426 /* OCP_DOWN_SPEED */
427 #define EN_10M_BGOFF            0x0080
428
429 /* OCP_ADC_CFG */
430 #define CKADSEL_L               0x0100
431 #define ADC_EN                  0x0080
432 #define EN_EMI_L                0x0040
433
434 /* SRAM_LPF_CFG */
435 #define LPF_AUTO_TUNE           0x8000
436
437 /* SRAM_10M_AMP1 */
438 #define GDAC_IB_UPALL           0x0008
439
440 /* SRAM_10M_AMP2 */
441 #define AMP_DN                  0x0200
442
443 /* SRAM_IMPEDANCE */
444 #define RX_DRIVING_MASK         0x6000
445
446 enum rtl_register_content {
447         _1000bps        = 0x10,
448         _100bps         = 0x08,
449         _10bps          = 0x04,
450         LINK_STATUS     = 0x02,
451         FULL_DUP        = 0x01,
452 };
453
454 #define RTL8152_MAX_TX          4
455 #define RTL8152_MAX_RX          10
456 #define INTBUFSIZE              2
457 #define CRC_SIZE                4
458 #define TX_ALIGN                4
459 #define RX_ALIGN                8
460
461 #define INTR_LINK               0x0004
462
463 #define RTL8152_REQT_READ       0xc0
464 #define RTL8152_REQT_WRITE      0x40
465 #define RTL8152_REQ_GET_REGS    0x05
466 #define RTL8152_REQ_SET_REGS    0x05
467
468 #define BYTE_EN_DWORD           0xff
469 #define BYTE_EN_WORD            0x33
470 #define BYTE_EN_BYTE            0x11
471 #define BYTE_EN_SIX_BYTES       0x3f
472 #define BYTE_EN_START_MASK      0x0f
473 #define BYTE_EN_END_MASK        0xf0
474
475 #define RTL8153_MAX_PACKET      9216 /* 9K */
476 #define RTL8153_MAX_MTU         (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - VLAN_HLEN)
477 #define RTL8152_RMS             (VLAN_ETH_FRAME_LEN + VLAN_HLEN)
478 #define RTL8153_RMS             RTL8153_MAX_PACKET
479 #define RTL8152_TX_TIMEOUT      (5 * HZ)
480 #define RTL8152_NAPI_WEIGHT     64
481
482 /* rtl8152 flags */
483 enum rtl8152_flags {
484         RTL8152_UNPLUG = 0,
485         RTL8152_SET_RX_MODE,
486         WORK_ENABLE,
487         RTL8152_LINK_CHG,
488         SELECTIVE_SUSPEND,
489         PHY_RESET,
490         SCHEDULE_NAPI,
491 };
492
493 /* Define these values to match your device */
494 #define VENDOR_ID_REALTEK               0x0bda
495 #define VENDOR_ID_SAMSUNG               0x04e8
496 #define VENDOR_ID_LENOVO                0x17ef
497 #define VENDOR_ID_NVIDIA                0x0955
498
499 #define MCU_TYPE_PLA                    0x0100
500 #define MCU_TYPE_USB                    0x0000
501
502 struct tally_counter {
503         __le64  tx_packets;
504         __le64  rx_packets;
505         __le64  tx_errors;
506         __le32  rx_errors;
507         __le16  rx_missed;
508         __le16  align_errors;
509         __le32  tx_one_collision;
510         __le32  tx_multi_collision;
511         __le64  rx_unicast;
512         __le64  rx_broadcast;
513         __le32  rx_multicast;
514         __le16  tx_aborted;
515         __le16  tx_underrun;
516 };
517
518 struct rx_desc {
519         __le32 opts1;
520 #define RX_LEN_MASK                     0x7fff
521
522         __le32 opts2;
523 #define RD_UDP_CS                       BIT(23)
524 #define RD_TCP_CS                       BIT(22)
525 #define RD_IPV6_CS                      BIT(20)
526 #define RD_IPV4_CS                      BIT(19)
527
528         __le32 opts3;
529 #define IPF                             BIT(23) /* IP checksum fail */
530 #define UDPF                            BIT(22) /* UDP checksum fail */
531 #define TCPF                            BIT(21) /* TCP checksum fail */
532 #define RX_VLAN_TAG                     BIT(16)
533
534         __le32 opts4;
535         __le32 opts5;
536         __le32 opts6;
537 };
538
539 struct tx_desc {
540         __le32 opts1;
541 #define TX_FS                   BIT(31) /* First segment of a packet */
542 #define TX_LS                   BIT(30) /* Final segment of a packet */
543 #define GTSENDV4                BIT(28)
544 #define GTSENDV6                BIT(27)
545 #define GTTCPHO_SHIFT           18
546 #define GTTCPHO_MAX             0x7fU
547 #define TX_LEN_MAX              0x3ffffU
548
549         __le32 opts2;
550 #define UDP_CS                  BIT(31) /* Calculate UDP/IP checksum */
551 #define TCP_CS                  BIT(30) /* Calculate TCP/IP checksum */
552 #define IPV4_CS                 BIT(29) /* Calculate IPv4 checksum */
553 #define IPV6_CS                 BIT(28) /* Calculate IPv6 checksum */
554 #define MSS_SHIFT               17
555 #define MSS_MAX                 0x7ffU
556 #define TCPHO_SHIFT             17
557 #define TCPHO_MAX               0x7ffU
558 #define TX_VLAN_TAG             BIT(16)
559 };
560
561 struct r8152;
562
563 struct rx_agg {
564         struct list_head list;
565         struct urb *urb;
566         struct r8152 *context;
567         void *buffer;
568         void *head;
569 };
570
571 struct tx_agg {
572         struct list_head list;
573         struct urb *urb;
574         struct r8152 *context;
575         void *buffer;
576         void *head;
577         u32 skb_num;
578         u32 skb_len;
579 };
580
581 struct r8152 {
582         unsigned long flags;
583         struct usb_device *udev;
584         struct napi_struct napi;
585         struct usb_interface *intf;
586         struct net_device *netdev;
587         struct urb *intr_urb;
588         struct tx_agg tx_info[RTL8152_MAX_TX];
589         struct rx_agg rx_info[RTL8152_MAX_RX];
590         struct list_head rx_done, tx_free;
591         struct sk_buff_head tx_queue, rx_queue;
592         spinlock_t rx_lock, tx_lock;
593         struct delayed_work schedule;
594         struct mii_if_info mii;
595         struct mutex control;   /* use for hw setting */
596
597         struct rtl_ops {
598                 void (*init)(struct r8152 *);
599                 int (*enable)(struct r8152 *);
600                 void (*disable)(struct r8152 *);
601                 void (*up)(struct r8152 *);
602                 void (*down)(struct r8152 *);
603                 void (*unload)(struct r8152 *);
604                 int (*eee_get)(struct r8152 *, struct ethtool_eee *);
605                 int (*eee_set)(struct r8152 *, struct ethtool_eee *);
606         } rtl_ops;
607
608         int intr_interval;
609         u32 saved_wolopts;
610         u32 msg_enable;
611         u32 tx_qlen;
612         u32 coalesce;
613         u16 ocp_base;
614         u8 *intr_buff;
615         u8 version;
616 };
617
618 enum rtl_version {
619         RTL_VER_UNKNOWN = 0,
620         RTL_VER_01,
621         RTL_VER_02,
622         RTL_VER_03,
623         RTL_VER_04,
624         RTL_VER_05,
625         RTL_VER_MAX
626 };
627
628 enum tx_csum_stat {
629         TX_CSUM_SUCCESS = 0,
630         TX_CSUM_TSO,
631         TX_CSUM_NONE
632 };
633
634 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
635  * The RTL chips use a 64 element hash table based on the Ethernet CRC.
636  */
637 static const int multicast_filter_limit = 32;
638 static unsigned int agg_buf_sz = 16384;
639
640 #define RTL_LIMITED_TSO_SIZE    (agg_buf_sz - sizeof(struct tx_desc) - \
641                                  VLAN_ETH_HLEN - VLAN_HLEN)
642
643 static
644 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
645 {
646         int ret;
647         void *tmp;
648
649         tmp = kmalloc(size, GFP_KERNEL);
650         if (!tmp)
651                 return -ENOMEM;
652
653         ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
654                               RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
655                               value, index, tmp, size, 500);
656
657         memcpy(data, tmp, size);
658         kfree(tmp);
659
660         return ret;
661 }
662
663 static
664 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
665 {
666         int ret;
667         void *tmp;
668
669         tmp = kmemdup(data, size, GFP_KERNEL);
670         if (!tmp)
671                 return -ENOMEM;
672
673         ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
674                               RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
675                               value, index, tmp, size, 500);
676
677         kfree(tmp);
678
679         return ret;
680 }
681
682 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
683                             void *data, u16 type)
684 {
685         u16 limit = 64;
686         int ret = 0;
687
688         if (test_bit(RTL8152_UNPLUG, &tp->flags))
689                 return -ENODEV;
690
691         /* both size and indix must be 4 bytes align */
692         if ((size & 3) || !size || (index & 3) || !data)
693                 return -EPERM;
694
695         if ((u32)index + (u32)size > 0xffff)
696                 return -EPERM;
697
698         while (size) {
699                 if (size > limit) {
700                         ret = get_registers(tp, index, type, limit, data);
701                         if (ret < 0)
702                                 break;
703
704                         index += limit;
705                         data += limit;
706                         size -= limit;
707                 } else {
708                         ret = get_registers(tp, index, type, size, data);
709                         if (ret < 0)
710                                 break;
711
712                         index += size;
713                         data += size;
714                         size = 0;
715                         break;
716                 }
717         }
718
719         if (ret == -ENODEV)
720                 set_bit(RTL8152_UNPLUG, &tp->flags);
721
722         return ret;
723 }
724
725 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
726                              u16 size, void *data, u16 type)
727 {
728         int ret;
729         u16 byteen_start, byteen_end, byen;
730         u16 limit = 512;
731
732         if (test_bit(RTL8152_UNPLUG, &tp->flags))
733                 return -ENODEV;
734
735         /* both size and indix must be 4 bytes align */
736         if ((size & 3) || !size || (index & 3) || !data)
737                 return -EPERM;
738
739         if ((u32)index + (u32)size > 0xffff)
740                 return -EPERM;
741
742         byteen_start = byteen & BYTE_EN_START_MASK;
743         byteen_end = byteen & BYTE_EN_END_MASK;
744
745         byen = byteen_start | (byteen_start << 4);
746         ret = set_registers(tp, index, type | byen, 4, data);
747         if (ret < 0)
748                 goto error1;
749
750         index += 4;
751         data += 4;
752         size -= 4;
753
754         if (size) {
755                 size -= 4;
756
757                 while (size) {
758                         if (size > limit) {
759                                 ret = set_registers(tp, index,
760                                                     type | BYTE_EN_DWORD,
761                                                     limit, data);
762                                 if (ret < 0)
763                                         goto error1;
764
765                                 index += limit;
766                                 data += limit;
767                                 size -= limit;
768                         } else {
769                                 ret = set_registers(tp, index,
770                                                     type | BYTE_EN_DWORD,
771                                                     size, data);
772                                 if (ret < 0)
773                                         goto error1;
774
775                                 index += size;
776                                 data += size;
777                                 size = 0;
778                                 break;
779                         }
780                 }
781
782                 byen = byteen_end | (byteen_end >> 4);
783                 ret = set_registers(tp, index, type | byen, 4, data);
784                 if (ret < 0)
785                         goto error1;
786         }
787
788 error1:
789         if (ret == -ENODEV)
790                 set_bit(RTL8152_UNPLUG, &tp->flags);
791
792         return ret;
793 }
794
795 static inline
796 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
797 {
798         return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
799 }
800
801 static inline
802 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
803 {
804         return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
805 }
806
807 static inline
808 int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
809 {
810         return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
811 }
812
813 static inline
814 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
815 {
816         return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
817 }
818
819 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
820 {
821         __le32 data;
822
823         generic_ocp_read(tp, index, sizeof(data), &data, type);
824
825         return __le32_to_cpu(data);
826 }
827
828 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
829 {
830         __le32 tmp = __cpu_to_le32(data);
831
832         generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
833 }
834
835 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
836 {
837         u32 data;
838         __le32 tmp;
839         u8 shift = index & 2;
840
841         index &= ~3;
842
843         generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
844
845         data = __le32_to_cpu(tmp);
846         data >>= (shift * 8);
847         data &= 0xffff;
848
849         return (u16)data;
850 }
851
852 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
853 {
854         u32 mask = 0xffff;
855         __le32 tmp;
856         u16 byen = BYTE_EN_WORD;
857         u8 shift = index & 2;
858
859         data &= mask;
860
861         if (index & 2) {
862                 byen <<= shift;
863                 mask <<= (shift * 8);
864                 data <<= (shift * 8);
865                 index &= ~3;
866         }
867
868         tmp = __cpu_to_le32(data);
869
870         generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
871 }
872
873 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
874 {
875         u32 data;
876         __le32 tmp;
877         u8 shift = index & 3;
878
879         index &= ~3;
880
881         generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
882
883         data = __le32_to_cpu(tmp);
884         data >>= (shift * 8);
885         data &= 0xff;
886
887         return (u8)data;
888 }
889
890 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
891 {
892         u32 mask = 0xff;
893         __le32 tmp;
894         u16 byen = BYTE_EN_BYTE;
895         u8 shift = index & 3;
896
897         data &= mask;
898
899         if (index & 3) {
900                 byen <<= shift;
901                 mask <<= (shift * 8);
902                 data <<= (shift * 8);
903                 index &= ~3;
904         }
905
906         tmp = __cpu_to_le32(data);
907
908         generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
909 }
910
911 static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
912 {
913         u16 ocp_base, ocp_index;
914
915         ocp_base = addr & 0xf000;
916         if (ocp_base != tp->ocp_base) {
917                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
918                 tp->ocp_base = ocp_base;
919         }
920
921         ocp_index = (addr & 0x0fff) | 0xb000;
922         return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
923 }
924
925 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
926 {
927         u16 ocp_base, ocp_index;
928
929         ocp_base = addr & 0xf000;
930         if (ocp_base != tp->ocp_base) {
931                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
932                 tp->ocp_base = ocp_base;
933         }
934
935         ocp_index = (addr & 0x0fff) | 0xb000;
936         ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
937 }
938
939 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
940 {
941         ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
942 }
943
944 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
945 {
946         return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
947 }
948
949 static void sram_write(struct r8152 *tp, u16 addr, u16 data)
950 {
951         ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
952         ocp_reg_write(tp, OCP_SRAM_DATA, data);
953 }
954
955 static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
956 {
957         struct r8152 *tp = netdev_priv(netdev);
958         int ret;
959
960         if (test_bit(RTL8152_UNPLUG, &tp->flags))
961                 return -ENODEV;
962
963         if (phy_id != R8152_PHY_ID)
964                 return -EINVAL;
965
966         ret = r8152_mdio_read(tp, reg);
967
968         return ret;
969 }
970
971 static
972 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
973 {
974         struct r8152 *tp = netdev_priv(netdev);
975
976         if (test_bit(RTL8152_UNPLUG, &tp->flags))
977                 return;
978
979         if (phy_id != R8152_PHY_ID)
980                 return;
981
982         r8152_mdio_write(tp, reg, val);
983 }
984
985 static int
986 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
987
988 static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
989 {
990         struct r8152 *tp = netdev_priv(netdev);
991         struct sockaddr *addr = p;
992         int ret = -EADDRNOTAVAIL;
993
994         if (!is_valid_ether_addr(addr->sa_data))
995                 goto out1;
996
997         ret = usb_autopm_get_interface(tp->intf);
998         if (ret < 0)
999                 goto out1;
1000
1001         mutex_lock(&tp->control);
1002
1003         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1004
1005         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1006         pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
1007         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1008
1009         mutex_unlock(&tp->control);
1010
1011         usb_autopm_put_interface(tp->intf);
1012 out1:
1013         return ret;
1014 }
1015
1016 static int set_ethernet_addr(struct r8152 *tp)
1017 {
1018         struct net_device *dev = tp->netdev;
1019         struct sockaddr sa;
1020         int ret;
1021
1022         if (tp->version == RTL_VER_01)
1023                 ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data);
1024         else
1025                 ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data);
1026
1027         if (ret < 0) {
1028                 netif_err(tp, probe, dev, "Get ether addr fail\n");
1029         } else if (!is_valid_ether_addr(sa.sa_data)) {
1030                 netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1031                           sa.sa_data);
1032                 eth_hw_addr_random(dev);
1033                 ether_addr_copy(sa.sa_data, dev->dev_addr);
1034                 ret = rtl8152_set_mac_address(dev, &sa);
1035                 netif_info(tp, probe, dev, "Random ether addr %pM\n",
1036                            sa.sa_data);
1037         } else {
1038                 if (tp->version == RTL_VER_01)
1039                         ether_addr_copy(dev->dev_addr, sa.sa_data);
1040                 else
1041                         ret = rtl8152_set_mac_address(dev, &sa);
1042         }
1043
1044         return ret;
1045 }
1046
1047 static void read_bulk_callback(struct urb *urb)
1048 {
1049         struct net_device *netdev;
1050         int status = urb->status;
1051         struct rx_agg *agg;
1052         struct r8152 *tp;
1053
1054         agg = urb->context;
1055         if (!agg)
1056                 return;
1057
1058         tp = agg->context;
1059         if (!tp)
1060                 return;
1061
1062         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1063                 return;
1064
1065         if (!test_bit(WORK_ENABLE, &tp->flags))
1066                 return;
1067
1068         netdev = tp->netdev;
1069
1070         /* When link down, the driver would cancel all bulks. */
1071         /* This avoid the re-submitting bulk */
1072         if (!netif_carrier_ok(netdev))
1073                 return;
1074
1075         usb_mark_last_busy(tp->udev);
1076
1077         switch (status) {
1078         case 0:
1079                 if (urb->actual_length < ETH_ZLEN)
1080                         break;
1081
1082                 spin_lock(&tp->rx_lock);
1083                 list_add_tail(&agg->list, &tp->rx_done);
1084                 spin_unlock(&tp->rx_lock);
1085                 napi_schedule(&tp->napi);
1086                 return;
1087         case -ESHUTDOWN:
1088                 set_bit(RTL8152_UNPLUG, &tp->flags);
1089                 netif_device_detach(tp->netdev);
1090                 return;
1091         case -ENOENT:
1092                 return; /* the urb is in unlink state */
1093         case -ETIME:
1094                 if (net_ratelimit())
1095                         netdev_warn(netdev, "maybe reset is needed?\n");
1096                 break;
1097         default:
1098                 if (net_ratelimit())
1099                         netdev_warn(netdev, "Rx status %d\n", status);
1100                 break;
1101         }
1102
1103         r8152_submit_rx(tp, agg, GFP_ATOMIC);
1104 }
1105
1106 static void write_bulk_callback(struct urb *urb)
1107 {
1108         struct net_device_stats *stats;
1109         struct net_device *netdev;
1110         struct tx_agg *agg;
1111         struct r8152 *tp;
1112         int status = urb->status;
1113
1114         agg = urb->context;
1115         if (!agg)
1116                 return;
1117
1118         tp = agg->context;
1119         if (!tp)
1120                 return;
1121
1122         netdev = tp->netdev;
1123         stats = &netdev->stats;
1124         if (status) {
1125                 if (net_ratelimit())
1126                         netdev_warn(netdev, "Tx status %d\n", status);
1127                 stats->tx_errors += agg->skb_num;
1128         } else {
1129                 stats->tx_packets += agg->skb_num;
1130                 stats->tx_bytes += agg->skb_len;
1131         }
1132
1133         spin_lock(&tp->tx_lock);
1134         list_add_tail(&agg->list, &tp->tx_free);
1135         spin_unlock(&tp->tx_lock);
1136
1137         usb_autopm_put_interface_async(tp->intf);
1138
1139         if (!netif_carrier_ok(netdev))
1140                 return;
1141
1142         if (!test_bit(WORK_ENABLE, &tp->flags))
1143                 return;
1144
1145         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1146                 return;
1147
1148         if (!skb_queue_empty(&tp->tx_queue))
1149                 napi_schedule(&tp->napi);
1150 }
1151
1152 static void intr_callback(struct urb *urb)
1153 {
1154         struct r8152 *tp;
1155         __le16 *d;
1156         int status = urb->status;
1157         int res;
1158
1159         tp = urb->context;
1160         if (!tp)
1161                 return;
1162
1163         if (!test_bit(WORK_ENABLE, &tp->flags))
1164                 return;
1165
1166         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1167                 return;
1168
1169         switch (status) {
1170         case 0:                 /* success */
1171                 break;
1172         case -ECONNRESET:       /* unlink */
1173         case -ESHUTDOWN:
1174                 netif_device_detach(tp->netdev);
1175         case -ENOENT:
1176         case -EPROTO:
1177                 netif_info(tp, intr, tp->netdev,
1178                            "Stop submitting intr, status %d\n", status);
1179                 return;
1180         case -EOVERFLOW:
1181                 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1182                 goto resubmit;
1183         /* -EPIPE:  should clear the halt */
1184         default:
1185                 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1186                 goto resubmit;
1187         }
1188
1189         d = urb->transfer_buffer;
1190         if (INTR_LINK & __le16_to_cpu(d[0])) {
1191                 if (!netif_carrier_ok(tp->netdev)) {
1192                         set_bit(RTL8152_LINK_CHG, &tp->flags);
1193                         schedule_delayed_work(&tp->schedule, 0);
1194                 }
1195         } else {
1196                 if (netif_carrier_ok(tp->netdev)) {
1197                         set_bit(RTL8152_LINK_CHG, &tp->flags);
1198                         schedule_delayed_work(&tp->schedule, 0);
1199                 }
1200         }
1201
1202 resubmit:
1203         res = usb_submit_urb(urb, GFP_ATOMIC);
1204         if (res == -ENODEV) {
1205                 set_bit(RTL8152_UNPLUG, &tp->flags);
1206                 netif_device_detach(tp->netdev);
1207         } else if (res) {
1208                 netif_err(tp, intr, tp->netdev,
1209                           "can't resubmit intr, status %d\n", res);
1210         }
1211 }
1212
1213 static inline void *rx_agg_align(void *data)
1214 {
1215         return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
1216 }
1217
1218 static inline void *tx_agg_align(void *data)
1219 {
1220         return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
1221 }
1222
1223 static void free_all_mem(struct r8152 *tp)
1224 {
1225         int i;
1226
1227         for (i = 0; i < RTL8152_MAX_RX; i++) {
1228                 usb_free_urb(tp->rx_info[i].urb);
1229                 tp->rx_info[i].urb = NULL;
1230
1231                 kfree(tp->rx_info[i].buffer);
1232                 tp->rx_info[i].buffer = NULL;
1233                 tp->rx_info[i].head = NULL;
1234         }
1235
1236         for (i = 0; i < RTL8152_MAX_TX; i++) {
1237                 usb_free_urb(tp->tx_info[i].urb);
1238                 tp->tx_info[i].urb = NULL;
1239
1240                 kfree(tp->tx_info[i].buffer);
1241                 tp->tx_info[i].buffer = NULL;
1242                 tp->tx_info[i].head = NULL;
1243         }
1244
1245         usb_free_urb(tp->intr_urb);
1246         tp->intr_urb = NULL;
1247
1248         kfree(tp->intr_buff);
1249         tp->intr_buff = NULL;
1250 }
1251
1252 static int alloc_all_mem(struct r8152 *tp)
1253 {
1254         struct net_device *netdev = tp->netdev;
1255         struct usb_interface *intf = tp->intf;
1256         struct usb_host_interface *alt = intf->cur_altsetting;
1257         struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
1258         struct urb *urb;
1259         int node, i;
1260         u8 *buf;
1261
1262         node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1263
1264         spin_lock_init(&tp->rx_lock);
1265         spin_lock_init(&tp->tx_lock);
1266         INIT_LIST_HEAD(&tp->tx_free);
1267         skb_queue_head_init(&tp->tx_queue);
1268         skb_queue_head_init(&tp->rx_queue);
1269
1270         for (i = 0; i < RTL8152_MAX_RX; i++) {
1271                 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1272                 if (!buf)
1273                         goto err1;
1274
1275                 if (buf != rx_agg_align(buf)) {
1276                         kfree(buf);
1277                         buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL,
1278                                            node);
1279                         if (!buf)
1280                                 goto err1;
1281                 }
1282
1283                 urb = usb_alloc_urb(0, GFP_KERNEL);
1284                 if (!urb) {
1285                         kfree(buf);
1286                         goto err1;
1287                 }
1288
1289                 INIT_LIST_HEAD(&tp->rx_info[i].list);
1290                 tp->rx_info[i].context = tp;
1291                 tp->rx_info[i].urb = urb;
1292                 tp->rx_info[i].buffer = buf;
1293                 tp->rx_info[i].head = rx_agg_align(buf);
1294         }
1295
1296         for (i = 0; i < RTL8152_MAX_TX; i++) {
1297                 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1298                 if (!buf)
1299                         goto err1;
1300
1301                 if (buf != tx_agg_align(buf)) {
1302                         kfree(buf);
1303                         buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
1304                                            node);
1305                         if (!buf)
1306                                 goto err1;
1307                 }
1308
1309                 urb = usb_alloc_urb(0, GFP_KERNEL);
1310                 if (!urb) {
1311                         kfree(buf);
1312                         goto err1;
1313                 }
1314
1315                 INIT_LIST_HEAD(&tp->tx_info[i].list);
1316                 tp->tx_info[i].context = tp;
1317                 tp->tx_info[i].urb = urb;
1318                 tp->tx_info[i].buffer = buf;
1319                 tp->tx_info[i].head = tx_agg_align(buf);
1320
1321                 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1322         }
1323
1324         tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1325         if (!tp->intr_urb)
1326                 goto err1;
1327
1328         tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1329         if (!tp->intr_buff)
1330                 goto err1;
1331
1332         tp->intr_interval = (int)ep_intr->desc.bInterval;
1333         usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
1334                          tp->intr_buff, INTBUFSIZE, intr_callback,
1335                          tp, tp->intr_interval);
1336
1337         return 0;
1338
1339 err1:
1340         free_all_mem(tp);
1341         return -ENOMEM;
1342 }
1343
1344 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1345 {
1346         struct tx_agg *agg = NULL;
1347         unsigned long flags;
1348
1349         if (list_empty(&tp->tx_free))
1350                 return NULL;
1351
1352         spin_lock_irqsave(&tp->tx_lock, flags);
1353         if (!list_empty(&tp->tx_free)) {
1354                 struct list_head *cursor;
1355
1356                 cursor = tp->tx_free.next;
1357                 list_del_init(cursor);
1358                 agg = list_entry(cursor, struct tx_agg, list);
1359         }
1360         spin_unlock_irqrestore(&tp->tx_lock, flags);
1361
1362         return agg;
1363 }
1364
1365 /* r8152_csum_workaround()
1366  * The hw limites the value the transport offset. When the offset is out of the
1367  * range, calculate the checksum by sw.
1368  */
1369 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
1370                                   struct sk_buff_head *list)
1371 {
1372         if (skb_shinfo(skb)->gso_size) {
1373                 netdev_features_t features = tp->netdev->features;
1374                 struct sk_buff_head seg_list;
1375                 struct sk_buff *segs, *nskb;
1376
1377                 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
1378                 segs = skb_gso_segment(skb, features);
1379                 if (IS_ERR(segs) || !segs)
1380                         goto drop;
1381
1382                 __skb_queue_head_init(&seg_list);
1383
1384                 do {
1385                         nskb = segs;
1386                         segs = segs->next;
1387                         nskb->next = NULL;
1388                         __skb_queue_tail(&seg_list, nskb);
1389                 } while (segs);
1390
1391                 skb_queue_splice(&seg_list, list);
1392                 dev_kfree_skb(skb);
1393         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1394                 if (skb_checksum_help(skb) < 0)
1395                         goto drop;
1396
1397                 __skb_queue_head(list, skb);
1398         } else {
1399                 struct net_device_stats *stats;
1400
1401 drop:
1402                 stats = &tp->netdev->stats;
1403                 stats->tx_dropped++;
1404                 dev_kfree_skb(skb);
1405         }
1406 }
1407
1408 /* msdn_giant_send_check()
1409  * According to the document of microsoft, the TCP Pseudo Header excludes the
1410  * packet length for IPv6 TCP large packets.
1411  */
1412 static int msdn_giant_send_check(struct sk_buff *skb)
1413 {
1414         const struct ipv6hdr *ipv6h;
1415         struct tcphdr *th;
1416         int ret;
1417
1418         ret = skb_cow_head(skb, 0);
1419         if (ret)
1420                 return ret;
1421
1422         ipv6h = ipv6_hdr(skb);
1423         th = tcp_hdr(skb);
1424
1425         th->check = 0;
1426         th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
1427
1428         return ret;
1429 }
1430
1431 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
1432 {
1433         if (skb_vlan_tag_present(skb)) {
1434                 u32 opts2;
1435
1436                 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
1437                 desc->opts2 |= cpu_to_le32(opts2);
1438         }
1439 }
1440
1441 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
1442 {
1443         u32 opts2 = le32_to_cpu(desc->opts2);
1444
1445         if (opts2 & RX_VLAN_TAG)
1446                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1447                                        swab16(opts2 & 0xffff));
1448 }
1449
1450 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
1451                          struct sk_buff *skb, u32 len, u32 transport_offset)
1452 {
1453         u32 mss = skb_shinfo(skb)->gso_size;
1454         u32 opts1, opts2 = 0;
1455         int ret = TX_CSUM_SUCCESS;
1456
1457         WARN_ON_ONCE(len > TX_LEN_MAX);
1458
1459         opts1 = len | TX_FS | TX_LS;
1460
1461         if (mss) {
1462                 if (transport_offset > GTTCPHO_MAX) {
1463                         netif_warn(tp, tx_err, tp->netdev,
1464                                    "Invalid transport offset 0x%x for TSO\n",
1465                                    transport_offset);
1466                         ret = TX_CSUM_TSO;
1467                         goto unavailable;
1468                 }
1469
1470                 switch (vlan_get_protocol(skb)) {
1471                 case htons(ETH_P_IP):
1472                         opts1 |= GTSENDV4;
1473                         break;
1474
1475                 case htons(ETH_P_IPV6):
1476                         if (msdn_giant_send_check(skb)) {
1477                                 ret = TX_CSUM_TSO;
1478                                 goto unavailable;
1479                         }
1480                         opts1 |= GTSENDV6;
1481                         break;
1482
1483                 default:
1484                         WARN_ON_ONCE(1);
1485                         break;
1486                 }
1487
1488                 opts1 |= transport_offset << GTTCPHO_SHIFT;
1489                 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
1490         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1491                 u8 ip_protocol;
1492
1493                 if (transport_offset > TCPHO_MAX) {
1494                         netif_warn(tp, tx_err, tp->netdev,
1495                                    "Invalid transport offset 0x%x\n",
1496                                    transport_offset);
1497                         ret = TX_CSUM_NONE;
1498                         goto unavailable;
1499                 }
1500
1501                 switch (vlan_get_protocol(skb)) {
1502                 case htons(ETH_P_IP):
1503                         opts2 |= IPV4_CS;
1504                         ip_protocol = ip_hdr(skb)->protocol;
1505                         break;
1506
1507                 case htons(ETH_P_IPV6):
1508                         opts2 |= IPV6_CS;
1509                         ip_protocol = ipv6_hdr(skb)->nexthdr;
1510                         break;
1511
1512                 default:
1513                         ip_protocol = IPPROTO_RAW;
1514                         break;
1515                 }
1516
1517                 if (ip_protocol == IPPROTO_TCP)
1518                         opts2 |= TCP_CS;
1519                 else if (ip_protocol == IPPROTO_UDP)
1520                         opts2 |= UDP_CS;
1521                 else
1522                         WARN_ON_ONCE(1);
1523
1524                 opts2 |= transport_offset << TCPHO_SHIFT;
1525         }
1526
1527         desc->opts2 = cpu_to_le32(opts2);
1528         desc->opts1 = cpu_to_le32(opts1);
1529
1530 unavailable:
1531         return ret;
1532 }
1533
1534 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
1535 {
1536         struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
1537         int remain, ret;
1538         u8 *tx_data;
1539
1540         __skb_queue_head_init(&skb_head);
1541         spin_lock(&tx_queue->lock);
1542         skb_queue_splice_init(tx_queue, &skb_head);
1543         spin_unlock(&tx_queue->lock);
1544
1545         tx_data = agg->head;
1546         agg->skb_num = 0;
1547         agg->skb_len = 0;
1548         remain = agg_buf_sz;
1549
1550         while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
1551                 struct tx_desc *tx_desc;
1552                 struct sk_buff *skb;
1553                 unsigned int len;
1554                 u32 offset;
1555
1556                 skb = __skb_dequeue(&skb_head);
1557                 if (!skb)
1558                         break;
1559
1560                 len = skb->len + sizeof(*tx_desc);
1561
1562                 if (len > remain) {
1563                         __skb_queue_head(&skb_head, skb);
1564                         break;
1565                 }
1566
1567                 tx_data = tx_agg_align(tx_data);
1568                 tx_desc = (struct tx_desc *)tx_data;
1569
1570                 offset = (u32)skb_transport_offset(skb);
1571
1572                 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
1573                         r8152_csum_workaround(tp, skb, &skb_head);
1574                         continue;
1575                 }
1576
1577                 rtl_tx_vlan_tag(tx_desc, skb);
1578
1579                 tx_data += sizeof(*tx_desc);
1580
1581                 len = skb->len;
1582                 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
1583                         struct net_device_stats *stats = &tp->netdev->stats;
1584
1585                         stats->tx_dropped++;
1586                         dev_kfree_skb_any(skb);
1587                         tx_data -= sizeof(*tx_desc);
1588                         continue;
1589                 }
1590
1591                 tx_data += len;
1592                 agg->skb_len += len;
1593                 agg->skb_num++;
1594
1595                 dev_kfree_skb_any(skb);
1596
1597                 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
1598         }
1599
1600         if (!skb_queue_empty(&skb_head)) {
1601                 spin_lock(&tx_queue->lock);
1602                 skb_queue_splice(&skb_head, tx_queue);
1603                 spin_unlock(&tx_queue->lock);
1604         }
1605
1606         netif_tx_lock(tp->netdev);
1607
1608         if (netif_queue_stopped(tp->netdev) &&
1609             skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
1610                 netif_wake_queue(tp->netdev);
1611
1612         netif_tx_unlock(tp->netdev);
1613
1614         ret = usb_autopm_get_interface_async(tp->intf);
1615         if (ret < 0)
1616                 goto out_tx_fill;
1617
1618         usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
1619                           agg->head, (int)(tx_data - (u8 *)agg->head),
1620                           (usb_complete_t)write_bulk_callback, agg);
1621
1622         ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
1623         if (ret < 0)
1624                 usb_autopm_put_interface_async(tp->intf);
1625
1626 out_tx_fill:
1627         return ret;
1628 }
1629
1630 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
1631 {
1632         u8 checksum = CHECKSUM_NONE;
1633         u32 opts2, opts3;
1634
1635         if (tp->version == RTL_VER_01)
1636                 goto return_result;
1637
1638         opts2 = le32_to_cpu(rx_desc->opts2);
1639         opts3 = le32_to_cpu(rx_desc->opts3);
1640
1641         if (opts2 & RD_IPV4_CS) {
1642                 if (opts3 & IPF)
1643                         checksum = CHECKSUM_NONE;
1644                 else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF))
1645                         checksum = CHECKSUM_NONE;
1646                 else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF))
1647                         checksum = CHECKSUM_NONE;
1648                 else
1649                         checksum = CHECKSUM_UNNECESSARY;
1650         } else if (RD_IPV6_CS) {
1651                 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
1652                         checksum = CHECKSUM_UNNECESSARY;
1653                 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
1654                         checksum = CHECKSUM_UNNECESSARY;
1655         }
1656
1657 return_result:
1658         return checksum;
1659 }
1660
1661 static int rx_bottom(struct r8152 *tp, int budget)
1662 {
1663         unsigned long flags;
1664         struct list_head *cursor, *next, rx_queue;
1665         int ret = 0, work_done = 0;
1666
1667         if (!skb_queue_empty(&tp->rx_queue)) {
1668                 while (work_done < budget) {
1669                         struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
1670                         struct net_device *netdev = tp->netdev;
1671                         struct net_device_stats *stats = &netdev->stats;
1672                         unsigned int pkt_len;
1673
1674                         if (!skb)
1675                                 break;
1676
1677                         pkt_len = skb->len;
1678                         napi_gro_receive(&tp->napi, skb);
1679                         work_done++;
1680                         stats->rx_packets++;
1681                         stats->rx_bytes += pkt_len;
1682                 }
1683         }
1684
1685         if (list_empty(&tp->rx_done))
1686                 goto out1;
1687
1688         INIT_LIST_HEAD(&rx_queue);
1689         spin_lock_irqsave(&tp->rx_lock, flags);
1690         list_splice_init(&tp->rx_done, &rx_queue);
1691         spin_unlock_irqrestore(&tp->rx_lock, flags);
1692
1693         list_for_each_safe(cursor, next, &rx_queue) {
1694                 struct rx_desc *rx_desc;
1695                 struct rx_agg *agg;
1696                 int len_used = 0;
1697                 struct urb *urb;
1698                 u8 *rx_data;
1699
1700                 list_del_init(cursor);
1701
1702                 agg = list_entry(cursor, struct rx_agg, list);
1703                 urb = agg->urb;
1704                 if (urb->actual_length < ETH_ZLEN)
1705                         goto submit;
1706
1707                 rx_desc = agg->head;
1708                 rx_data = agg->head;
1709                 len_used += sizeof(struct rx_desc);
1710
1711                 while (urb->actual_length > len_used) {
1712                         struct net_device *netdev = tp->netdev;
1713                         struct net_device_stats *stats = &netdev->stats;
1714                         unsigned int pkt_len;
1715                         struct sk_buff *skb;
1716
1717                         pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
1718                         if (pkt_len < ETH_ZLEN)
1719                                 break;
1720
1721                         len_used += pkt_len;
1722                         if (urb->actual_length < len_used)
1723                                 break;
1724
1725                         pkt_len -= CRC_SIZE;
1726                         rx_data += sizeof(struct rx_desc);
1727
1728                         skb = netdev_alloc_skb_ip_align(netdev, pkt_len);
1729                         if (!skb) {
1730                                 stats->rx_dropped++;
1731                                 goto find_next_rx;
1732                         }
1733
1734                         skb->ip_summed = r8152_rx_csum(tp, rx_desc);
1735                         memcpy(skb->data, rx_data, pkt_len);
1736                         skb_put(skb, pkt_len);
1737                         skb->protocol = eth_type_trans(skb, netdev);
1738                         rtl_rx_vlan_tag(rx_desc, skb);
1739                         if (work_done < budget) {
1740                                 napi_gro_receive(&tp->napi, skb);
1741                                 work_done++;
1742                                 stats->rx_packets++;
1743                                 stats->rx_bytes += pkt_len;
1744                         } else {
1745                                 __skb_queue_tail(&tp->rx_queue, skb);
1746                         }
1747
1748 find_next_rx:
1749                         rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE);
1750                         rx_desc = (struct rx_desc *)rx_data;
1751                         len_used = (int)(rx_data - (u8 *)agg->head);
1752                         len_used += sizeof(struct rx_desc);
1753                 }
1754
1755 submit:
1756                 if (!ret) {
1757                         ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
1758                 } else {
1759                         urb->actual_length = 0;
1760                         list_add_tail(&agg->list, next);
1761                 }
1762         }
1763
1764         if (!list_empty(&rx_queue)) {
1765                 spin_lock_irqsave(&tp->rx_lock, flags);
1766                 list_splice_tail(&rx_queue, &tp->rx_done);
1767                 spin_unlock_irqrestore(&tp->rx_lock, flags);
1768         }
1769
1770 out1:
1771         return work_done;
1772 }
1773
1774 static void tx_bottom(struct r8152 *tp)
1775 {
1776         int res;
1777
1778         do {
1779                 struct tx_agg *agg;
1780
1781                 if (skb_queue_empty(&tp->tx_queue))
1782                         break;
1783
1784                 agg = r8152_get_tx_agg(tp);
1785                 if (!agg)
1786                         break;
1787
1788                 res = r8152_tx_agg_fill(tp, agg);
1789                 if (res) {
1790                         struct net_device *netdev = tp->netdev;
1791
1792                         if (res == -ENODEV) {
1793                                 set_bit(RTL8152_UNPLUG, &tp->flags);
1794                                 netif_device_detach(netdev);
1795                         } else {
1796                                 struct net_device_stats *stats = &netdev->stats;
1797                                 unsigned long flags;
1798
1799                                 netif_warn(tp, tx_err, netdev,
1800                                            "failed tx_urb %d\n", res);
1801                                 stats->tx_dropped += agg->skb_num;
1802
1803                                 spin_lock_irqsave(&tp->tx_lock, flags);
1804                                 list_add_tail(&agg->list, &tp->tx_free);
1805                                 spin_unlock_irqrestore(&tp->tx_lock, flags);
1806                         }
1807                 }
1808         } while (res == 0);
1809 }
1810
1811 static void bottom_half(struct r8152 *tp)
1812 {
1813         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1814                 return;
1815
1816         if (!test_bit(WORK_ENABLE, &tp->flags))
1817                 return;
1818
1819         /* When link down, the driver would cancel all bulks. */
1820         /* This avoid the re-submitting bulk */
1821         if (!netif_carrier_ok(tp->netdev))
1822                 return;
1823
1824         clear_bit(SCHEDULE_NAPI, &tp->flags);
1825
1826         tx_bottom(tp);
1827 }
1828
1829 static int r8152_poll(struct napi_struct *napi, int budget)
1830 {
1831         struct r8152 *tp = container_of(napi, struct r8152, napi);
1832         int work_done;
1833
1834         work_done = rx_bottom(tp, budget);
1835         bottom_half(tp);
1836
1837         if (work_done < budget) {
1838                 napi_complete(napi);
1839                 if (!list_empty(&tp->rx_done))
1840                         napi_schedule(napi);
1841         }
1842
1843         return work_done;
1844 }
1845
1846 static
1847 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
1848 {
1849         int ret;
1850
1851         /* The rx would be stopped, so skip submitting */
1852         if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
1853             !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
1854                 return 0;
1855
1856         usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
1857                           agg->head, agg_buf_sz,
1858                           (usb_complete_t)read_bulk_callback, agg);
1859
1860         ret = usb_submit_urb(agg->urb, mem_flags);
1861         if (ret == -ENODEV) {
1862                 set_bit(RTL8152_UNPLUG, &tp->flags);
1863                 netif_device_detach(tp->netdev);
1864         } else if (ret) {
1865                 struct urb *urb = agg->urb;
1866                 unsigned long flags;
1867
1868                 urb->actual_length = 0;
1869                 spin_lock_irqsave(&tp->rx_lock, flags);
1870                 list_add_tail(&agg->list, &tp->rx_done);
1871                 spin_unlock_irqrestore(&tp->rx_lock, flags);
1872
1873                 netif_err(tp, rx_err, tp->netdev,
1874                           "Couldn't submit rx[%p], ret = %d\n", agg, ret);
1875
1876                 napi_schedule(&tp->napi);
1877         }
1878
1879         return ret;
1880 }
1881
1882 static void rtl_drop_queued_tx(struct r8152 *tp)
1883 {
1884         struct net_device_stats *stats = &tp->netdev->stats;
1885         struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
1886         struct sk_buff *skb;
1887
1888         if (skb_queue_empty(tx_queue))
1889                 return;
1890
1891         __skb_queue_head_init(&skb_head);
1892         spin_lock_bh(&tx_queue->lock);
1893         skb_queue_splice_init(tx_queue, &skb_head);
1894         spin_unlock_bh(&tx_queue->lock);
1895
1896         while ((skb = __skb_dequeue(&skb_head))) {
1897                 dev_kfree_skb(skb);
1898                 stats->tx_dropped++;
1899         }
1900 }
1901
1902 static void rtl8152_tx_timeout(struct net_device *netdev)
1903 {
1904         struct r8152 *tp = netdev_priv(netdev);
1905         int i;
1906
1907         netif_warn(tp, tx_err, netdev, "Tx timeout\n");
1908         for (i = 0; i < RTL8152_MAX_TX; i++)
1909                 usb_unlink_urb(tp->tx_info[i].urb);
1910 }
1911
1912 static void rtl8152_set_rx_mode(struct net_device *netdev)
1913 {
1914         struct r8152 *tp = netdev_priv(netdev);
1915
1916         if (netif_carrier_ok(netdev)) {
1917                 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
1918                 schedule_delayed_work(&tp->schedule, 0);
1919         }
1920 }
1921
1922 static void _rtl8152_set_rx_mode(struct net_device *netdev)
1923 {
1924         struct r8152 *tp = netdev_priv(netdev);
1925         u32 mc_filter[2];       /* Multicast hash filter */
1926         __le32 tmp[2];
1927         u32 ocp_data;
1928
1929         clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
1930         netif_stop_queue(netdev);
1931         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1932         ocp_data &= ~RCR_ACPT_ALL;
1933         ocp_data |= RCR_AB | RCR_APM;
1934
1935         if (netdev->flags & IFF_PROMISC) {
1936                 /* Unconditionally log net taps. */
1937                 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
1938                 ocp_data |= RCR_AM | RCR_AAP;
1939                 mc_filter[1] = 0xffffffff;
1940                 mc_filter[0] = 0xffffffff;
1941         } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
1942                    (netdev->flags & IFF_ALLMULTI)) {
1943                 /* Too many to filter perfectly -- accept all multicasts. */
1944                 ocp_data |= RCR_AM;
1945                 mc_filter[1] = 0xffffffff;
1946                 mc_filter[0] = 0xffffffff;
1947         } else {
1948                 struct netdev_hw_addr *ha;
1949
1950                 mc_filter[1] = 0;
1951                 mc_filter[0] = 0;
1952                 netdev_for_each_mc_addr(ha, netdev) {
1953                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1954
1955                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1956                         ocp_data |= RCR_AM;
1957                 }
1958         }
1959
1960         tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
1961         tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
1962
1963         pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
1964         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1965         netif_wake_queue(netdev);
1966 }
1967
1968 static netdev_features_t
1969 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
1970                        netdev_features_t features)
1971 {
1972         u32 mss = skb_shinfo(skb)->gso_size;
1973         int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
1974         int offset = skb_transport_offset(skb);
1975
1976         if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
1977                 features &= ~(NETIF_F_ALL_CSUM | NETIF_F_GSO_MASK);
1978         else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
1979                 features &= ~NETIF_F_GSO_MASK;
1980
1981         return features;
1982 }
1983
1984 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
1985                                       struct net_device *netdev)
1986 {
1987         struct r8152 *tp = netdev_priv(netdev);
1988
1989         skb_tx_timestamp(skb);
1990
1991         skb_queue_tail(&tp->tx_queue, skb);
1992
1993         if (!list_empty(&tp->tx_free)) {
1994                 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
1995                         set_bit(SCHEDULE_NAPI, &tp->flags);
1996                         schedule_delayed_work(&tp->schedule, 0);
1997                 } else {
1998                         usb_mark_last_busy(tp->udev);
1999                         napi_schedule(&tp->napi);
2000                 }
2001         } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
2002                 netif_stop_queue(netdev);
2003         }
2004
2005         return NETDEV_TX_OK;
2006 }
2007
2008 static void r8152b_reset_packet_filter(struct r8152 *tp)
2009 {
2010         u32     ocp_data;
2011
2012         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
2013         ocp_data &= ~FMC_FCR_MCU_EN;
2014         ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2015         ocp_data |= FMC_FCR_MCU_EN;
2016         ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2017 }
2018
2019 static void rtl8152_nic_reset(struct r8152 *tp)
2020 {
2021         int     i;
2022
2023         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
2024
2025         for (i = 0; i < 1000; i++) {
2026                 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
2027                         break;
2028                 usleep_range(100, 400);
2029         }
2030 }
2031
2032 static void set_tx_qlen(struct r8152 *tp)
2033 {
2034         struct net_device *netdev = tp->netdev;
2035
2036         tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN +
2037                                     sizeof(struct tx_desc));
2038 }
2039
2040 static inline u8 rtl8152_get_speed(struct r8152 *tp)
2041 {
2042         return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
2043 }
2044
2045 static void rtl_set_eee_plus(struct r8152 *tp)
2046 {
2047         u32 ocp_data;
2048         u8 speed;
2049
2050         speed = rtl8152_get_speed(tp);
2051         if (speed & _10bps) {
2052                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2053                 ocp_data |= EEEP_CR_EEEP_TX;
2054                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2055         } else {
2056                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2057                 ocp_data &= ~EEEP_CR_EEEP_TX;
2058                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2059         }
2060 }
2061
2062 static void rxdy_gated_en(struct r8152 *tp, bool enable)
2063 {
2064         u32 ocp_data;
2065
2066         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
2067         if (enable)
2068                 ocp_data |= RXDY_GATED_EN;
2069         else
2070                 ocp_data &= ~RXDY_GATED_EN;
2071         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
2072 }
2073
2074 static int rtl_start_rx(struct r8152 *tp)
2075 {
2076         int i, ret = 0;
2077
2078         napi_disable(&tp->napi);
2079         INIT_LIST_HEAD(&tp->rx_done);
2080         for (i = 0; i < RTL8152_MAX_RX; i++) {
2081                 INIT_LIST_HEAD(&tp->rx_info[i].list);
2082                 ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
2083                 if (ret)
2084                         break;
2085         }
2086         napi_enable(&tp->napi);
2087
2088         if (ret && ++i < RTL8152_MAX_RX) {
2089                 struct list_head rx_queue;
2090                 unsigned long flags;
2091
2092                 INIT_LIST_HEAD(&rx_queue);
2093
2094                 do {
2095                         struct rx_agg *agg = &tp->rx_info[i++];
2096                         struct urb *urb = agg->urb;
2097
2098                         urb->actual_length = 0;
2099                         list_add_tail(&agg->list, &rx_queue);
2100                 } while (i < RTL8152_MAX_RX);
2101
2102                 spin_lock_irqsave(&tp->rx_lock, flags);
2103                 list_splice_tail(&rx_queue, &tp->rx_done);
2104                 spin_unlock_irqrestore(&tp->rx_lock, flags);
2105         }
2106
2107         return ret;
2108 }
2109
2110 static int rtl_stop_rx(struct r8152 *tp)
2111 {
2112         int i;
2113
2114         for (i = 0; i < RTL8152_MAX_RX; i++)
2115                 usb_kill_urb(tp->rx_info[i].urb);
2116
2117         while (!skb_queue_empty(&tp->rx_queue))
2118                 dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
2119
2120         return 0;
2121 }
2122
2123 static int rtl_enable(struct r8152 *tp)
2124 {
2125         u32 ocp_data;
2126
2127         r8152b_reset_packet_filter(tp);
2128
2129         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2130         ocp_data |= CR_RE | CR_TE;
2131         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2132
2133         rxdy_gated_en(tp, false);
2134
2135         return 0;
2136 }
2137
2138 static int rtl8152_enable(struct r8152 *tp)
2139 {
2140         if (test_bit(RTL8152_UNPLUG, &tp->flags))
2141                 return -ENODEV;
2142
2143         set_tx_qlen(tp);
2144         rtl_set_eee_plus(tp);
2145
2146         return rtl_enable(tp);
2147 }
2148
2149 static void r8153_set_rx_early_timeout(struct r8152 *tp)
2150 {
2151         u32 ocp_data = tp->coalesce / 8;
2152
2153         ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, ocp_data);
2154 }
2155
2156 static void r8153_set_rx_early_size(struct r8152 *tp)
2157 {
2158         u32 mtu = tp->netdev->mtu;
2159         u32 ocp_data = (agg_buf_sz - mtu - VLAN_ETH_HLEN - VLAN_HLEN) / 4;
2160
2161         ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, ocp_data);
2162 }
2163
2164 static int rtl8153_enable(struct r8152 *tp)
2165 {
2166         if (test_bit(RTL8152_UNPLUG, &tp->flags))
2167                 return -ENODEV;
2168
2169         set_tx_qlen(tp);
2170         rtl_set_eee_plus(tp);
2171         r8153_set_rx_early_timeout(tp);
2172         r8153_set_rx_early_size(tp);
2173
2174         return rtl_enable(tp);
2175 }
2176
2177 static void rtl_disable(struct r8152 *tp)
2178 {
2179         u32 ocp_data;
2180         int i;
2181
2182         if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2183                 rtl_drop_queued_tx(tp);
2184                 return;
2185         }
2186
2187         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2188         ocp_data &= ~RCR_ACPT_ALL;
2189         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2190
2191         rtl_drop_queued_tx(tp);
2192
2193         for (i = 0; i < RTL8152_MAX_TX; i++)
2194                 usb_kill_urb(tp->tx_info[i].urb);
2195
2196         rxdy_gated_en(tp, true);
2197
2198         for (i = 0; i < 1000; i++) {
2199                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2200                 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
2201                         break;
2202                 usleep_range(1000, 2000);
2203         }
2204
2205         for (i = 0; i < 1000; i++) {
2206                 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
2207                         break;
2208                 usleep_range(1000, 2000);
2209         }
2210
2211         rtl_stop_rx(tp);
2212
2213         rtl8152_nic_reset(tp);
2214 }
2215
2216 static void r8152_power_cut_en(struct r8152 *tp, bool enable)
2217 {
2218         u32 ocp_data;
2219
2220         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2221         if (enable)
2222                 ocp_data |= POWER_CUT;
2223         else
2224                 ocp_data &= ~POWER_CUT;
2225         ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2226
2227         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2228         ocp_data &= ~RESUME_INDICATE;
2229         ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
2230 }
2231
2232 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
2233 {
2234         u32 ocp_data;
2235
2236         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2237         if (enable)
2238                 ocp_data |= CPCR_RX_VLAN;
2239         else
2240                 ocp_data &= ~CPCR_RX_VLAN;
2241         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2242 }
2243
2244 static int rtl8152_set_features(struct net_device *dev,
2245                                 netdev_features_t features)
2246 {
2247         netdev_features_t changed = features ^ dev->features;
2248         struct r8152 *tp = netdev_priv(dev);
2249         int ret;
2250
2251         ret = usb_autopm_get_interface(tp->intf);
2252         if (ret < 0)
2253                 goto out;
2254
2255         mutex_lock(&tp->control);
2256
2257         if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
2258                 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2259                         rtl_rx_vlan_en(tp, true);
2260                 else
2261                         rtl_rx_vlan_en(tp, false);
2262         }
2263
2264         mutex_unlock(&tp->control);
2265
2266         usb_autopm_put_interface(tp->intf);
2267
2268 out:
2269         return ret;
2270 }
2271
2272 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
2273
2274 static u32 __rtl_get_wol(struct r8152 *tp)
2275 {
2276         u32 ocp_data;
2277         u32 wolopts = 0;
2278
2279         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2280         if (!(ocp_data & LAN_WAKE_EN))
2281                 return 0;
2282
2283         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2284         if (ocp_data & LINK_ON_WAKE_EN)
2285                 wolopts |= WAKE_PHY;
2286
2287         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2288         if (ocp_data & UWF_EN)
2289                 wolopts |= WAKE_UCAST;
2290         if (ocp_data & BWF_EN)
2291                 wolopts |= WAKE_BCAST;
2292         if (ocp_data & MWF_EN)
2293                 wolopts |= WAKE_MCAST;
2294
2295         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2296         if (ocp_data & MAGIC_EN)
2297                 wolopts |= WAKE_MAGIC;
2298
2299         return wolopts;
2300 }
2301
2302 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
2303 {
2304         u32 ocp_data;
2305
2306         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2307
2308         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2309         ocp_data &= ~LINK_ON_WAKE_EN;
2310         if (wolopts & WAKE_PHY)
2311                 ocp_data |= LINK_ON_WAKE_EN;
2312         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2313
2314         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2315         ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN | LAN_WAKE_EN);
2316         if (wolopts & WAKE_UCAST)
2317                 ocp_data |= UWF_EN;
2318         if (wolopts & WAKE_BCAST)
2319                 ocp_data |= BWF_EN;
2320         if (wolopts & WAKE_MCAST)
2321                 ocp_data |= MWF_EN;
2322         if (wolopts & WAKE_ANY)
2323                 ocp_data |= LAN_WAKE_EN;
2324         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
2325
2326         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2327
2328         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2329         ocp_data &= ~MAGIC_EN;
2330         if (wolopts & WAKE_MAGIC)
2331                 ocp_data |= MAGIC_EN;
2332         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
2333
2334         if (wolopts & WAKE_ANY)
2335                 device_set_wakeup_enable(&tp->udev->dev, true);
2336         else
2337                 device_set_wakeup_enable(&tp->udev->dev, false);
2338 }
2339
2340 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
2341 {
2342         if (enable) {
2343                 u32 ocp_data;
2344
2345                 __rtl_set_wol(tp, WAKE_ANY);
2346
2347                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2348
2349                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2350                 ocp_data |= LINK_OFF_WAKE_EN;
2351                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2352
2353                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2354         } else {
2355                 __rtl_set_wol(tp, tp->saved_wolopts);
2356         }
2357 }
2358
2359 static void rtl_phy_reset(struct r8152 *tp)
2360 {
2361         u16 data;
2362         int i;
2363
2364         clear_bit(PHY_RESET, &tp->flags);
2365
2366         data = r8152_mdio_read(tp, MII_BMCR);
2367
2368         /* don't reset again before the previous one complete */
2369         if (data & BMCR_RESET)
2370                 return;
2371
2372         data |= BMCR_RESET;
2373         r8152_mdio_write(tp, MII_BMCR, data);
2374
2375         for (i = 0; i < 50; i++) {
2376                 msleep(20);
2377                 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
2378                         break;
2379         }
2380 }
2381
2382 static void r8153_teredo_off(struct r8152 *tp)
2383 {
2384         u32 ocp_data;
2385
2386         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2387         ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN);
2388         ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2389
2390         ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
2391         ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
2392         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
2393 }
2394
2395 static void r8152b_disable_aldps(struct r8152 *tp)
2396 {
2397         ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE);
2398         msleep(20);
2399 }
2400
2401 static inline void r8152b_enable_aldps(struct r8152 *tp)
2402 {
2403         ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
2404                                             LINKENA | DIS_SDSAVE);
2405 }
2406
2407 static void rtl8152_disable(struct r8152 *tp)
2408 {
2409         r8152b_disable_aldps(tp);
2410         rtl_disable(tp);
2411         r8152b_enable_aldps(tp);
2412 }
2413
2414 static void r8152b_hw_phy_cfg(struct r8152 *tp)
2415 {
2416         u16 data;
2417
2418         data = r8152_mdio_read(tp, MII_BMCR);
2419         if (data & BMCR_PDOWN) {
2420                 data &= ~BMCR_PDOWN;
2421                 r8152_mdio_write(tp, MII_BMCR, data);
2422         }
2423
2424         set_bit(PHY_RESET, &tp->flags);
2425 }
2426
2427 static void r8152b_exit_oob(struct r8152 *tp)
2428 {
2429         u32 ocp_data;
2430         int i;
2431
2432         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2433         ocp_data &= ~RCR_ACPT_ALL;
2434         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2435
2436         rxdy_gated_en(tp, true);
2437         r8153_teredo_off(tp);
2438         r8152b_hw_phy_cfg(tp);
2439
2440         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2441         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
2442
2443         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2444         ocp_data &= ~NOW_IS_OOB;
2445         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2446
2447         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2448         ocp_data &= ~MCU_BORW_EN;
2449         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2450
2451         for (i = 0; i < 1000; i++) {
2452                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2453                 if (ocp_data & LINK_LIST_READY)
2454                         break;
2455                 usleep_range(1000, 2000);
2456         }
2457
2458         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2459         ocp_data |= RE_INIT_LL;
2460         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2461
2462         for (i = 0; i < 1000; i++) {
2463                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2464                 if (ocp_data & LINK_LIST_READY)
2465                         break;
2466                 usleep_range(1000, 2000);
2467         }
2468
2469         rtl8152_nic_reset(tp);
2470
2471         /* rx share fifo credit full threshold */
2472         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2473
2474         if (tp->udev->speed == USB_SPEED_FULL ||
2475             tp->udev->speed == USB_SPEED_LOW) {
2476                 /* rx share fifo credit near full threshold */
2477                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2478                                 RXFIFO_THR2_FULL);
2479                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2480                                 RXFIFO_THR3_FULL);
2481         } else {
2482                 /* rx share fifo credit near full threshold */
2483                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2484                                 RXFIFO_THR2_HIGH);
2485                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2486                                 RXFIFO_THR3_HIGH);
2487         }
2488
2489         /* TX share fifo free credit full threshold */
2490         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
2491
2492         ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
2493         ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
2494         ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
2495                         TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
2496
2497         rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
2498
2499         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2500
2501         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2502         ocp_data |= TCR0_AUTO_FIFO;
2503         ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2504 }
2505
2506 static void r8152b_enter_oob(struct r8152 *tp)
2507 {
2508         u32 ocp_data;
2509         int i;
2510
2511         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2512         ocp_data &= ~NOW_IS_OOB;
2513         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2514
2515         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
2516         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
2517         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
2518
2519         rtl_disable(tp);
2520
2521         for (i = 0; i < 1000; i++) {
2522                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2523                 if (ocp_data & LINK_LIST_READY)
2524                         break;
2525                 usleep_range(1000, 2000);
2526         }
2527
2528         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2529         ocp_data |= RE_INIT_LL;
2530         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2531
2532         for (i = 0; i < 1000; i++) {
2533                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2534                 if (ocp_data & LINK_LIST_READY)
2535                         break;
2536                 usleep_range(1000, 2000);
2537         }
2538
2539         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2540
2541         rtl_rx_vlan_en(tp, true);
2542
2543         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2544         ocp_data |= ALDPS_PROXY_MODE;
2545         ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2546
2547         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2548         ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2549         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2550
2551         rxdy_gated_en(tp, false);
2552
2553         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2554         ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2555         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2556 }
2557
2558 static void r8153_hw_phy_cfg(struct r8152 *tp)
2559 {
2560         u32 ocp_data;
2561         u16 data;
2562
2563         ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
2564         data = r8152_mdio_read(tp, MII_BMCR);
2565         if (data & BMCR_PDOWN) {
2566                 data &= ~BMCR_PDOWN;
2567                 r8152_mdio_write(tp, MII_BMCR, data);
2568         }
2569
2570         if (tp->version == RTL_VER_03) {
2571                 data = ocp_reg_read(tp, OCP_EEE_CFG);
2572                 data &= ~CTAP_SHORT_EN;
2573                 ocp_reg_write(tp, OCP_EEE_CFG, data);
2574         }
2575
2576         data = ocp_reg_read(tp, OCP_POWER_CFG);
2577         data |= EEE_CLKDIV_EN;
2578         ocp_reg_write(tp, OCP_POWER_CFG, data);
2579
2580         data = ocp_reg_read(tp, OCP_DOWN_SPEED);
2581         data |= EN_10M_BGOFF;
2582         ocp_reg_write(tp, OCP_DOWN_SPEED, data);
2583         data = ocp_reg_read(tp, OCP_POWER_CFG);
2584         data |= EN_10M_PLLOFF;
2585         ocp_reg_write(tp, OCP_POWER_CFG, data);
2586         sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
2587
2588         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
2589         ocp_data |= PFM_PWM_SWITCH;
2590         ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
2591
2592         /* Enable LPF corner auto tune */
2593         sram_write(tp, SRAM_LPF_CFG, 0xf70f);
2594
2595         /* Adjust 10M Amplitude */
2596         sram_write(tp, SRAM_10M_AMP1, 0x00af);
2597         sram_write(tp, SRAM_10M_AMP2, 0x0208);
2598
2599         set_bit(PHY_RESET, &tp->flags);
2600 }
2601
2602 static void r8153_u1u2en(struct r8152 *tp, bool enable)
2603 {
2604         u8 u1u2[8];
2605
2606         if (enable)
2607                 memset(u1u2, 0xff, sizeof(u1u2));
2608         else
2609                 memset(u1u2, 0x00, sizeof(u1u2));
2610
2611         usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
2612 }
2613
2614 static void r8153_u2p3en(struct r8152 *tp, bool enable)
2615 {
2616         u32 ocp_data;
2617
2618         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
2619         if (enable)
2620                 ocp_data |= U2P3_ENABLE;
2621         else
2622                 ocp_data &= ~U2P3_ENABLE;
2623         ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
2624 }
2625
2626 static void r8153_power_cut_en(struct r8152 *tp, bool enable)
2627 {
2628         u32 ocp_data;
2629
2630         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2631         if (enable)
2632                 ocp_data |= PWR_EN | PHASE2_EN;
2633         else
2634                 ocp_data &= ~(PWR_EN | PHASE2_EN);
2635         ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2636
2637         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2638         ocp_data &= ~PCUT_STATUS;
2639         ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2640 }
2641
2642 static void r8153_first_init(struct r8152 *tp)
2643 {
2644         u32 ocp_data;
2645         int i;
2646
2647         rxdy_gated_en(tp, true);
2648         r8153_teredo_off(tp);
2649
2650         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2651         ocp_data &= ~RCR_ACPT_ALL;
2652         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2653
2654         r8153_hw_phy_cfg(tp);
2655
2656         rtl8152_nic_reset(tp);
2657
2658         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2659         ocp_data &= ~NOW_IS_OOB;
2660         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2661
2662         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2663         ocp_data &= ~MCU_BORW_EN;
2664         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2665
2666         for (i = 0; i < 1000; i++) {
2667                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2668                 if (ocp_data & LINK_LIST_READY)
2669                         break;
2670                 usleep_range(1000, 2000);
2671         }
2672
2673         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2674         ocp_data |= RE_INIT_LL;
2675         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2676
2677         for (i = 0; i < 1000; i++) {
2678                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2679                 if (ocp_data & LINK_LIST_READY)
2680                         break;
2681                 usleep_range(1000, 2000);
2682         }
2683
2684         rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
2685
2686         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
2687         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
2688
2689         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2690         ocp_data |= TCR0_AUTO_FIFO;
2691         ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2692
2693         rtl8152_nic_reset(tp);
2694
2695         /* rx share fifo credit full threshold */
2696         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2697         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
2698         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
2699         /* TX share fifo free credit full threshold */
2700         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
2701
2702         /* rx aggregation */
2703         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2704         ocp_data &= ~RX_AGG_DISABLE;
2705         ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2706 }
2707
2708 static void r8153_enter_oob(struct r8152 *tp)
2709 {
2710         u32 ocp_data;
2711         int i;
2712
2713         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2714         ocp_data &= ~NOW_IS_OOB;
2715         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2716
2717         rtl_disable(tp);
2718
2719         for (i = 0; i < 1000; i++) {
2720                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2721                 if (ocp_data & LINK_LIST_READY)
2722                         break;
2723                 usleep_range(1000, 2000);
2724         }
2725
2726         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2727         ocp_data |= RE_INIT_LL;
2728         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2729
2730         for (i = 0; i < 1000; i++) {
2731                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2732                 if (ocp_data & LINK_LIST_READY)
2733                         break;
2734                 usleep_range(1000, 2000);
2735         }
2736
2737         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
2738
2739         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2740         ocp_data &= ~TEREDO_WAKE_MASK;
2741         ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2742
2743         rtl_rx_vlan_en(tp, true);
2744
2745         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2746         ocp_data |= ALDPS_PROXY_MODE;
2747         ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2748
2749         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2750         ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2751         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2752
2753         rxdy_gated_en(tp, false);
2754
2755         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2756         ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2757         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2758 }
2759
2760 static void r8153_disable_aldps(struct r8152 *tp)
2761 {
2762         u16 data;
2763
2764         data = ocp_reg_read(tp, OCP_POWER_CFG);
2765         data &= ~EN_ALDPS;
2766         ocp_reg_write(tp, OCP_POWER_CFG, data);
2767         msleep(20);
2768 }
2769
2770 static void r8153_enable_aldps(struct r8152 *tp)
2771 {
2772         u16 data;
2773
2774         data = ocp_reg_read(tp, OCP_POWER_CFG);
2775         data |= EN_ALDPS;
2776         ocp_reg_write(tp, OCP_POWER_CFG, data);
2777 }
2778
2779 static void rtl8153_disable(struct r8152 *tp)
2780 {
2781         r8153_disable_aldps(tp);
2782         rtl_disable(tp);
2783         r8153_enable_aldps(tp);
2784 }
2785
2786 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
2787 {
2788         u16 bmcr, anar, gbcr;
2789         int ret = 0;
2790
2791         cancel_delayed_work_sync(&tp->schedule);
2792         anar = r8152_mdio_read(tp, MII_ADVERTISE);
2793         anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
2794                   ADVERTISE_100HALF | ADVERTISE_100FULL);
2795         if (tp->mii.supports_gmii) {
2796                 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
2797                 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
2798         } else {
2799                 gbcr = 0;
2800         }
2801
2802         if (autoneg == AUTONEG_DISABLE) {
2803                 if (speed == SPEED_10) {
2804                         bmcr = 0;
2805                         anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2806                 } else if (speed == SPEED_100) {
2807                         bmcr = BMCR_SPEED100;
2808                         anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2809                 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2810                         bmcr = BMCR_SPEED1000;
2811                         gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
2812                 } else {
2813                         ret = -EINVAL;
2814                         goto out;
2815                 }
2816
2817                 if (duplex == DUPLEX_FULL)
2818                         bmcr |= BMCR_FULLDPLX;
2819         } else {
2820                 if (speed == SPEED_10) {
2821                         if (duplex == DUPLEX_FULL)
2822                                 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2823                         else
2824                                 anar |= ADVERTISE_10HALF;
2825                 } else if (speed == SPEED_100) {
2826                         if (duplex == DUPLEX_FULL) {
2827                                 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2828                                 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2829                         } else {
2830                                 anar |= ADVERTISE_10HALF;
2831                                 anar |= ADVERTISE_100HALF;
2832                         }
2833                 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2834                         if (duplex == DUPLEX_FULL) {
2835                                 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2836                                 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2837                                 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
2838                         } else {
2839                                 anar |= ADVERTISE_10HALF;
2840                                 anar |= ADVERTISE_100HALF;
2841                                 gbcr |= ADVERTISE_1000HALF;
2842                         }
2843                 } else {
2844                         ret = -EINVAL;
2845                         goto out;
2846                 }
2847
2848                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
2849         }
2850
2851         if (test_bit(PHY_RESET, &tp->flags))
2852                 bmcr |= BMCR_RESET;
2853
2854         if (tp->mii.supports_gmii)
2855                 r8152_mdio_write(tp, MII_CTRL1000, gbcr);
2856
2857         r8152_mdio_write(tp, MII_ADVERTISE, anar);
2858         r8152_mdio_write(tp, MII_BMCR, bmcr);
2859
2860         if (test_bit(PHY_RESET, &tp->flags)) {
2861                 int i;
2862
2863                 clear_bit(PHY_RESET, &tp->flags);
2864                 for (i = 0; i < 50; i++) {
2865                         msleep(20);
2866                         if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
2867                                 break;
2868                 }
2869         }
2870
2871 out:
2872
2873         return ret;
2874 }
2875
2876 static void rtl8152_up(struct r8152 *tp)
2877 {
2878         if (test_bit(RTL8152_UNPLUG, &tp->flags))
2879                 return;
2880
2881         r8152b_disable_aldps(tp);
2882         r8152b_exit_oob(tp);
2883         r8152b_enable_aldps(tp);
2884 }
2885
2886 static void rtl8152_down(struct r8152 *tp)
2887 {
2888         if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2889                 rtl_drop_queued_tx(tp);
2890                 return;
2891         }
2892
2893         r8152_power_cut_en(tp, false);
2894         r8152b_disable_aldps(tp);
2895         r8152b_enter_oob(tp);
2896         r8152b_enable_aldps(tp);
2897 }
2898
2899 static void rtl8153_up(struct r8152 *tp)
2900 {
2901         if (test_bit(RTL8152_UNPLUG, &tp->flags))
2902                 return;
2903
2904         r8153_disable_aldps(tp);
2905         r8153_first_init(tp);
2906         r8153_enable_aldps(tp);
2907 }
2908
2909 static void rtl8153_down(struct r8152 *tp)
2910 {
2911         if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2912                 rtl_drop_queued_tx(tp);
2913                 return;
2914         }
2915
2916         r8153_u1u2en(tp, false);
2917         r8153_power_cut_en(tp, false);
2918         r8153_disable_aldps(tp);
2919         r8153_enter_oob(tp);
2920         r8153_enable_aldps(tp);
2921 }
2922
2923 static void set_carrier(struct r8152 *tp)
2924 {
2925         struct net_device *netdev = tp->netdev;
2926         u8 speed;
2927
2928         clear_bit(RTL8152_LINK_CHG, &tp->flags);
2929         speed = rtl8152_get_speed(tp);
2930
2931         if (speed & LINK_STATUS) {
2932                 if (!netif_carrier_ok(netdev)) {
2933                         tp->rtl_ops.enable(tp);
2934                         set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2935                         netif_carrier_on(netdev);
2936                         rtl_start_rx(tp);
2937                 }
2938         } else {
2939                 if (netif_carrier_ok(netdev)) {
2940                         netif_carrier_off(netdev);
2941                         napi_disable(&tp->napi);
2942                         tp->rtl_ops.disable(tp);
2943                         napi_enable(&tp->napi);
2944                 }
2945         }
2946 }
2947
2948 static void rtl_work_func_t(struct work_struct *work)
2949 {
2950         struct r8152 *tp = container_of(work, struct r8152, schedule.work);
2951
2952         /* If the device is unplugged or !netif_running(), the workqueue
2953          * doesn't need to wake the device, and could return directly.
2954          */
2955         if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
2956                 return;
2957
2958         if (usb_autopm_get_interface(tp->intf) < 0)
2959                 return;
2960
2961         if (!test_bit(WORK_ENABLE, &tp->flags))
2962                 goto out1;
2963
2964         if (!mutex_trylock(&tp->control)) {
2965                 schedule_delayed_work(&tp->schedule, 0);
2966                 goto out1;
2967         }
2968
2969         if (test_bit(RTL8152_LINK_CHG, &tp->flags))
2970                 set_carrier(tp);
2971
2972         if (test_bit(RTL8152_SET_RX_MODE, &tp->flags))
2973                 _rtl8152_set_rx_mode(tp->netdev);
2974
2975         /* don't schedule napi before linking */
2976         if (test_bit(SCHEDULE_NAPI, &tp->flags) &&
2977             netif_carrier_ok(tp->netdev)) {
2978                 clear_bit(SCHEDULE_NAPI, &tp->flags);
2979                 napi_schedule(&tp->napi);
2980         }
2981
2982         if (test_bit(PHY_RESET, &tp->flags))
2983                 rtl_phy_reset(tp);
2984
2985         mutex_unlock(&tp->control);
2986
2987 out1:
2988         usb_autopm_put_interface(tp->intf);
2989 }
2990
2991 static int rtl8152_open(struct net_device *netdev)
2992 {
2993         struct r8152 *tp = netdev_priv(netdev);
2994         int res = 0;
2995
2996         res = alloc_all_mem(tp);
2997         if (res)
2998                 goto out;
2999
3000         netif_carrier_off(netdev);
3001
3002         res = usb_autopm_get_interface(tp->intf);
3003         if (res < 0) {
3004                 free_all_mem(tp);
3005                 goto out;
3006         }
3007
3008         mutex_lock(&tp->control);
3009
3010         /* The WORK_ENABLE may be set when autoresume occurs */
3011         if (test_bit(WORK_ENABLE, &tp->flags)) {
3012                 clear_bit(WORK_ENABLE, &tp->flags);
3013                 usb_kill_urb(tp->intr_urb);
3014                 cancel_delayed_work_sync(&tp->schedule);
3015
3016                 /* disable the tx/rx, if the workqueue has enabled them. */
3017                 if (netif_carrier_ok(netdev))
3018                         tp->rtl_ops.disable(tp);
3019         }
3020
3021         tp->rtl_ops.up(tp);
3022
3023         rtl8152_set_speed(tp, AUTONEG_ENABLE,
3024                           tp->mii.supports_gmii ? SPEED_1000 : SPEED_100,
3025                           DUPLEX_FULL);
3026         netif_carrier_off(netdev);
3027         netif_start_queue(netdev);
3028         set_bit(WORK_ENABLE, &tp->flags);
3029
3030         res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
3031         if (res) {
3032                 if (res == -ENODEV)
3033                         netif_device_detach(tp->netdev);
3034                 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
3035                            res);
3036                 free_all_mem(tp);
3037         } else {
3038                 napi_enable(&tp->napi);
3039         }
3040
3041         mutex_unlock(&tp->control);
3042
3043         usb_autopm_put_interface(tp->intf);
3044
3045 out:
3046         return res;
3047 }
3048
3049 static int rtl8152_close(struct net_device *netdev)
3050 {
3051         struct r8152 *tp = netdev_priv(netdev);
3052         int res = 0;
3053
3054         napi_disable(&tp->napi);
3055         clear_bit(WORK_ENABLE, &tp->flags);
3056         usb_kill_urb(tp->intr_urb);
3057         cancel_delayed_work_sync(&tp->schedule);
3058         netif_stop_queue(netdev);
3059
3060         res = usb_autopm_get_interface(tp->intf);
3061         if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
3062                 rtl_drop_queued_tx(tp);
3063                 rtl_stop_rx(tp);
3064         } else {
3065                 mutex_lock(&tp->control);
3066
3067                 /* The autosuspend may have been enabled and wouldn't
3068                  * be disable when autoresume occurs, because the
3069                  * netif_running() would be false.
3070                  */
3071                 rtl_runtime_suspend_enable(tp, false);
3072
3073                 tp->rtl_ops.down(tp);
3074
3075                 mutex_unlock(&tp->control);
3076
3077                 usb_autopm_put_interface(tp->intf);
3078         }
3079
3080         free_all_mem(tp);
3081
3082         return res;
3083 }
3084
3085 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
3086 {
3087         ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
3088         ocp_reg_write(tp, OCP_EEE_DATA, reg);
3089         ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
3090 }
3091
3092 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
3093 {
3094         u16 data;
3095
3096         r8152_mmd_indirect(tp, dev, reg);
3097         data = ocp_reg_read(tp, OCP_EEE_DATA);
3098         ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
3099
3100         return data;
3101 }
3102
3103 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
3104 {
3105         r8152_mmd_indirect(tp, dev, reg);
3106         ocp_reg_write(tp, OCP_EEE_DATA, data);
3107         ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
3108 }
3109
3110 static void r8152_eee_en(struct r8152 *tp, bool enable)
3111 {
3112         u16 config1, config2, config3;
3113         u32 ocp_data;
3114
3115         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3116         config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
3117         config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
3118         config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
3119
3120         if (enable) {
3121                 ocp_data |= EEE_RX_EN | EEE_TX_EN;
3122                 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
3123                 config1 |= sd_rise_time(1);
3124                 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
3125                 config3 |= fast_snr(42);
3126         } else {
3127                 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3128                 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
3129                              RX_QUIET_EN);
3130                 config1 |= sd_rise_time(7);
3131                 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
3132                 config3 |= fast_snr(511);
3133         }
3134
3135         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
3136         ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
3137         ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
3138         ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
3139 }
3140
3141 static void r8152b_enable_eee(struct r8152 *tp)
3142 {
3143         r8152_eee_en(tp, true);
3144         r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX);
3145 }
3146
3147 static void r8153_eee_en(struct r8152 *tp, bool enable)
3148 {
3149         u32 ocp_data;
3150         u16 config;
3151
3152         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3153         config = ocp_reg_read(tp, OCP_EEE_CFG);
3154
3155         if (enable) {
3156                 ocp_data |= EEE_RX_EN | EEE_TX_EN;
3157                 config |= EEE10_EN;
3158         } else {
3159                 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3160                 config &= ~EEE10_EN;
3161         }
3162
3163         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
3164         ocp_reg_write(tp, OCP_EEE_CFG, config);
3165 }
3166
3167 static void r8153_enable_eee(struct r8152 *tp)
3168 {
3169         r8153_eee_en(tp, true);
3170         ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
3171 }
3172
3173 static void r8152b_enable_fc(struct r8152 *tp)
3174 {
3175         u16 anar;
3176
3177         anar = r8152_mdio_read(tp, MII_ADVERTISE);
3178         anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3179         r8152_mdio_write(tp, MII_ADVERTISE, anar);
3180 }
3181
3182 static void rtl_tally_reset(struct r8152 *tp)
3183 {
3184         u32 ocp_data;
3185
3186         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
3187         ocp_data |= TALLY_RESET;
3188         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
3189 }
3190
3191 static void r8152b_init(struct r8152 *tp)
3192 {
3193         u32 ocp_data;
3194
3195         if (test_bit(RTL8152_UNPLUG, &tp->flags))
3196                 return;
3197
3198         r8152b_disable_aldps(tp);
3199
3200         if (tp->version == RTL_VER_01) {
3201                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
3202                 ocp_data &= ~LED_MODE_MASK;
3203                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
3204         }
3205
3206         r8152_power_cut_en(tp, false);
3207
3208         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
3209         ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
3210         ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
3211         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
3212         ocp_data &= ~MCU_CLK_RATIO_MASK;
3213         ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
3214         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
3215         ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
3216                    SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
3217         ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
3218
3219         r8152b_enable_eee(tp);
3220         r8152b_enable_aldps(tp);
3221         r8152b_enable_fc(tp);
3222         rtl_tally_reset(tp);
3223
3224         /* enable rx aggregation */
3225         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
3226         ocp_data &= ~RX_AGG_DISABLE;
3227         ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
3228 }
3229
3230 static void r8153_init(struct r8152 *tp)
3231 {
3232         u32 ocp_data;
3233         int i;
3234
3235         if (test_bit(RTL8152_UNPLUG, &tp->flags))
3236                 return;
3237
3238         r8153_disable_aldps(tp);
3239         r8153_u1u2en(tp, false);
3240
3241         for (i = 0; i < 500; i++) {
3242                 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
3243                     AUTOLOAD_DONE)
3244                         break;
3245                 msleep(20);
3246         }
3247
3248         for (i = 0; i < 500; i++) {
3249                 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
3250                 if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
3251                         break;
3252                 msleep(20);
3253         }
3254
3255         r8153_u2p3en(tp, false);
3256
3257         if (tp->version == RTL_VER_04) {
3258                 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
3259                 ocp_data &= ~pwd_dn_scale_mask;
3260                 ocp_data |= pwd_dn_scale(96);
3261                 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
3262
3263                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
3264                 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
3265                 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
3266         } else if (tp->version == RTL_VER_05) {
3267                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
3268                 ocp_data &= ~ECM_ALDPS;
3269                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
3270
3271                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
3272                 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
3273                         ocp_data &= ~DYNAMIC_BURST;
3274                 else
3275                         ocp_data |= DYNAMIC_BURST;
3276                 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
3277         }
3278
3279         ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
3280         ocp_data |= EP4_FULL_FC;
3281         ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
3282
3283         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
3284         ocp_data &= ~TIMER11_EN;
3285         ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
3286
3287         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
3288         ocp_data &= ~LED_MODE_MASK;
3289         ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
3290
3291         ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
3292         if (tp->version == RTL_VER_04 && tp->udev->speed != USB_SPEED_SUPER)
3293                 ocp_data |= LPM_TIMER_500MS;
3294         else
3295                 ocp_data |= LPM_TIMER_500US;
3296         ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
3297
3298         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
3299         ocp_data &= ~SEN_VAL_MASK;
3300         ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
3301         ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
3302
3303         ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
3304
3305         r8153_power_cut_en(tp, false);
3306         r8153_u1u2en(tp, true);
3307
3308         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ALDPS_SPDWN_RATIO);
3309         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, EEE_SPDWN_RATIO);
3310         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
3311                        PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN |
3312                        U1U2_SPDWN_EN | L1_SPDWN_EN);
3313         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
3314                        PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN |
3315                        TP100_SPDWN_EN | TP500_SPDWN_EN | TP1000_SPDWN_EN |
3316                        EEE_SPDWN_EN);
3317
3318         r8153_enable_eee(tp);
3319         r8153_enable_aldps(tp);
3320         r8152b_enable_fc(tp);
3321         rtl_tally_reset(tp);
3322 }
3323
3324 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
3325 {
3326         struct r8152 *tp = usb_get_intfdata(intf);
3327         struct net_device *netdev = tp->netdev;
3328         int ret = 0;
3329
3330         mutex_lock(&tp->control);
3331
3332         if (PMSG_IS_AUTO(message)) {
3333                 if (netif_running(netdev) && work_busy(&tp->schedule.work)) {
3334                         ret = -EBUSY;
3335                         goto out1;
3336                 }
3337
3338                 set_bit(SELECTIVE_SUSPEND, &tp->flags);
3339         } else {
3340                 netif_device_detach(netdev);
3341         }
3342
3343         if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
3344                 clear_bit(WORK_ENABLE, &tp->flags);
3345                 usb_kill_urb(tp->intr_urb);
3346                 napi_disable(&tp->napi);
3347                 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3348                         rtl_stop_rx(tp);
3349                         rtl_runtime_suspend_enable(tp, true);
3350                 } else {
3351                         cancel_delayed_work_sync(&tp->schedule);
3352                         tp->rtl_ops.down(tp);
3353                 }
3354                 napi_enable(&tp->napi);
3355         }
3356 out1:
3357         mutex_unlock(&tp->control);
3358
3359         return ret;
3360 }
3361
3362 static int rtl8152_resume(struct usb_interface *intf)
3363 {
3364         struct r8152 *tp = usb_get_intfdata(intf);
3365
3366         mutex_lock(&tp->control);
3367
3368         if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3369                 tp->rtl_ops.init(tp);
3370                 netif_device_attach(tp->netdev);
3371         }
3372
3373         if (netif_running(tp->netdev)) {
3374                 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3375                         rtl_runtime_suspend_enable(tp, false);
3376                         clear_bit(SELECTIVE_SUSPEND, &tp->flags);
3377                         set_bit(WORK_ENABLE, &tp->flags);
3378                         if (netif_carrier_ok(tp->netdev))
3379                                 rtl_start_rx(tp);
3380                 } else {
3381                         tp->rtl_ops.up(tp);
3382                         rtl8152_set_speed(tp, AUTONEG_ENABLE,
3383                                           tp->mii.supports_gmii ?
3384                                           SPEED_1000 : SPEED_100,
3385                                           DUPLEX_FULL);
3386                         netif_carrier_off(tp->netdev);
3387                         set_bit(WORK_ENABLE, &tp->flags);
3388                 }
3389                 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
3390         } else if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3391                 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
3392         }
3393
3394         mutex_unlock(&tp->control);
3395
3396         return 0;
3397 }
3398
3399 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3400 {
3401         struct r8152 *tp = netdev_priv(dev);
3402
3403         if (usb_autopm_get_interface(tp->intf) < 0)
3404                 return;
3405
3406         mutex_lock(&tp->control);
3407
3408         wol->supported = WAKE_ANY;
3409         wol->wolopts = __rtl_get_wol(tp);
3410
3411         mutex_unlock(&tp->control);
3412
3413         usb_autopm_put_interface(tp->intf);
3414 }
3415
3416 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3417 {
3418         struct r8152 *tp = netdev_priv(dev);
3419         int ret;
3420
3421         ret = usb_autopm_get_interface(tp->intf);
3422         if (ret < 0)
3423                 goto out_set_wol;
3424
3425         mutex_lock(&tp->control);
3426
3427         __rtl_set_wol(tp, wol->wolopts);
3428         tp->saved_wolopts = wol->wolopts & WAKE_ANY;
3429
3430         mutex_unlock(&tp->control);
3431
3432         usb_autopm_put_interface(tp->intf);
3433
3434 out_set_wol:
3435         return ret;
3436 }
3437
3438 static u32 rtl8152_get_msglevel(struct net_device *dev)
3439 {
3440         struct r8152 *tp = netdev_priv(dev);
3441
3442         return tp->msg_enable;
3443 }
3444
3445 static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
3446 {
3447         struct r8152 *tp = netdev_priv(dev);
3448
3449         tp->msg_enable = value;
3450 }
3451
3452 static void rtl8152_get_drvinfo(struct net_device *netdev,
3453                                 struct ethtool_drvinfo *info)
3454 {
3455         struct r8152 *tp = netdev_priv(netdev);
3456
3457         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
3458         strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
3459         usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
3460 }
3461
3462 static
3463 int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
3464 {
3465         struct r8152 *tp = netdev_priv(netdev);
3466         int ret;
3467
3468         if (!tp->mii.mdio_read)
3469                 return -EOPNOTSUPP;
3470
3471         ret = usb_autopm_get_interface(tp->intf);
3472         if (ret < 0)
3473                 goto out;
3474
3475         mutex_lock(&tp->control);
3476
3477         ret = mii_ethtool_gset(&tp->mii, cmd);
3478
3479         mutex_unlock(&tp->control);
3480
3481         usb_autopm_put_interface(tp->intf);
3482
3483 out:
3484         return ret;
3485 }
3486
3487 static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
3488 {
3489         struct r8152 *tp = netdev_priv(dev);
3490         int ret;
3491
3492         ret = usb_autopm_get_interface(tp->intf);
3493         if (ret < 0)
3494                 goto out;
3495
3496         mutex_lock(&tp->control);
3497
3498         ret = rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex);
3499
3500         mutex_unlock(&tp->control);
3501
3502         usb_autopm_put_interface(tp->intf);
3503
3504 out:
3505         return ret;
3506 }
3507
3508 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
3509         "tx_packets",
3510         "rx_packets",
3511         "tx_errors",
3512         "rx_errors",
3513         "rx_missed",
3514         "align_errors",
3515         "tx_single_collisions",
3516         "tx_multi_collisions",
3517         "rx_unicast",
3518         "rx_broadcast",
3519         "rx_multicast",
3520         "tx_aborted",
3521         "tx_underrun",
3522 };
3523
3524 static int rtl8152_get_sset_count(struct net_device *dev, int sset)
3525 {
3526         switch (sset) {
3527         case ETH_SS_STATS:
3528                 return ARRAY_SIZE(rtl8152_gstrings);
3529         default:
3530                 return -EOPNOTSUPP;
3531         }
3532 }
3533
3534 static void rtl8152_get_ethtool_stats(struct net_device *dev,
3535                                       struct ethtool_stats *stats, u64 *data)
3536 {
3537         struct r8152 *tp = netdev_priv(dev);
3538         struct tally_counter tally;
3539
3540         if (usb_autopm_get_interface(tp->intf) < 0)
3541                 return;
3542
3543         generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
3544
3545         usb_autopm_put_interface(tp->intf);
3546
3547         data[0] = le64_to_cpu(tally.tx_packets);
3548         data[1] = le64_to_cpu(tally.rx_packets);
3549         data[2] = le64_to_cpu(tally.tx_errors);
3550         data[3] = le32_to_cpu(tally.rx_errors);
3551         data[4] = le16_to_cpu(tally.rx_missed);
3552         data[5] = le16_to_cpu(tally.align_errors);
3553         data[6] = le32_to_cpu(tally.tx_one_collision);
3554         data[7] = le32_to_cpu(tally.tx_multi_collision);
3555         data[8] = le64_to_cpu(tally.rx_unicast);
3556         data[9] = le64_to_cpu(tally.rx_broadcast);
3557         data[10] = le32_to_cpu(tally.rx_multicast);
3558         data[11] = le16_to_cpu(tally.tx_aborted);
3559         data[12] = le16_to_cpu(tally.tx_underrun);
3560 }
3561
3562 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
3563 {
3564         switch (stringset) {
3565         case ETH_SS_STATS:
3566                 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
3567                 break;
3568         }
3569 }
3570
3571 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
3572 {
3573         u32 ocp_data, lp, adv, supported = 0;
3574         u16 val;
3575
3576         val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
3577         supported = mmd_eee_cap_to_ethtool_sup_t(val);
3578
3579         val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
3580         adv = mmd_eee_adv_to_ethtool_adv_t(val);
3581
3582         val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
3583         lp = mmd_eee_adv_to_ethtool_adv_t(val);
3584
3585         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3586         ocp_data &= EEE_RX_EN | EEE_TX_EN;
3587
3588         eee->eee_enabled = !!ocp_data;
3589         eee->eee_active = !!(supported & adv & lp);
3590         eee->supported = supported;
3591         eee->advertised = adv;
3592         eee->lp_advertised = lp;
3593
3594         return 0;
3595 }
3596
3597 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
3598 {
3599         u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
3600
3601         r8152_eee_en(tp, eee->eee_enabled);
3602
3603         if (!eee->eee_enabled)
3604                 val = 0;
3605
3606         r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
3607
3608         return 0;
3609 }
3610
3611 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
3612 {
3613         u32 ocp_data, lp, adv, supported = 0;
3614         u16 val;
3615
3616         val = ocp_reg_read(tp, OCP_EEE_ABLE);
3617         supported = mmd_eee_cap_to_ethtool_sup_t(val);
3618
3619         val = ocp_reg_read(tp, OCP_EEE_ADV);
3620         adv = mmd_eee_adv_to_ethtool_adv_t(val);
3621
3622         val = ocp_reg_read(tp, OCP_EEE_LPABLE);
3623         lp = mmd_eee_adv_to_ethtool_adv_t(val);
3624
3625         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3626         ocp_data &= EEE_RX_EN | EEE_TX_EN;
3627
3628         eee->eee_enabled = !!ocp_data;
3629         eee->eee_active = !!(supported & adv & lp);
3630         eee->supported = supported;
3631         eee->advertised = adv;
3632         eee->lp_advertised = lp;
3633
3634         return 0;
3635 }
3636
3637 static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
3638 {
3639         u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
3640
3641         r8153_eee_en(tp, eee->eee_enabled);
3642
3643         if (!eee->eee_enabled)
3644                 val = 0;
3645
3646         ocp_reg_write(tp, OCP_EEE_ADV, val);
3647
3648         return 0;
3649 }
3650
3651 static int
3652 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
3653 {
3654         struct r8152 *tp = netdev_priv(net);
3655         int ret;
3656
3657         ret = usb_autopm_get_interface(tp->intf);
3658         if (ret < 0)
3659                 goto out;
3660
3661         mutex_lock(&tp->control);
3662
3663         ret = tp->rtl_ops.eee_get(tp, edata);
3664
3665         mutex_unlock(&tp->control);
3666
3667         usb_autopm_put_interface(tp->intf);
3668
3669 out:
3670         return ret;
3671 }
3672
3673 static int
3674 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
3675 {
3676         struct r8152 *tp = netdev_priv(net);
3677         int ret;
3678
3679         ret = usb_autopm_get_interface(tp->intf);
3680         if (ret < 0)
3681                 goto out;
3682
3683         mutex_lock(&tp->control);
3684
3685         ret = tp->rtl_ops.eee_set(tp, edata);
3686         if (!ret)
3687                 ret = mii_nway_restart(&tp->mii);
3688
3689         mutex_unlock(&tp->control);
3690
3691         usb_autopm_put_interface(tp->intf);
3692
3693 out:
3694         return ret;
3695 }
3696
3697 static int rtl8152_nway_reset(struct net_device *dev)
3698 {
3699         struct r8152 *tp = netdev_priv(dev);
3700         int ret;
3701
3702         ret = usb_autopm_get_interface(tp->intf);
3703         if (ret < 0)
3704                 goto out;
3705
3706         mutex_lock(&tp->control);
3707
3708         ret = mii_nway_restart(&tp->mii);
3709
3710         mutex_unlock(&tp->control);
3711
3712         usb_autopm_put_interface(tp->intf);
3713
3714 out:
3715         return ret;
3716 }
3717
3718 static int rtl8152_get_coalesce(struct net_device *netdev,
3719                                 struct ethtool_coalesce *coalesce)
3720 {
3721         struct r8152 *tp = netdev_priv(netdev);
3722
3723         switch (tp->version) {
3724         case RTL_VER_01:
3725         case RTL_VER_02:
3726                 return -EOPNOTSUPP;
3727         default:
3728                 break;
3729         }
3730
3731         coalesce->rx_coalesce_usecs = tp->coalesce;
3732
3733         return 0;
3734 }
3735
3736 static int rtl8152_set_coalesce(struct net_device *netdev,
3737                                 struct ethtool_coalesce *coalesce)
3738 {
3739         struct r8152 *tp = netdev_priv(netdev);
3740         int ret;
3741
3742         switch (tp->version) {
3743         case RTL_VER_01:
3744         case RTL_VER_02:
3745                 return -EOPNOTSUPP;
3746         default:
3747                 break;
3748         }
3749
3750         if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
3751                 return -EINVAL;
3752
3753         ret = usb_autopm_get_interface(tp->intf);
3754         if (ret < 0)
3755                 return ret;
3756
3757         mutex_lock(&tp->control);
3758
3759         if (tp->coalesce != coalesce->rx_coalesce_usecs) {
3760                 tp->coalesce = coalesce->rx_coalesce_usecs;
3761
3762                 if (netif_running(tp->netdev) && netif_carrier_ok(netdev))
3763                         r8153_set_rx_early_timeout(tp);
3764         }
3765
3766         mutex_unlock(&tp->control);
3767
3768         usb_autopm_put_interface(tp->intf);
3769
3770         return ret;
3771 }
3772
3773 static struct ethtool_ops ops = {
3774         .get_drvinfo = rtl8152_get_drvinfo,
3775         .get_settings = rtl8152_get_settings,
3776         .set_settings = rtl8152_set_settings,
3777         .get_link = ethtool_op_get_link,
3778         .nway_reset = rtl8152_nway_reset,
3779         .get_msglevel = rtl8152_get_msglevel,
3780         .set_msglevel = rtl8152_set_msglevel,
3781         .get_wol = rtl8152_get_wol,
3782         .set_wol = rtl8152_set_wol,
3783         .get_strings = rtl8152_get_strings,
3784         .get_sset_count = rtl8152_get_sset_count,
3785         .get_ethtool_stats = rtl8152_get_ethtool_stats,
3786         .get_coalesce = rtl8152_get_coalesce,
3787         .set_coalesce = rtl8152_set_coalesce,
3788         .get_eee = rtl_ethtool_get_eee,
3789         .set_eee = rtl_ethtool_set_eee,
3790 };
3791
3792 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
3793 {
3794         struct r8152 *tp = netdev_priv(netdev);
3795         struct mii_ioctl_data *data = if_mii(rq);
3796         int res;
3797
3798         if (test_bit(RTL8152_UNPLUG, &tp->flags))
3799                 return -ENODEV;
3800
3801         res = usb_autopm_get_interface(tp->intf);
3802         if (res < 0)
3803                 goto out;
3804
3805         switch (cmd) {
3806         case SIOCGMIIPHY:
3807                 data->phy_id = R8152_PHY_ID; /* Internal PHY */
3808                 break;
3809
3810         case SIOCGMIIREG:
3811                 mutex_lock(&tp->control);
3812                 data->val_out = r8152_mdio_read(tp, data->reg_num);
3813                 mutex_unlock(&tp->control);
3814                 break;
3815
3816         case SIOCSMIIREG:
3817                 if (!capable(CAP_NET_ADMIN)) {
3818                         res = -EPERM;
3819                         break;
3820                 }
3821                 mutex_lock(&tp->control);
3822                 r8152_mdio_write(tp, data->reg_num, data->val_in);
3823                 mutex_unlock(&tp->control);
3824                 break;
3825
3826         default:
3827                 res = -EOPNOTSUPP;
3828         }
3829
3830         usb_autopm_put_interface(tp->intf);
3831
3832 out:
3833         return res;
3834 }
3835
3836 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
3837 {
3838         struct r8152 *tp = netdev_priv(dev);
3839         int ret;
3840
3841         switch (tp->version) {
3842         case RTL_VER_01:
3843         case RTL_VER_02:
3844                 return eth_change_mtu(dev, new_mtu);
3845         default:
3846                 break;
3847         }
3848
3849         if (new_mtu < 68 || new_mtu > RTL8153_MAX_MTU)
3850                 return -EINVAL;
3851
3852         ret = usb_autopm_get_interface(tp->intf);
3853         if (ret < 0)
3854                 return ret;
3855
3856         mutex_lock(&tp->control);
3857
3858         dev->mtu = new_mtu;
3859
3860         if (netif_running(dev) && netif_carrier_ok(dev))
3861                 r8153_set_rx_early_size(tp);
3862
3863         mutex_unlock(&tp->control);
3864
3865         usb_autopm_put_interface(tp->intf);
3866
3867         return ret;
3868 }
3869
3870 static const struct net_device_ops rtl8152_netdev_ops = {
3871         .ndo_open               = rtl8152_open,
3872         .ndo_stop               = rtl8152_close,
3873         .ndo_do_ioctl           = rtl8152_ioctl,
3874         .ndo_start_xmit         = rtl8152_start_xmit,
3875         .ndo_tx_timeout         = rtl8152_tx_timeout,
3876         .ndo_set_features       = rtl8152_set_features,
3877         .ndo_set_rx_mode        = rtl8152_set_rx_mode,
3878         .ndo_set_mac_address    = rtl8152_set_mac_address,
3879         .ndo_change_mtu         = rtl8152_change_mtu,
3880         .ndo_validate_addr      = eth_validate_addr,
3881         .ndo_features_check     = rtl8152_features_check,
3882 };
3883
3884 static void r8152b_get_version(struct r8152 *tp)
3885 {
3886         u32     ocp_data;
3887         u16     version;
3888
3889         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
3890         version = (u16)(ocp_data & VERSION_MASK);
3891
3892         switch (version) {
3893         case 0x4c00:
3894                 tp->version = RTL_VER_01;
3895                 break;
3896         case 0x4c10:
3897                 tp->version = RTL_VER_02;
3898                 break;
3899         case 0x5c00:
3900                 tp->version = RTL_VER_03;
3901                 tp->mii.supports_gmii = 1;
3902                 break;
3903         case 0x5c10:
3904                 tp->version = RTL_VER_04;
3905                 tp->mii.supports_gmii = 1;
3906                 break;
3907         case 0x5c20:
3908                 tp->version = RTL_VER_05;
3909                 tp->mii.supports_gmii = 1;
3910                 break;
3911         default:
3912                 netif_info(tp, probe, tp->netdev,
3913                            "Unknown version 0x%04x\n", version);
3914                 break;
3915         }
3916 }
3917
3918 static void rtl8152_unload(struct r8152 *tp)
3919 {
3920         if (test_bit(RTL8152_UNPLUG, &tp->flags))
3921                 return;
3922
3923         if (tp->version != RTL_VER_01)
3924                 r8152_power_cut_en(tp, true);
3925 }
3926
3927 static void rtl8153_unload(struct r8152 *tp)
3928 {
3929         if (test_bit(RTL8152_UNPLUG, &tp->flags))
3930                 return;
3931
3932         r8153_power_cut_en(tp, false);
3933 }
3934
3935 static int rtl_ops_init(struct r8152 *tp)
3936 {
3937         struct rtl_ops *ops = &tp->rtl_ops;
3938         int ret = 0;
3939
3940         switch (tp->version) {
3941         case RTL_VER_01:
3942         case RTL_VER_02:
3943                 ops->init               = r8152b_init;
3944                 ops->enable             = rtl8152_enable;
3945                 ops->disable            = rtl8152_disable;
3946                 ops->up                 = rtl8152_up;
3947                 ops->down               = rtl8152_down;
3948                 ops->unload             = rtl8152_unload;
3949                 ops->eee_get            = r8152_get_eee;
3950                 ops->eee_set            = r8152_set_eee;
3951                 break;
3952
3953         case RTL_VER_03:
3954         case RTL_VER_04:
3955         case RTL_VER_05:
3956                 ops->init               = r8153_init;
3957                 ops->enable             = rtl8153_enable;
3958                 ops->disable            = rtl8153_disable;
3959                 ops->up                 = rtl8153_up;
3960                 ops->down               = rtl8153_down;
3961                 ops->unload             = rtl8153_unload;
3962                 ops->eee_get            = r8153_get_eee;
3963                 ops->eee_set            = r8153_set_eee;
3964                 break;
3965
3966         default:
3967                 ret = -ENODEV;
3968                 netif_err(tp, probe, tp->netdev, "Unknown Device\n");
3969                 break;
3970         }
3971
3972         return ret;
3973 }
3974
3975 static int rtl8152_probe(struct usb_interface *intf,
3976                          const struct usb_device_id *id)
3977 {
3978         struct usb_device *udev = interface_to_usbdev(intf);
3979         struct r8152 *tp;
3980         struct net_device *netdev;
3981         int ret;
3982
3983         if (udev->actconfig->desc.bConfigurationValue != 1) {
3984                 usb_driver_set_configuration(udev, 1);
3985                 return -ENODEV;
3986         }
3987
3988         usb_reset_device(udev);
3989         netdev = alloc_etherdev(sizeof(struct r8152));
3990         if (!netdev) {
3991                 dev_err(&intf->dev, "Out of memory\n");
3992                 return -ENOMEM;
3993         }
3994
3995         SET_NETDEV_DEV(netdev, &intf->dev);
3996         tp = netdev_priv(netdev);
3997         tp->msg_enable = 0x7FFF;
3998
3999         tp->udev = udev;
4000         tp->netdev = netdev;
4001         tp->intf = intf;
4002
4003         r8152b_get_version(tp);
4004         ret = rtl_ops_init(tp);
4005         if (ret)
4006                 goto out;
4007
4008         mutex_init(&tp->control);
4009         INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
4010
4011         netdev->netdev_ops = &rtl8152_netdev_ops;
4012         netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
4013
4014         netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
4015                             NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
4016                             NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
4017                             NETIF_F_HW_VLAN_CTAG_TX;
4018         netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
4019                               NETIF_F_TSO | NETIF_F_FRAGLIST |
4020                               NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
4021                               NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
4022         netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
4023                                 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
4024                                 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
4025
4026         netdev->ethtool_ops = &ops;
4027         netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
4028
4029         tp->mii.dev = netdev;
4030         tp->mii.mdio_read = read_mii_word;
4031         tp->mii.mdio_write = write_mii_word;
4032         tp->mii.phy_id_mask = 0x3f;
4033         tp->mii.reg_num_mask = 0x1f;
4034         tp->mii.phy_id = R8152_PHY_ID;
4035
4036         switch (udev->speed) {
4037         case USB_SPEED_SUPER:
4038                 tp->coalesce = COALESCE_SUPER;
4039                 break;
4040         case USB_SPEED_HIGH:
4041                 tp->coalesce = COALESCE_HIGH;
4042                 break;
4043         default:
4044                 tp->coalesce = COALESCE_SLOW;
4045                 break;
4046         }
4047
4048         intf->needs_remote_wakeup = 1;
4049
4050         tp->rtl_ops.init(tp);
4051         set_ethernet_addr(tp);
4052
4053         usb_set_intfdata(intf, tp);
4054         netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT);
4055
4056         ret = register_netdev(netdev);
4057         if (ret != 0) {
4058                 netif_err(tp, probe, netdev, "couldn't register the device\n");
4059                 goto out1;
4060         }
4061
4062         tp->saved_wolopts = __rtl_get_wol(tp);
4063         if (tp->saved_wolopts)
4064                 device_set_wakeup_enable(&udev->dev, true);
4065         else
4066                 device_set_wakeup_enable(&udev->dev, false);
4067
4068         netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
4069
4070         return 0;
4071
4072 out1:
4073         netif_napi_del(&tp->napi);
4074         usb_set_intfdata(intf, NULL);
4075 out:
4076         free_netdev(netdev);
4077         return ret;
4078 }
4079
4080 static void rtl8152_disconnect(struct usb_interface *intf)
4081 {
4082         struct r8152 *tp = usb_get_intfdata(intf);
4083
4084         usb_set_intfdata(intf, NULL);
4085         if (tp) {
4086                 struct usb_device *udev = tp->udev;
4087
4088                 if (udev->state == USB_STATE_NOTATTACHED)
4089                         set_bit(RTL8152_UNPLUG, &tp->flags);
4090
4091                 netif_napi_del(&tp->napi);
4092                 unregister_netdev(tp->netdev);
4093                 tp->rtl_ops.unload(tp);
4094                 free_netdev(tp->netdev);
4095         }
4096 }
4097
4098 #define REALTEK_USB_DEVICE(vend, prod)  \
4099         .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \
4100                        USB_DEVICE_ID_MATCH_INT_CLASS, \
4101         .idVendor = (vend), \
4102         .idProduct = (prod), \
4103         .bInterfaceClass = USB_CLASS_VENDOR_SPEC \
4104 }, \
4105 { \
4106         .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \
4107                        USB_DEVICE_ID_MATCH_DEVICE, \
4108         .idVendor = (vend), \
4109         .idProduct = (prod), \
4110         .bInterfaceClass = USB_CLASS_COMM, \
4111         .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
4112         .bInterfaceProtocol = USB_CDC_PROTO_NONE
4113
4114 /* table of devices that work with this driver */
4115 static struct usb_device_id rtl8152_table[] = {
4116         {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
4117         {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
4118         {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
4119         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x7205)},
4120         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x304f)},
4121         {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA,  0x09ff)},
4122         {}
4123 };
4124
4125 MODULE_DEVICE_TABLE(usb, rtl8152_table);
4126
4127 static struct usb_driver rtl8152_driver = {
4128         .name =         MODULENAME,
4129         .id_table =     rtl8152_table,
4130         .probe =        rtl8152_probe,
4131         .disconnect =   rtl8152_disconnect,
4132         .suspend =      rtl8152_suspend,
4133         .resume =       rtl8152_resume,
4134         .reset_resume = rtl8152_resume,
4135         .supports_autosuspend = 1,
4136         .disable_hub_initiated_lpm = 1,
4137 };
4138
4139 module_usb_driver(rtl8152_driver);
4140
4141 MODULE_AUTHOR(DRIVER_AUTHOR);
4142 MODULE_DESCRIPTION(DRIVER_DESC);
4143 MODULE_LICENSE("GPL");