2 * Texas Instruments CPDMA Driver
4 * Copyright (C) 2010 Texas Instruments
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 #include <linux/kernel.h>
16 #include <linux/spinlock.h>
17 #include <linux/device.h>
18 #include <linux/module.h>
19 #include <linux/slab.h>
20 #include <linux/err.h>
21 #include <linux/dma-mapping.h>
23 #include <linux/delay.h>
25 #include "davinci_cpdma.h"
28 #define CPDMA_TXIDVER 0x00
29 #define CPDMA_TXCONTROL 0x04
30 #define CPDMA_TXTEARDOWN 0x08
31 #define CPDMA_RXIDVER 0x10
32 #define CPDMA_RXCONTROL 0x14
33 #define CPDMA_SOFTRESET 0x1c
34 #define CPDMA_RXTEARDOWN 0x18
35 #define CPDMA_TXINTSTATRAW 0x80
36 #define CPDMA_TXINTSTATMASKED 0x84
37 #define CPDMA_TXINTMASKSET 0x88
38 #define CPDMA_TXINTMASKCLEAR 0x8c
39 #define CPDMA_MACINVECTOR 0x90
40 #define CPDMA_MACEOIVECTOR 0x94
41 #define CPDMA_RXINTSTATRAW 0xa0
42 #define CPDMA_RXINTSTATMASKED 0xa4
43 #define CPDMA_RXINTMASKSET 0xa8
44 #define CPDMA_RXINTMASKCLEAR 0xac
45 #define CPDMA_DMAINTSTATRAW 0xb0
46 #define CPDMA_DMAINTSTATMASKED 0xb4
47 #define CPDMA_DMAINTMASKSET 0xb8
48 #define CPDMA_DMAINTMASKCLEAR 0xbc
49 #define CPDMA_DMAINT_HOSTERR BIT(1)
51 /* the following exist only if has_ext_regs is set */
52 #define CPDMA_DMACONTROL 0x20
53 #define CPDMA_DMASTATUS 0x24
54 #define CPDMA_RXBUFFOFS 0x28
55 #define CPDMA_EM_CONTROL 0x2c
57 /* Descriptor mode bits */
58 #define CPDMA_DESC_SOP BIT(31)
59 #define CPDMA_DESC_EOP BIT(30)
60 #define CPDMA_DESC_OWNER BIT(29)
61 #define CPDMA_DESC_EOQ BIT(28)
62 #define CPDMA_DESC_TD_COMPLETE BIT(27)
63 #define CPDMA_DESC_PASS_CRC BIT(26)
64 #define CPDMA_DESC_TO_PORT_EN BIT(20)
65 #define CPDMA_TO_PORT_SHIFT 16
66 #define CPDMA_DESC_PORT_MASK (BIT(18) | BIT(17) | BIT(16))
67 #define CPDMA_DESC_CRC_LEN 4
69 #define CPDMA_TEARDOWN_VALUE 0xfffffffc
83 struct cpdma_desc_pool {
86 void __iomem *iomap; /* ioremap map */
87 void *cpumap; /* dma_alloc map */
88 int desc_size, mem_size;
89 int num_desc, used_desc;
90 unsigned long *bitmap;
101 static const char *cpdma_state_str[] = { "idle", "active", "teardown" };
104 enum cpdma_state state;
105 struct cpdma_params params;
107 struct cpdma_desc_pool *pool;
109 struct cpdma_chan *channels[2 * CPDMA_MAX_CHANNELS];
113 struct cpdma_desc __iomem *head, *tail;
114 void __iomem *hdp, *cp, *rxfree;
115 enum cpdma_state state;
116 struct cpdma_ctlr *ctlr;
121 cpdma_handler_fn handler;
122 enum dma_data_direction dir;
123 struct cpdma_chan_stats stats;
124 /* offsets into dmaregs */
125 int int_set, int_clear, td;
128 /* The following make access to common cpdma_ctlr params more readable */
129 #define dmaregs params.dmaregs
130 #define num_chan params.num_chan
132 /* various accessors */
133 #define dma_reg_read(ctlr, ofs) __raw_readl((ctlr)->dmaregs + (ofs))
134 #define chan_read(chan, fld) __raw_readl((chan)->fld)
135 #define desc_read(desc, fld) __raw_readl(&(desc)->fld)
136 #define dma_reg_write(ctlr, ofs, v) __raw_writel(v, (ctlr)->dmaregs + (ofs))
137 #define chan_write(chan, fld, v) __raw_writel(v, (chan)->fld)
138 #define desc_write(desc, fld, v) __raw_writel((u32)(v), &(desc)->fld)
140 #define cpdma_desc_to_port(chan, mode, directed) \
142 if (!is_rx_chan(chan) && ((directed == 1) || \
144 mode |= (CPDMA_DESC_TO_PORT_EN | \
145 (directed << CPDMA_TO_PORT_SHIFT)); \
149 * Utility constructs for a cpdma descriptor pool. Some devices (e.g. davinci
150 * emac) have dedicated on-chip memory for these descriptors. Some other
151 * devices (e.g. cpsw switches) use plain old memory. Descriptor pools
152 * abstract out these details
154 static struct cpdma_desc_pool *
155 cpdma_desc_pool_create(struct device *dev, u32 phys, u32 hw_addr,
159 struct cpdma_desc_pool *pool;
161 pool = kzalloc(sizeof(*pool), GFP_KERNEL);
165 spin_lock_init(&pool->lock);
168 pool->mem_size = size;
169 pool->desc_size = ALIGN(sizeof(struct cpdma_desc), align);
170 pool->num_desc = size / pool->desc_size;
172 bitmap_size = (pool->num_desc / BITS_PER_LONG) * sizeof(long);
173 pool->bitmap = kzalloc(bitmap_size, GFP_KERNEL);
179 pool->iomap = ioremap(phys, size);
180 pool->hw_addr = hw_addr;
182 pool->cpumap = dma_alloc_coherent(dev, size, &pool->phys,
184 pool->iomap = pool->cpumap;
185 pool->hw_addr = pool->phys;
197 static void cpdma_desc_pool_destroy(struct cpdma_desc_pool *pool)
204 spin_lock_irqsave(&pool->lock, flags);
205 WARN_ON(pool->used_desc);
208 dma_free_coherent(pool->dev, pool->mem_size, pool->cpumap,
211 iounmap(pool->iomap);
213 spin_unlock_irqrestore(&pool->lock, flags);
217 static inline dma_addr_t desc_phys(struct cpdma_desc_pool *pool,
218 struct cpdma_desc __iomem *desc)
222 return pool->hw_addr + (__force dma_addr_t)desc -
223 (__force dma_addr_t)pool->iomap;
226 static inline struct cpdma_desc __iomem *
227 desc_from_phys(struct cpdma_desc_pool *pool, dma_addr_t dma)
229 return dma ? pool->iomap + dma - pool->hw_addr : NULL;
232 static struct cpdma_desc __iomem *
233 cpdma_desc_alloc(struct cpdma_desc_pool *pool, int num_desc, bool is_rx)
239 struct cpdma_desc __iomem *desc = NULL;
241 spin_lock_irqsave(&pool->lock, flags);
245 desc_end = pool->num_desc/2;
247 desc_start = pool->num_desc/2;
248 desc_end = pool->num_desc;
251 index = bitmap_find_next_zero_area(pool->bitmap,
252 desc_end, desc_start, num_desc, 0);
253 if (index < desc_end) {
254 bitmap_set(pool->bitmap, index, num_desc);
255 desc = pool->iomap + pool->desc_size * index;
259 spin_unlock_irqrestore(&pool->lock, flags);
263 static void cpdma_desc_free(struct cpdma_desc_pool *pool,
264 struct cpdma_desc __iomem *desc, int num_desc)
266 unsigned long flags, index;
268 index = ((unsigned long)desc - (unsigned long)pool->iomap) /
270 spin_lock_irqsave(&pool->lock, flags);
271 bitmap_clear(pool->bitmap, index, num_desc);
273 spin_unlock_irqrestore(&pool->lock, flags);
276 struct cpdma_ctlr *cpdma_ctlr_create(struct cpdma_params *params)
278 struct cpdma_ctlr *ctlr;
280 ctlr = kzalloc(sizeof(*ctlr), GFP_KERNEL);
284 ctlr->state = CPDMA_STATE_IDLE;
285 ctlr->params = *params;
286 ctlr->dev = params->dev;
287 spin_lock_init(&ctlr->lock);
289 ctlr->pool = cpdma_desc_pool_create(ctlr->dev,
290 ctlr->params.desc_mem_phys,
291 ctlr->params.desc_hw_addr,
292 ctlr->params.desc_mem_size,
293 ctlr->params.desc_align);
299 if (WARN_ON(ctlr->num_chan > CPDMA_MAX_CHANNELS))
300 ctlr->num_chan = CPDMA_MAX_CHANNELS;
303 EXPORT_SYMBOL_GPL(cpdma_ctlr_create);
305 int cpdma_ctlr_start(struct cpdma_ctlr *ctlr)
310 spin_lock_irqsave(&ctlr->lock, flags);
311 if (ctlr->state != CPDMA_STATE_IDLE) {
312 spin_unlock_irqrestore(&ctlr->lock, flags);
316 if (ctlr->params.has_soft_reset) {
317 unsigned timeout = 10 * 100;
319 dma_reg_write(ctlr, CPDMA_SOFTRESET, 1);
321 if (dma_reg_read(ctlr, CPDMA_SOFTRESET) == 0)
329 for (i = 0; i < ctlr->num_chan; i++) {
330 __raw_writel(0, ctlr->params.txhdp + 4 * i);
331 __raw_writel(0, ctlr->params.rxhdp + 4 * i);
332 __raw_writel(0, ctlr->params.txcp + 4 * i);
333 __raw_writel(0, ctlr->params.rxcp + 4 * i);
336 dma_reg_write(ctlr, CPDMA_RXINTMASKCLEAR, 0xffffffff);
337 dma_reg_write(ctlr, CPDMA_TXINTMASKCLEAR, 0xffffffff);
339 dma_reg_write(ctlr, CPDMA_TXCONTROL, 1);
340 dma_reg_write(ctlr, CPDMA_RXCONTROL, 1);
342 ctlr->state = CPDMA_STATE_ACTIVE;
344 for (i = 0; i < ARRAY_SIZE(ctlr->channels); i++) {
345 if (ctlr->channels[i])
346 cpdma_chan_start(ctlr->channels[i]);
348 spin_unlock_irqrestore(&ctlr->lock, flags);
351 EXPORT_SYMBOL_GPL(cpdma_ctlr_start);
353 int cpdma_ctlr_stop(struct cpdma_ctlr *ctlr)
358 spin_lock_irqsave(&ctlr->lock, flags);
359 if (ctlr->state != CPDMA_STATE_ACTIVE) {
360 spin_unlock_irqrestore(&ctlr->lock, flags);
364 ctlr->state = CPDMA_STATE_TEARDOWN;
366 for (i = 0; i < ARRAY_SIZE(ctlr->channels); i++) {
367 if (ctlr->channels[i])
368 cpdma_chan_stop(ctlr->channels[i]);
371 dma_reg_write(ctlr, CPDMA_RXINTMASKCLEAR, 0xffffffff);
372 dma_reg_write(ctlr, CPDMA_TXINTMASKCLEAR, 0xffffffff);
374 dma_reg_write(ctlr, CPDMA_TXCONTROL, 0);
375 dma_reg_write(ctlr, CPDMA_RXCONTROL, 0);
377 ctlr->state = CPDMA_STATE_IDLE;
379 spin_unlock_irqrestore(&ctlr->lock, flags);
382 EXPORT_SYMBOL_GPL(cpdma_ctlr_stop);
384 int cpdma_ctlr_dump(struct cpdma_ctlr *ctlr)
386 struct device *dev = ctlr->dev;
390 spin_lock_irqsave(&ctlr->lock, flags);
392 dev_info(dev, "CPDMA: state: %s", cpdma_state_str[ctlr->state]);
394 dev_info(dev, "CPDMA: txidver: %x",
395 dma_reg_read(ctlr, CPDMA_TXIDVER));
396 dev_info(dev, "CPDMA: txcontrol: %x",
397 dma_reg_read(ctlr, CPDMA_TXCONTROL));
398 dev_info(dev, "CPDMA: txteardown: %x",
399 dma_reg_read(ctlr, CPDMA_TXTEARDOWN));
400 dev_info(dev, "CPDMA: rxidver: %x",
401 dma_reg_read(ctlr, CPDMA_RXIDVER));
402 dev_info(dev, "CPDMA: rxcontrol: %x",
403 dma_reg_read(ctlr, CPDMA_RXCONTROL));
404 dev_info(dev, "CPDMA: softreset: %x",
405 dma_reg_read(ctlr, CPDMA_SOFTRESET));
406 dev_info(dev, "CPDMA: rxteardown: %x",
407 dma_reg_read(ctlr, CPDMA_RXTEARDOWN));
408 dev_info(dev, "CPDMA: txintstatraw: %x",
409 dma_reg_read(ctlr, CPDMA_TXINTSTATRAW));
410 dev_info(dev, "CPDMA: txintstatmasked: %x",
411 dma_reg_read(ctlr, CPDMA_TXINTSTATMASKED));
412 dev_info(dev, "CPDMA: txintmaskset: %x",
413 dma_reg_read(ctlr, CPDMA_TXINTMASKSET));
414 dev_info(dev, "CPDMA: txintmaskclear: %x",
415 dma_reg_read(ctlr, CPDMA_TXINTMASKCLEAR));
416 dev_info(dev, "CPDMA: macinvector: %x",
417 dma_reg_read(ctlr, CPDMA_MACINVECTOR));
418 dev_info(dev, "CPDMA: maceoivector: %x",
419 dma_reg_read(ctlr, CPDMA_MACEOIVECTOR));
420 dev_info(dev, "CPDMA: rxintstatraw: %x",
421 dma_reg_read(ctlr, CPDMA_RXINTSTATRAW));
422 dev_info(dev, "CPDMA: rxintstatmasked: %x",
423 dma_reg_read(ctlr, CPDMA_RXINTSTATMASKED));
424 dev_info(dev, "CPDMA: rxintmaskset: %x",
425 dma_reg_read(ctlr, CPDMA_RXINTMASKSET));
426 dev_info(dev, "CPDMA: rxintmaskclear: %x",
427 dma_reg_read(ctlr, CPDMA_RXINTMASKCLEAR));
428 dev_info(dev, "CPDMA: dmaintstatraw: %x",
429 dma_reg_read(ctlr, CPDMA_DMAINTSTATRAW));
430 dev_info(dev, "CPDMA: dmaintstatmasked: %x",
431 dma_reg_read(ctlr, CPDMA_DMAINTSTATMASKED));
432 dev_info(dev, "CPDMA: dmaintmaskset: %x",
433 dma_reg_read(ctlr, CPDMA_DMAINTMASKSET));
434 dev_info(dev, "CPDMA: dmaintmaskclear: %x",
435 dma_reg_read(ctlr, CPDMA_DMAINTMASKCLEAR));
437 if (!ctlr->params.has_ext_regs) {
438 dev_info(dev, "CPDMA: dmacontrol: %x",
439 dma_reg_read(ctlr, CPDMA_DMACONTROL));
440 dev_info(dev, "CPDMA: dmastatus: %x",
441 dma_reg_read(ctlr, CPDMA_DMASTATUS));
442 dev_info(dev, "CPDMA: rxbuffofs: %x",
443 dma_reg_read(ctlr, CPDMA_RXBUFFOFS));
446 for (i = 0; i < ARRAY_SIZE(ctlr->channels); i++)
447 if (ctlr->channels[i])
448 cpdma_chan_dump(ctlr->channels[i]);
450 spin_unlock_irqrestore(&ctlr->lock, flags);
453 EXPORT_SYMBOL_GPL(cpdma_ctlr_dump);
455 int cpdma_ctlr_destroy(struct cpdma_ctlr *ctlr)
463 spin_lock_irqsave(&ctlr->lock, flags);
464 if (ctlr->state != CPDMA_STATE_IDLE)
465 cpdma_ctlr_stop(ctlr);
467 for (i = 0; i < ARRAY_SIZE(ctlr->channels); i++)
468 cpdma_chan_destroy(ctlr->channels[i]);
470 cpdma_desc_pool_destroy(ctlr->pool);
471 spin_unlock_irqrestore(&ctlr->lock, flags);
475 EXPORT_SYMBOL_GPL(cpdma_ctlr_destroy);
477 int cpdma_ctlr_int_ctrl(struct cpdma_ctlr *ctlr, bool enable)
482 spin_lock_irqsave(&ctlr->lock, flags);
483 if (ctlr->state != CPDMA_STATE_ACTIVE) {
484 spin_unlock_irqrestore(&ctlr->lock, flags);
488 reg = enable ? CPDMA_DMAINTMASKSET : CPDMA_DMAINTMASKCLEAR;
489 dma_reg_write(ctlr, reg, CPDMA_DMAINT_HOSTERR);
491 for (i = 0; i < ARRAY_SIZE(ctlr->channels); i++) {
492 if (ctlr->channels[i])
493 cpdma_chan_int_ctrl(ctlr->channels[i], enable);
496 spin_unlock_irqrestore(&ctlr->lock, flags);
499 EXPORT_SYMBOL_GPL(cpdma_ctlr_int_ctrl);
501 void cpdma_ctlr_eoi(struct cpdma_ctlr *ctlr, u32 value)
503 dma_reg_write(ctlr, CPDMA_MACEOIVECTOR, value);
505 EXPORT_SYMBOL_GPL(cpdma_ctlr_eoi);
507 struct cpdma_chan *cpdma_chan_create(struct cpdma_ctlr *ctlr, int chan_num,
508 cpdma_handler_fn handler)
510 struct cpdma_chan *chan;
511 int ret, offset = (chan_num % CPDMA_MAX_CHANNELS) * 4;
514 if (__chan_linear(chan_num) >= ctlr->num_chan)
518 chan = kzalloc(sizeof(*chan), GFP_KERNEL);
522 spin_lock_irqsave(&ctlr->lock, flags);
524 if (ctlr->channels[chan_num])
528 chan->state = CPDMA_STATE_IDLE;
529 chan->chan_num = chan_num;
530 chan->handler = handler;
532 if (is_rx_chan(chan)) {
533 chan->hdp = ctlr->params.rxhdp + offset;
534 chan->cp = ctlr->params.rxcp + offset;
535 chan->rxfree = ctlr->params.rxfree + offset;
536 chan->int_set = CPDMA_RXINTMASKSET;
537 chan->int_clear = CPDMA_RXINTMASKCLEAR;
538 chan->td = CPDMA_RXTEARDOWN;
539 chan->dir = DMA_FROM_DEVICE;
541 chan->hdp = ctlr->params.txhdp + offset;
542 chan->cp = ctlr->params.txcp + offset;
543 chan->int_set = CPDMA_TXINTMASKSET;
544 chan->int_clear = CPDMA_TXINTMASKCLEAR;
545 chan->td = CPDMA_TXTEARDOWN;
546 chan->dir = DMA_TO_DEVICE;
548 chan->mask = BIT(chan_linear(chan));
550 spin_lock_init(&chan->lock);
552 ctlr->channels[chan_num] = chan;
553 spin_unlock_irqrestore(&ctlr->lock, flags);
557 spin_unlock_irqrestore(&ctlr->lock, flags);
562 EXPORT_SYMBOL_GPL(cpdma_chan_create);
564 int cpdma_chan_destroy(struct cpdma_chan *chan)
566 struct cpdma_ctlr *ctlr;
573 spin_lock_irqsave(&ctlr->lock, flags);
574 if (chan->state != CPDMA_STATE_IDLE)
575 cpdma_chan_stop(chan);
576 ctlr->channels[chan->chan_num] = NULL;
577 spin_unlock_irqrestore(&ctlr->lock, flags);
581 EXPORT_SYMBOL_GPL(cpdma_chan_destroy);
583 int cpdma_chan_get_stats(struct cpdma_chan *chan,
584 struct cpdma_chan_stats *stats)
589 spin_lock_irqsave(&chan->lock, flags);
590 memcpy(stats, &chan->stats, sizeof(*stats));
591 spin_unlock_irqrestore(&chan->lock, flags);
594 EXPORT_SYMBOL_GPL(cpdma_chan_get_stats);
596 int cpdma_chan_dump(struct cpdma_chan *chan)
599 struct device *dev = chan->ctlr->dev;
601 spin_lock_irqsave(&chan->lock, flags);
603 dev_info(dev, "channel %d (%s %d) state %s",
604 chan->chan_num, is_rx_chan(chan) ? "rx" : "tx",
605 chan_linear(chan), cpdma_state_str[chan->state]);
606 dev_info(dev, "\thdp: %x\n", chan_read(chan, hdp));
607 dev_info(dev, "\tcp: %x\n", chan_read(chan, cp));
609 dev_info(dev, "\trxfree: %x\n",
610 chan_read(chan, rxfree));
613 dev_info(dev, "\tstats head_enqueue: %d\n",
614 chan->stats.head_enqueue);
615 dev_info(dev, "\tstats tail_enqueue: %d\n",
616 chan->stats.tail_enqueue);
617 dev_info(dev, "\tstats pad_enqueue: %d\n",
618 chan->stats.pad_enqueue);
619 dev_info(dev, "\tstats misqueued: %d\n",
620 chan->stats.misqueued);
621 dev_info(dev, "\tstats desc_alloc_fail: %d\n",
622 chan->stats.desc_alloc_fail);
623 dev_info(dev, "\tstats pad_alloc_fail: %d\n",
624 chan->stats.pad_alloc_fail);
625 dev_info(dev, "\tstats runt_receive_buff: %d\n",
626 chan->stats.runt_receive_buff);
627 dev_info(dev, "\tstats runt_transmit_buff: %d\n",
628 chan->stats.runt_transmit_buff);
629 dev_info(dev, "\tstats empty_dequeue: %d\n",
630 chan->stats.empty_dequeue);
631 dev_info(dev, "\tstats busy_dequeue: %d\n",
632 chan->stats.busy_dequeue);
633 dev_info(dev, "\tstats good_dequeue: %d\n",
634 chan->stats.good_dequeue);
635 dev_info(dev, "\tstats requeue: %d\n",
636 chan->stats.requeue);
637 dev_info(dev, "\tstats teardown_dequeue: %d\n",
638 chan->stats.teardown_dequeue);
640 spin_unlock_irqrestore(&chan->lock, flags);
644 static void __cpdma_chan_submit(struct cpdma_chan *chan,
645 struct cpdma_desc __iomem *desc)
647 struct cpdma_ctlr *ctlr = chan->ctlr;
648 struct cpdma_desc __iomem *prev = chan->tail;
649 struct cpdma_desc_pool *pool = ctlr->pool;
653 desc_dma = desc_phys(pool, desc);
655 /* simple case - idle channel */
657 chan->stats.head_enqueue++;
660 if (chan->state == CPDMA_STATE_ACTIVE)
661 chan_write(chan, hdp, desc_dma);
665 /* first chain the descriptor at the tail of the list */
666 desc_write(prev, hw_next, desc_dma);
668 chan->stats.tail_enqueue++;
670 /* next check if EOQ has been triggered already */
671 mode = desc_read(prev, hw_mode);
672 if (((mode & (CPDMA_DESC_EOQ | CPDMA_DESC_OWNER)) == CPDMA_DESC_EOQ) &&
673 (chan->state == CPDMA_STATE_ACTIVE)) {
674 desc_write(prev, hw_mode, mode & ~CPDMA_DESC_EOQ);
675 chan_write(chan, hdp, desc_dma);
676 chan->stats.misqueued++;
680 int cpdma_chan_submit(struct cpdma_chan *chan, void *token, void *data,
681 int len, int directed)
683 struct cpdma_ctlr *ctlr = chan->ctlr;
684 struct cpdma_desc __iomem *desc;
690 spin_lock_irqsave(&chan->lock, flags);
692 if (chan->state == CPDMA_STATE_TEARDOWN) {
697 desc = cpdma_desc_alloc(ctlr->pool, 1, is_rx_chan(chan));
699 chan->stats.desc_alloc_fail++;
704 if (len < ctlr->params.min_packet_size) {
705 len = ctlr->params.min_packet_size;
706 chan->stats.runt_transmit_buff++;
709 buffer = dma_map_single(ctlr->dev, data, len, chan->dir);
710 ret = dma_mapping_error(ctlr->dev, buffer);
712 cpdma_desc_free(ctlr->pool, desc, 1);
717 mode = CPDMA_DESC_OWNER | CPDMA_DESC_SOP | CPDMA_DESC_EOP;
718 cpdma_desc_to_port(chan, mode, directed);
720 desc_write(desc, hw_next, 0);
721 desc_write(desc, hw_buffer, buffer);
722 desc_write(desc, hw_len, len);
723 desc_write(desc, hw_mode, mode | len);
724 desc_write(desc, sw_token, token);
725 desc_write(desc, sw_buffer, buffer);
726 desc_write(desc, sw_len, len);
728 __cpdma_chan_submit(chan, desc);
730 if (chan->state == CPDMA_STATE_ACTIVE && chan->rxfree)
731 chan_write(chan, rxfree, 1);
736 spin_unlock_irqrestore(&chan->lock, flags);
739 EXPORT_SYMBOL_GPL(cpdma_chan_submit);
741 bool cpdma_check_free_tx_desc(struct cpdma_chan *chan)
746 struct cpdma_ctlr *ctlr = chan->ctlr;
747 struct cpdma_desc_pool *pool = ctlr->pool;
749 spin_lock_irqsave(&pool->lock, flags);
751 index = bitmap_find_next_zero_area(pool->bitmap,
752 pool->num_desc, pool->num_desc/2, 1, 0);
754 if (index < pool->num_desc)
759 spin_unlock_irqrestore(&pool->lock, flags);
762 EXPORT_SYMBOL_GPL(cpdma_check_free_tx_desc);
764 static void __cpdma_chan_free(struct cpdma_chan *chan,
765 struct cpdma_desc __iomem *desc,
766 int outlen, int status)
768 struct cpdma_ctlr *ctlr = chan->ctlr;
769 struct cpdma_desc_pool *pool = ctlr->pool;
774 token = (void *)desc_read(desc, sw_token);
775 buff_dma = desc_read(desc, sw_buffer);
776 origlen = desc_read(desc, sw_len);
778 dma_unmap_single(ctlr->dev, buff_dma, origlen, chan->dir);
779 cpdma_desc_free(pool, desc, 1);
780 (*chan->handler)(token, outlen, status);
783 static int __cpdma_chan_process(struct cpdma_chan *chan)
785 struct cpdma_ctlr *ctlr = chan->ctlr;
786 struct cpdma_desc __iomem *desc;
789 struct cpdma_desc_pool *pool = ctlr->pool;
793 spin_lock_irqsave(&chan->lock, flags);
797 chan->stats.empty_dequeue++;
801 desc_dma = desc_phys(pool, desc);
803 status = __raw_readl(&desc->hw_mode);
804 outlen = status & 0x7ff;
805 if (status & CPDMA_DESC_OWNER) {
806 chan->stats.busy_dequeue++;
811 if (status & CPDMA_DESC_PASS_CRC)
812 outlen -= CPDMA_DESC_CRC_LEN;
814 status = status & (CPDMA_DESC_EOQ | CPDMA_DESC_TD_COMPLETE |
815 CPDMA_DESC_PORT_MASK);
817 chan->head = desc_from_phys(pool, desc_read(desc, hw_next));
818 chan_write(chan, cp, desc_dma);
820 chan->stats.good_dequeue++;
822 if (status & CPDMA_DESC_EOQ) {
823 chan->stats.requeue++;
824 chan_write(chan, hdp, desc_phys(pool, chan->head));
827 spin_unlock_irqrestore(&chan->lock, flags);
828 if (unlikely(status & CPDMA_DESC_TD_COMPLETE))
833 __cpdma_chan_free(chan, desc, outlen, cb_status);
837 spin_unlock_irqrestore(&chan->lock, flags);
841 int cpdma_chan_process(struct cpdma_chan *chan, int quota)
843 int used = 0, ret = 0;
845 if (chan->state != CPDMA_STATE_ACTIVE)
848 while (used < quota) {
849 ret = __cpdma_chan_process(chan);
856 EXPORT_SYMBOL_GPL(cpdma_chan_process);
858 int cpdma_chan_start(struct cpdma_chan *chan)
860 struct cpdma_ctlr *ctlr = chan->ctlr;
861 struct cpdma_desc_pool *pool = ctlr->pool;
864 spin_lock_irqsave(&chan->lock, flags);
865 if (chan->state != CPDMA_STATE_IDLE) {
866 spin_unlock_irqrestore(&chan->lock, flags);
869 if (ctlr->state != CPDMA_STATE_ACTIVE) {
870 spin_unlock_irqrestore(&chan->lock, flags);
873 dma_reg_write(ctlr, chan->int_set, chan->mask);
874 chan->state = CPDMA_STATE_ACTIVE;
876 chan_write(chan, hdp, desc_phys(pool, chan->head));
878 chan_write(chan, rxfree, chan->count);
881 spin_unlock_irqrestore(&chan->lock, flags);
884 EXPORT_SYMBOL_GPL(cpdma_chan_start);
886 int cpdma_chan_stop(struct cpdma_chan *chan)
888 struct cpdma_ctlr *ctlr = chan->ctlr;
889 struct cpdma_desc_pool *pool = ctlr->pool;
894 spin_lock_irqsave(&chan->lock, flags);
895 if (chan->state != CPDMA_STATE_ACTIVE) {
896 spin_unlock_irqrestore(&chan->lock, flags);
900 chan->state = CPDMA_STATE_TEARDOWN;
901 dma_reg_write(ctlr, chan->int_clear, chan->mask);
903 /* trigger teardown */
904 dma_reg_write(ctlr, chan->td, chan_linear(chan));
906 /* wait for teardown complete */
907 timeout = 100 * 100; /* 100 ms */
909 u32 cp = chan_read(chan, cp);
910 if ((cp & CPDMA_TEARDOWN_VALUE) == CPDMA_TEARDOWN_VALUE)
916 chan_write(chan, cp, CPDMA_TEARDOWN_VALUE);
918 /* handle completed packets */
919 spin_unlock_irqrestore(&chan->lock, flags);
921 ret = __cpdma_chan_process(chan);
924 } while ((ret & CPDMA_DESC_TD_COMPLETE) == 0);
925 spin_lock_irqsave(&chan->lock, flags);
927 /* remaining packets haven't been tx/rx'ed, clean them up */
929 struct cpdma_desc __iomem *desc = chan->head;
932 next_dma = desc_read(desc, hw_next);
933 chan->head = desc_from_phys(pool, next_dma);
935 chan->stats.teardown_dequeue++;
937 /* issue callback without locks held */
938 spin_unlock_irqrestore(&chan->lock, flags);
939 __cpdma_chan_free(chan, desc, 0, -ENOSYS);
940 spin_lock_irqsave(&chan->lock, flags);
943 chan->state = CPDMA_STATE_IDLE;
944 spin_unlock_irqrestore(&chan->lock, flags);
947 EXPORT_SYMBOL_GPL(cpdma_chan_stop);
949 int cpdma_chan_int_ctrl(struct cpdma_chan *chan, bool enable)
953 spin_lock_irqsave(&chan->lock, flags);
954 if (chan->state != CPDMA_STATE_ACTIVE) {
955 spin_unlock_irqrestore(&chan->lock, flags);
959 dma_reg_write(chan->ctlr, enable ? chan->int_set : chan->int_clear,
961 spin_unlock_irqrestore(&chan->lock, flags);
966 struct cpdma_control_info {
970 #define ACCESS_RO BIT(0)
971 #define ACCESS_WO BIT(1)
972 #define ACCESS_RW (ACCESS_RO | ACCESS_WO)
975 struct cpdma_control_info controls[] = {
976 [CPDMA_CMD_IDLE] = {CPDMA_DMACONTROL, 3, 1, ACCESS_WO},
977 [CPDMA_COPY_ERROR_FRAMES] = {CPDMA_DMACONTROL, 4, 1, ACCESS_RW},
978 [CPDMA_RX_OFF_LEN_UPDATE] = {CPDMA_DMACONTROL, 2, 1, ACCESS_RW},
979 [CPDMA_RX_OWNERSHIP_FLIP] = {CPDMA_DMACONTROL, 1, 1, ACCESS_RW},
980 [CPDMA_TX_PRIO_FIXED] = {CPDMA_DMACONTROL, 0, 1, ACCESS_RW},
981 [CPDMA_STAT_IDLE] = {CPDMA_DMASTATUS, 31, 1, ACCESS_RO},
982 [CPDMA_STAT_TX_ERR_CODE] = {CPDMA_DMASTATUS, 20, 0xf, ACCESS_RW},
983 [CPDMA_STAT_TX_ERR_CHAN] = {CPDMA_DMASTATUS, 16, 0x7, ACCESS_RW},
984 [CPDMA_STAT_RX_ERR_CODE] = {CPDMA_DMASTATUS, 12, 0xf, ACCESS_RW},
985 [CPDMA_STAT_RX_ERR_CHAN] = {CPDMA_DMASTATUS, 8, 0x7, ACCESS_RW},
986 [CPDMA_RX_BUFFER_OFFSET] = {CPDMA_RXBUFFOFS, 0, 0xffff, ACCESS_RW},
989 int cpdma_control_get(struct cpdma_ctlr *ctlr, int control)
992 struct cpdma_control_info *info = &controls[control];
995 spin_lock_irqsave(&ctlr->lock, flags);
998 if (!ctlr->params.has_ext_regs)
1002 if (ctlr->state != CPDMA_STATE_ACTIVE)
1006 if (control < 0 || control >= ARRAY_SIZE(controls))
1010 if ((info->access & ACCESS_RO) != ACCESS_RO)
1013 ret = (dma_reg_read(ctlr, info->reg) >> info->shift) & info->mask;
1016 spin_unlock_irqrestore(&ctlr->lock, flags);
1020 int cpdma_control_set(struct cpdma_ctlr *ctlr, int control, int value)
1022 unsigned long flags;
1023 struct cpdma_control_info *info = &controls[control];
1027 spin_lock_irqsave(&ctlr->lock, flags);
1030 if (!ctlr->params.has_ext_regs)
1034 if (ctlr->state != CPDMA_STATE_ACTIVE)
1038 if (control < 0 || control >= ARRAY_SIZE(controls))
1042 if ((info->access & ACCESS_WO) != ACCESS_WO)
1045 val = dma_reg_read(ctlr, info->reg);
1046 val &= ~(info->mask << info->shift);
1047 val |= (value & info->mask) << info->shift;
1048 dma_reg_write(ctlr, info->reg, val);
1052 spin_unlock_irqrestore(&ctlr->lock, flags);
1055 EXPORT_SYMBOL_GPL(cpdma_control_set);
1057 MODULE_LICENSE("GPL");