1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2013 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
32 #include "ixgbe_common.h"
33 #include "ixgbe_phy.h"
35 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
36 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
37 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
38 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
39 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
40 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
41 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
42 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
43 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
44 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
45 static bool ixgbe_get_i2c_data(u32 *i2cctl);
46 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
47 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
48 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
49 static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw);
52 * ixgbe_identify_phy_generic - Get physical layer module
53 * @hw: pointer to hardware structure
55 * Determines the physical layer module found on the current adapter.
57 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
59 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
63 if (hw->phy.type == ixgbe_phy_unknown) {
64 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
65 hw->phy.mdio.prtad = phy_addr;
66 if (mdio45_probe(&hw->phy.mdio, phy_addr) == 0) {
69 ixgbe_get_phy_type_from_id(hw->phy.id);
71 if (hw->phy.type == ixgbe_phy_unknown) {
72 hw->phy.ops.read_reg(hw,
77 (MDIO_PMA_EXTABLE_10GBT |
78 MDIO_PMA_EXTABLE_1000BT))
90 /* clear value if nothing found */
92 hw->phy.mdio.prtad = 0;
101 * ixgbe_get_phy_id - Get the phy type
102 * @hw: pointer to hardware structure
105 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
111 status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD,
115 hw->phy.id = (u32)(phy_id_high << 16);
116 status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD,
118 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
119 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
125 * ixgbe_get_phy_type_from_id - Get the phy type
126 * @hw: pointer to hardware structure
129 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
131 enum ixgbe_phy_type phy_type;
135 phy_type = ixgbe_phy_tn;
138 phy_type = ixgbe_phy_aq;
141 phy_type = ixgbe_phy_qt;
144 phy_type = ixgbe_phy_nl;
147 phy_type = ixgbe_phy_unknown;
155 * ixgbe_reset_phy_generic - Performs a PHY reset
156 * @hw: pointer to hardware structure
158 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
164 if (hw->phy.type == ixgbe_phy_unknown)
165 status = ixgbe_identify_phy_generic(hw);
167 if (status != 0 || hw->phy.type == ixgbe_phy_none)
170 /* Don't reset PHY if it's shut down due to overtemp. */
171 if (!hw->phy.reset_if_overtemp &&
172 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
176 * Perform soft PHY reset to the PHY_XS.
177 * This will cause a soft reset to the PHY
179 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
184 * Poll for reset bit to self-clear indicating reset is complete.
185 * Some PHYs could take up to 3 seconds to complete and need about
186 * 1.7 usec delay after the reset is complete.
188 for (i = 0; i < 30; i++) {
190 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
191 MDIO_MMD_PHYXS, &ctrl);
192 if (!(ctrl & MDIO_CTRL1_RESET)) {
198 if (ctrl & MDIO_CTRL1_RESET) {
199 status = IXGBE_ERR_RESET_FAILED;
200 hw_dbg(hw, "PHY reset polling failed to complete.\n");
208 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
210 * @hw: pointer to hardware structure
211 * @reg_addr: 32 bit address of PHY register to read
212 * @phy_data: Pointer to read data from PHY register
214 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
217 u32 i, data, command;
219 /* Setup and write the address cycle command */
220 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
221 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
222 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
223 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
225 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
227 /* Check every 10 usec to see if the address cycle completed.
228 * The MDI Command bit will clear when the operation is
231 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
234 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
235 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
240 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
241 hw_dbg(hw, "PHY address command did not complete.\n");
242 return IXGBE_ERR_PHY;
245 /* Address cycle complete, setup and write the read
248 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
249 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
250 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
251 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
253 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
255 /* Check every 10 usec to see if the address cycle
256 * completed. The MDI Command bit will clear when the
257 * operation is complete
259 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
262 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
263 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
267 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
268 hw_dbg(hw, "PHY read command didn't complete\n");
269 return IXGBE_ERR_PHY;
272 /* Read operation is complete. Get the data
275 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
276 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
277 *phy_data = (u16)(data);
283 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
284 * using the SWFW lock - this function is needed in most cases
285 * @hw: pointer to hardware structure
286 * @reg_addr: 32 bit address of PHY register to read
287 * @phy_data: Pointer to read data from PHY register
289 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
290 u32 device_type, u16 *phy_data)
295 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
296 gssr = IXGBE_GSSR_PHY1_SM;
298 gssr = IXGBE_GSSR_PHY0_SM;
300 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
301 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type,
303 hw->mac.ops.release_swfw_sync(hw, gssr);
305 status = IXGBE_ERR_SWFW_SYNC;
312 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
314 * @hw: pointer to hardware structure
315 * @reg_addr: 32 bit PHY register to write
316 * @device_type: 5 bit device type
317 * @phy_data: Data to write to the PHY register
319 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
320 u32 device_type, u16 phy_data)
324 /* Put the data in the MDI single read and write data register*/
325 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
327 /* Setup and write the address cycle command */
328 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
329 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
330 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
331 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
333 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
336 * Check every 10 usec to see if the address cycle completed.
337 * The MDI Command bit will clear when the operation is
340 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
343 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
344 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
348 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
349 hw_dbg(hw, "PHY address cmd didn't complete\n");
350 return IXGBE_ERR_PHY;
354 * Address cycle complete, setup and write the write
357 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
358 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
359 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
360 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
362 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
364 /* Check every 10 usec to see if the address cycle
365 * completed. The MDI Command bit will clear when the
366 * operation is complete
368 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
371 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
372 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
376 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
377 hw_dbg(hw, "PHY write cmd didn't complete\n");
378 return IXGBE_ERR_PHY;
385 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
386 * using SWFW lock- this function is needed in most cases
387 * @hw: pointer to hardware structure
388 * @reg_addr: 32 bit PHY register to write
389 * @device_type: 5 bit device type
390 * @phy_data: Data to write to the PHY register
392 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
393 u32 device_type, u16 phy_data)
398 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
399 gssr = IXGBE_GSSR_PHY1_SM;
401 gssr = IXGBE_GSSR_PHY0_SM;
403 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
404 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
406 hw->mac.ops.release_swfw_sync(hw, gssr);
408 status = IXGBE_ERR_SWFW_SYNC;
415 * ixgbe_setup_phy_link_generic - Set and restart autoneg
416 * @hw: pointer to hardware structure
418 * Restart autonegotiation and PHY and waits for completion.
420 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
424 u32 max_time_out = 10;
425 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
426 bool autoneg = false;
427 ixgbe_link_speed speed;
429 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
431 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
432 /* Set or unset auto-negotiation 10G advertisement */
433 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
437 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
438 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
439 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
441 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL,
446 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
447 /* Set or unset auto-negotiation 1G advertisement */
448 hw->phy.ops.read_reg(hw,
449 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
453 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
454 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
455 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
457 hw->phy.ops.write_reg(hw,
458 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
463 if (speed & IXGBE_LINK_SPEED_100_FULL) {
464 /* Set or unset auto-negotiation 100M advertisement */
465 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
469 autoneg_reg &= ~(ADVERTISE_100FULL |
471 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
472 autoneg_reg |= ADVERTISE_100FULL;
474 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
479 /* Restart PHY autonegotiation and wait for completion */
480 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
481 MDIO_MMD_AN, &autoneg_reg);
483 autoneg_reg |= MDIO_AN_CTRL1_RESTART;
485 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
486 MDIO_MMD_AN, autoneg_reg);
488 /* Wait for autonegotiation to finish */
489 for (time_out = 0; time_out < max_time_out; time_out++) {
491 /* Restart PHY autonegotiation and wait for completion */
492 status = hw->phy.ops.read_reg(hw, MDIO_STAT1,
496 autoneg_reg &= MDIO_AN_STAT1_COMPLETE;
497 if (autoneg_reg == MDIO_AN_STAT1_COMPLETE) {
502 if (time_out == max_time_out) {
503 status = IXGBE_ERR_LINK_SETUP;
504 hw_dbg(hw, "ixgbe_setup_phy_link_generic: time out");
511 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
512 * @hw: pointer to hardware structure
513 * @speed: new link speed
515 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
516 ixgbe_link_speed speed,
517 bool autoneg_wait_to_complete)
521 * Clear autoneg_advertised and set new values based on input link
524 hw->phy.autoneg_advertised = 0;
526 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
527 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
529 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
530 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
532 if (speed & IXGBE_LINK_SPEED_100_FULL)
533 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
535 /* Setup link based on the new speed settings */
536 hw->phy.ops.setup_link(hw);
542 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
543 * @hw: pointer to hardware structure
544 * @speed: pointer to link speed
545 * @autoneg: boolean auto-negotiation value
547 * Determines the link capabilities by reading the AUTOC register.
549 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
550 ixgbe_link_speed *speed,
553 s32 status = IXGBE_ERR_LINK_SETUP;
559 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
563 if (speed_ability & MDIO_SPEED_10G)
564 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
565 if (speed_ability & MDIO_PMA_SPEED_1000)
566 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
567 if (speed_ability & MDIO_PMA_SPEED_100)
568 *speed |= IXGBE_LINK_SPEED_100_FULL;
575 * ixgbe_check_phy_link_tnx - Determine link and speed status
576 * @hw: pointer to hardware structure
578 * Reads the VS1 register to determine if link is up and the current speed for
581 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
586 u32 max_time_out = 10;
591 /* Initialize speed and link to default case */
593 *speed = IXGBE_LINK_SPEED_10GB_FULL;
596 * Check current speed and link status of the PHY register.
597 * This is a vendor specific register and may have to
598 * be changed for other copper PHYs.
600 for (time_out = 0; time_out < max_time_out; time_out++) {
602 status = hw->phy.ops.read_reg(hw,
606 phy_link = phy_data &
607 IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
608 phy_speed = phy_data &
609 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
610 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
613 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
614 *speed = IXGBE_LINK_SPEED_1GB_FULL;
623 * ixgbe_setup_phy_link_tnx - Set and restart autoneg
624 * @hw: pointer to hardware structure
626 * Restart autonegotiation and PHY and waits for completion.
628 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
632 u32 max_time_out = 10;
633 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
634 bool autoneg = false;
635 ixgbe_link_speed speed;
637 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
639 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
640 /* Set or unset auto-negotiation 10G advertisement */
641 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
645 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
646 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
647 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
649 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL,
654 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
655 /* Set or unset auto-negotiation 1G advertisement */
656 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
660 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
661 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
662 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
664 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
669 if (speed & IXGBE_LINK_SPEED_100_FULL) {
670 /* Set or unset auto-negotiation 100M advertisement */
671 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
675 autoneg_reg &= ~(ADVERTISE_100FULL |
677 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
678 autoneg_reg |= ADVERTISE_100FULL;
680 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
685 /* Restart PHY autonegotiation and wait for completion */
686 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
687 MDIO_MMD_AN, &autoneg_reg);
689 autoneg_reg |= MDIO_AN_CTRL1_RESTART;
691 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
692 MDIO_MMD_AN, autoneg_reg);
694 /* Wait for autonegotiation to finish */
695 for (time_out = 0; time_out < max_time_out; time_out++) {
697 /* Restart PHY autonegotiation and wait for completion */
698 status = hw->phy.ops.read_reg(hw, MDIO_STAT1,
702 autoneg_reg &= MDIO_AN_STAT1_COMPLETE;
703 if (autoneg_reg == MDIO_AN_STAT1_COMPLETE)
707 if (time_out == max_time_out) {
708 status = IXGBE_ERR_LINK_SETUP;
709 hw_dbg(hw, "ixgbe_setup_phy_link_tnx: time out");
716 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
717 * @hw: pointer to hardware structure
718 * @firmware_version: pointer to the PHY Firmware Version
720 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
721 u16 *firmware_version)
725 status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
733 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
734 * @hw: pointer to hardware structure
735 * @firmware_version: pointer to the PHY Firmware Version
737 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
738 u16 *firmware_version)
742 status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
750 * ixgbe_reset_phy_nl - Performs a PHY reset
751 * @hw: pointer to hardware structure
753 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
755 u16 phy_offset, control, eword, edata, block_crc;
756 bool end_data = false;
757 u16 list_offset, data_offset;
762 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data);
764 /* reset the PHY and poll for completion */
765 hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
766 (phy_data | MDIO_CTRL1_RESET));
768 for (i = 0; i < 100; i++) {
769 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
771 if ((phy_data & MDIO_CTRL1_RESET) == 0)
773 usleep_range(10000, 20000);
776 if ((phy_data & MDIO_CTRL1_RESET) != 0) {
777 hw_dbg(hw, "PHY reset did not complete.\n");
778 ret_val = IXGBE_ERR_PHY;
782 /* Get init offsets */
783 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
788 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
792 * Read control word from PHY init contents offset
794 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
797 control = (eword & IXGBE_CONTROL_MASK_NL) >>
798 IXGBE_CONTROL_SHIFT_NL;
799 edata = eword & IXGBE_DATA_MASK_NL;
803 hw_dbg(hw, "DELAY: %d MS\n", edata);
804 usleep_range(edata * 1000, edata * 2000);
807 hw_dbg(hw, "DATA:\n");
809 ret_val = hw->eeprom.ops.read(hw, data_offset++,
813 for (i = 0; i < edata; i++) {
814 ret_val = hw->eeprom.ops.read(hw, data_offset,
818 hw->phy.ops.write_reg(hw, phy_offset,
819 MDIO_MMD_PMAPMD, eword);
820 hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword,
826 case IXGBE_CONTROL_NL:
828 hw_dbg(hw, "CONTROL:\n");
829 if (edata == IXGBE_CONTROL_EOL_NL) {
832 } else if (edata == IXGBE_CONTROL_SOL_NL) {
835 hw_dbg(hw, "Bad control value\n");
836 ret_val = IXGBE_ERR_PHY;
841 hw_dbg(hw, "Bad control type\n");
842 ret_val = IXGBE_ERR_PHY;
851 hw_err(hw, "eeprom read at offset %d failed\n", data_offset);
852 return IXGBE_ERR_PHY;
856 * ixgbe_identify_module_generic - Identifies module type
857 * @hw: pointer to hardware structure
859 * Determines HW type and calls appropriate function.
861 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
863 s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
865 switch (hw->mac.ops.get_media_type(hw)) {
866 case ixgbe_media_type_fiber:
867 status = ixgbe_identify_sfp_module_generic(hw);
869 case ixgbe_media_type_fiber_qsfp:
870 status = ixgbe_identify_qsfp_module_generic(hw);
873 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
874 status = IXGBE_ERR_SFP_NOT_PRESENT;
882 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
883 * @hw: pointer to hardware structure
885 * Searches for and identifies the SFP module and assigns appropriate PHY type.
887 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
889 struct ixgbe_adapter *adapter = hw->back;
890 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
892 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
894 u8 comp_codes_1g = 0;
895 u8 comp_codes_10g = 0;
896 u8 oui_bytes[3] = {0, 0, 0};
901 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
902 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
903 status = IXGBE_ERR_SFP_NOT_PRESENT;
907 status = hw->phy.ops.read_i2c_eeprom(hw,
908 IXGBE_SFF_IDENTIFIER,
912 goto err_read_i2c_eeprom;
914 /* LAN ID is needed for sfp_type determination */
915 hw->mac.ops.set_lan_id(hw);
917 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
918 hw->phy.type = ixgbe_phy_sfp_unsupported;
919 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
921 status = hw->phy.ops.read_i2c_eeprom(hw,
922 IXGBE_SFF_1GBE_COMP_CODES,
926 goto err_read_i2c_eeprom;
928 status = hw->phy.ops.read_i2c_eeprom(hw,
929 IXGBE_SFF_10GBE_COMP_CODES,
933 goto err_read_i2c_eeprom;
934 status = hw->phy.ops.read_i2c_eeprom(hw,
935 IXGBE_SFF_CABLE_TECHNOLOGY,
939 goto err_read_i2c_eeprom;
946 * 3 SFP_DA_CORE0 - 82599-specific
947 * 4 SFP_DA_CORE1 - 82599-specific
948 * 5 SFP_SR/LR_CORE0 - 82599-specific
949 * 6 SFP_SR/LR_CORE1 - 82599-specific
950 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
951 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
952 * 9 SFP_1g_cu_CORE0 - 82599-specific
953 * 10 SFP_1g_cu_CORE1 - 82599-specific
954 * 11 SFP_1g_sx_CORE0 - 82599-specific
955 * 12 SFP_1g_sx_CORE1 - 82599-specific
957 if (hw->mac.type == ixgbe_mac_82598EB) {
958 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
959 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
960 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
961 hw->phy.sfp_type = ixgbe_sfp_type_sr;
962 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
963 hw->phy.sfp_type = ixgbe_sfp_type_lr;
965 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
966 } else if (hw->mac.type == ixgbe_mac_82599EB) {
967 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
968 if (hw->bus.lan_id == 0)
970 ixgbe_sfp_type_da_cu_core0;
973 ixgbe_sfp_type_da_cu_core1;
974 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
975 hw->phy.ops.read_i2c_eeprom(
976 hw, IXGBE_SFF_CABLE_SPEC_COMP,
979 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
980 if (hw->bus.lan_id == 0)
982 ixgbe_sfp_type_da_act_lmt_core0;
985 ixgbe_sfp_type_da_act_lmt_core1;
988 ixgbe_sfp_type_unknown;
990 } else if (comp_codes_10g &
991 (IXGBE_SFF_10GBASESR_CAPABLE |
992 IXGBE_SFF_10GBASELR_CAPABLE)) {
993 if (hw->bus.lan_id == 0)
995 ixgbe_sfp_type_srlr_core0;
998 ixgbe_sfp_type_srlr_core1;
999 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1000 if (hw->bus.lan_id == 0)
1002 ixgbe_sfp_type_1g_cu_core0;
1005 ixgbe_sfp_type_1g_cu_core1;
1006 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1007 if (hw->bus.lan_id == 0)
1009 ixgbe_sfp_type_1g_sx_core0;
1012 ixgbe_sfp_type_1g_sx_core1;
1013 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1014 if (hw->bus.lan_id == 0)
1016 ixgbe_sfp_type_1g_lx_core0;
1019 ixgbe_sfp_type_1g_lx_core1;
1021 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1025 if (hw->phy.sfp_type != stored_sfp_type)
1026 hw->phy.sfp_setup_needed = true;
1028 /* Determine if the SFP+ PHY is dual speed or not. */
1029 hw->phy.multispeed_fiber = false;
1030 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1031 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1032 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1033 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1034 hw->phy.multispeed_fiber = true;
1036 /* Determine PHY vendor */
1037 if (hw->phy.type != ixgbe_phy_nl) {
1038 hw->phy.id = identifier;
1039 status = hw->phy.ops.read_i2c_eeprom(hw,
1040 IXGBE_SFF_VENDOR_OUI_BYTE0,
1044 goto err_read_i2c_eeprom;
1046 status = hw->phy.ops.read_i2c_eeprom(hw,
1047 IXGBE_SFF_VENDOR_OUI_BYTE1,
1051 goto err_read_i2c_eeprom;
1053 status = hw->phy.ops.read_i2c_eeprom(hw,
1054 IXGBE_SFF_VENDOR_OUI_BYTE2,
1058 goto err_read_i2c_eeprom;
1061 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1062 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1063 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1065 switch (vendor_oui) {
1066 case IXGBE_SFF_VENDOR_OUI_TYCO:
1067 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1069 ixgbe_phy_sfp_passive_tyco;
1071 case IXGBE_SFF_VENDOR_OUI_FTL:
1072 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1073 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1075 hw->phy.type = ixgbe_phy_sfp_ftl;
1077 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1078 hw->phy.type = ixgbe_phy_sfp_avago;
1080 case IXGBE_SFF_VENDOR_OUI_INTEL:
1081 hw->phy.type = ixgbe_phy_sfp_intel;
1084 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1086 ixgbe_phy_sfp_passive_unknown;
1087 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1089 ixgbe_phy_sfp_active_unknown;
1091 hw->phy.type = ixgbe_phy_sfp_unknown;
1096 /* Allow any DA cable vendor */
1097 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1098 IXGBE_SFF_DA_ACTIVE_CABLE)) {
1103 /* Verify supported 1G SFP modules */
1104 if (comp_codes_10g == 0 &&
1105 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1106 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1107 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1108 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1109 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1110 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1111 hw->phy.type = ixgbe_phy_sfp_unsupported;
1112 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1116 /* Anything else 82598-based is supported */
1117 if (hw->mac.type == ixgbe_mac_82598EB) {
1122 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
1123 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1124 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1125 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1126 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1127 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1128 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1129 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1130 /* Make sure we're a supported PHY type */
1131 if (hw->phy.type == ixgbe_phy_sfp_intel) {
1134 if (hw->allow_unsupported_sfp) {
1135 e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.");
1139 "SFP+ module not supported\n");
1141 ixgbe_phy_sfp_unsupported;
1142 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1153 err_read_i2c_eeprom:
1154 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1155 if (hw->phy.type != ixgbe_phy_nl) {
1157 hw->phy.type = ixgbe_phy_unknown;
1159 return IXGBE_ERR_SFP_NOT_PRESENT;
1163 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1164 * @hw: pointer to hardware structure
1166 * Searches for and identifies the QSFP module and assigns appropriate PHY type
1168 static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1170 struct ixgbe_adapter *adapter = hw->back;
1171 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1173 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1175 u8 comp_codes_1g = 0;
1176 u8 comp_codes_10g = 0;
1177 u8 oui_bytes[3] = {0, 0, 0};
1178 u16 enforce_sfp = 0;
1180 u8 cable_length = 0;
1182 bool active_cable = false;
1184 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1185 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1186 status = IXGBE_ERR_SFP_NOT_PRESENT;
1190 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1194 goto err_read_i2c_eeprom;
1196 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1197 hw->phy.type = ixgbe_phy_sfp_unsupported;
1198 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1202 hw->phy.id = identifier;
1204 /* LAN ID is needed for sfp_type determination */
1205 hw->mac.ops.set_lan_id(hw);
1207 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1211 goto err_read_i2c_eeprom;
1213 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1217 goto err_read_i2c_eeprom;
1219 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1220 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1221 if (hw->bus.lan_id == 0)
1222 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1224 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1225 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1226 IXGBE_SFF_10GBASELR_CAPABLE)) {
1227 if (hw->bus.lan_id == 0)
1228 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1230 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1232 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1233 active_cable = true;
1235 if (!active_cable) {
1236 /* check for active DA cables that pre-date
1239 hw->phy.ops.read_i2c_eeprom(hw,
1240 IXGBE_SFF_QSFP_CONNECTOR,
1243 hw->phy.ops.read_i2c_eeprom(hw,
1244 IXGBE_SFF_QSFP_CABLE_LENGTH,
1247 hw->phy.ops.read_i2c_eeprom(hw,
1248 IXGBE_SFF_QSFP_DEVICE_TECH,
1252 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1253 (cable_length > 0) &&
1254 ((device_tech >> 4) ==
1255 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1256 active_cable = true;
1260 hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1261 if (hw->bus.lan_id == 0)
1263 ixgbe_sfp_type_da_act_lmt_core0;
1266 ixgbe_sfp_type_da_act_lmt_core1;
1268 /* unsupported module type */
1269 hw->phy.type = ixgbe_phy_sfp_unsupported;
1270 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1275 if (hw->phy.sfp_type != stored_sfp_type)
1276 hw->phy.sfp_setup_needed = true;
1278 /* Determine if the QSFP+ PHY is dual speed or not. */
1279 hw->phy.multispeed_fiber = false;
1280 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1281 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1282 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1283 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1284 hw->phy.multispeed_fiber = true;
1286 /* Determine PHY vendor for optical modules */
1287 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1288 IXGBE_SFF_10GBASELR_CAPABLE)) {
1289 status = hw->phy.ops.read_i2c_eeprom(hw,
1290 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1294 goto err_read_i2c_eeprom;
1296 status = hw->phy.ops.read_i2c_eeprom(hw,
1297 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1301 goto err_read_i2c_eeprom;
1303 status = hw->phy.ops.read_i2c_eeprom(hw,
1304 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1308 goto err_read_i2c_eeprom;
1311 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1312 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1313 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1315 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1316 hw->phy.type = ixgbe_phy_qsfp_intel;
1318 hw->phy.type = ixgbe_phy_qsfp_unknown;
1320 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
1321 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1322 /* Make sure we're a supported PHY type */
1323 if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1326 if (hw->allow_unsupported_sfp == true) {
1327 e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1331 "QSFP module not supported\n");
1333 ixgbe_phy_sfp_unsupported;
1334 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1345 err_read_i2c_eeprom:
1346 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1348 hw->phy.type = ixgbe_phy_unknown;
1350 return IXGBE_ERR_SFP_NOT_PRESENT;
1354 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1355 * @hw: pointer to hardware structure
1356 * @list_offset: offset to the SFP ID list
1357 * @data_offset: offset to the SFP data block
1359 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1360 * so it returns the offsets to the phy init sequence block.
1362 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1367 u16 sfp_type = hw->phy.sfp_type;
1369 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1370 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1372 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1373 return IXGBE_ERR_SFP_NOT_PRESENT;
1375 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1376 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1377 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1380 * Limiting active cables and 1G Phys must be initialized as
1383 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1384 sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1385 sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1386 sfp_type == ixgbe_sfp_type_1g_sx_core0)
1387 sfp_type = ixgbe_sfp_type_srlr_core0;
1388 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1389 sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1390 sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1391 sfp_type == ixgbe_sfp_type_1g_sx_core1)
1392 sfp_type = ixgbe_sfp_type_srlr_core1;
1394 /* Read offset to PHY init contents */
1395 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1396 hw_err(hw, "eeprom read at %d failed\n",
1397 IXGBE_PHY_INIT_OFFSET_NL);
1398 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1401 if ((!*list_offset) || (*list_offset == 0xFFFF))
1402 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1404 /* Shift offset to first ID word */
1408 * Find the matching SFP ID in the EEPROM
1409 * and program the init sequence
1411 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1414 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1415 if (sfp_id == sfp_type) {
1417 if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1419 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1420 hw_dbg(hw, "SFP+ module not supported\n");
1421 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1426 (*list_offset) += 2;
1427 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1432 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1433 hw_dbg(hw, "No matching SFP+ module found\n");
1434 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1440 hw_err(hw, "eeprom read at offset %d failed\n", *list_offset);
1441 return IXGBE_ERR_PHY;
1445 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1446 * @hw: pointer to hardware structure
1447 * @byte_offset: EEPROM byte offset to read
1448 * @eeprom_data: value read
1450 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1452 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1455 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1456 IXGBE_I2C_EEPROM_DEV_ADDR,
1461 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1462 * @hw: pointer to hardware structure
1463 * @byte_offset: byte offset at address 0xA2
1464 * @eeprom_data: value read
1466 * Performs byte read operation to SFP module's SFF-8472 data over I2C
1468 s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1471 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1472 IXGBE_I2C_EEPROM_DEV_ADDR2,
1477 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1478 * @hw: pointer to hardware structure
1479 * @byte_offset: EEPROM byte offset to write
1480 * @eeprom_data: value to write
1482 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1484 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1487 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1488 IXGBE_I2C_EEPROM_DEV_ADDR,
1493 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
1494 * @hw: pointer to hardware structure
1495 * @byte_offset: byte offset to read
1498 * Performs byte read operation to SFP module's EEPROM over I2C interface at
1499 * a specified device address.
1501 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1502 u8 dev_addr, u8 *data)
1511 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1512 swfw_mask = IXGBE_GSSR_PHY1_SM;
1514 swfw_mask = IXGBE_GSSR_PHY0_SM;
1517 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 0) {
1518 status = IXGBE_ERR_SWFW_SYNC;
1522 ixgbe_i2c_start(hw);
1524 /* Device Address and write indication */
1525 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1529 status = ixgbe_get_i2c_ack(hw);
1533 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1537 status = ixgbe_get_i2c_ack(hw);
1541 ixgbe_i2c_start(hw);
1543 /* Device Address and read indication */
1544 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
1548 status = ixgbe_get_i2c_ack(hw);
1552 status = ixgbe_clock_in_i2c_byte(hw, data);
1556 status = ixgbe_clock_out_i2c_bit(hw, nack);
1564 ixgbe_i2c_bus_clear(hw);
1565 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1568 if (retry < max_retry)
1569 hw_dbg(hw, "I2C byte read error - Retrying.\n");
1571 hw_dbg(hw, "I2C byte read error.\n");
1573 } while (retry < max_retry);
1575 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1582 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
1583 * @hw: pointer to hardware structure
1584 * @byte_offset: byte offset to write
1585 * @data: value to write
1587 * Performs byte write operation to SFP module's EEPROM over I2C interface at
1588 * a specified device address.
1590 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1591 u8 dev_addr, u8 data)
1598 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1599 swfw_mask = IXGBE_GSSR_PHY1_SM;
1601 swfw_mask = IXGBE_GSSR_PHY0_SM;
1603 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 0) {
1604 status = IXGBE_ERR_SWFW_SYNC;
1605 goto write_byte_out;
1609 ixgbe_i2c_start(hw);
1611 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1615 status = ixgbe_get_i2c_ack(hw);
1619 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1623 status = ixgbe_get_i2c_ack(hw);
1627 status = ixgbe_clock_out_i2c_byte(hw, data);
1631 status = ixgbe_get_i2c_ack(hw);
1639 ixgbe_i2c_bus_clear(hw);
1641 if (retry < max_retry)
1642 hw_dbg(hw, "I2C byte write error - Retrying.\n");
1644 hw_dbg(hw, "I2C byte write error.\n");
1645 } while (retry < max_retry);
1647 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1654 * ixgbe_i2c_start - Sets I2C start condition
1655 * @hw: pointer to hardware structure
1657 * Sets I2C start condition (High -> Low on SDA while SCL is High)
1659 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
1661 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1663 /* Start condition must begin with data and clock high */
1664 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1665 ixgbe_raise_i2c_clk(hw, &i2cctl);
1667 /* Setup time for start condition (4.7us) */
1668 udelay(IXGBE_I2C_T_SU_STA);
1670 ixgbe_set_i2c_data(hw, &i2cctl, 0);
1672 /* Hold time for start condition (4us) */
1673 udelay(IXGBE_I2C_T_HD_STA);
1675 ixgbe_lower_i2c_clk(hw, &i2cctl);
1677 /* Minimum low period of clock is 4.7 us */
1678 udelay(IXGBE_I2C_T_LOW);
1683 * ixgbe_i2c_stop - Sets I2C stop condition
1684 * @hw: pointer to hardware structure
1686 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
1688 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
1690 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1692 /* Stop condition must begin with data low and clock high */
1693 ixgbe_set_i2c_data(hw, &i2cctl, 0);
1694 ixgbe_raise_i2c_clk(hw, &i2cctl);
1696 /* Setup time for stop condition (4us) */
1697 udelay(IXGBE_I2C_T_SU_STO);
1699 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1701 /* bus free time between stop and start (4.7us)*/
1702 udelay(IXGBE_I2C_T_BUF);
1706 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
1707 * @hw: pointer to hardware structure
1708 * @data: data byte to clock in
1710 * Clocks in one byte data via I2C data/clock
1712 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
1717 for (i = 7; i >= 0; i--) {
1718 ixgbe_clock_in_i2c_bit(hw, &bit);
1726 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
1727 * @hw: pointer to hardware structure
1728 * @data: data byte clocked out
1730 * Clocks out one byte data via I2C data/clock
1732 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
1739 for (i = 7; i >= 0; i--) {
1740 bit = (data >> i) & 0x1;
1741 status = ixgbe_clock_out_i2c_bit(hw, bit);
1747 /* Release SDA line (set high) */
1748 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1749 i2cctl |= IXGBE_I2C_DATA_OUT;
1750 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
1751 IXGBE_WRITE_FLUSH(hw);
1757 * ixgbe_get_i2c_ack - Polls for I2C ACK
1758 * @hw: pointer to hardware structure
1760 * Clocks in/out one bit via I2C data/clock
1762 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
1766 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1770 ixgbe_raise_i2c_clk(hw, &i2cctl);
1773 /* Minimum high period of clock is 4us */
1774 udelay(IXGBE_I2C_T_HIGH);
1776 /* Poll for ACK. Note that ACK in I2C spec is
1777 * transition from 1 to 0 */
1778 for (i = 0; i < timeout; i++) {
1779 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1780 ack = ixgbe_get_i2c_data(&i2cctl);
1788 hw_dbg(hw, "I2C ack was not received.\n");
1789 status = IXGBE_ERR_I2C;
1792 ixgbe_lower_i2c_clk(hw, &i2cctl);
1794 /* Minimum low period of clock is 4.7 us */
1795 udelay(IXGBE_I2C_T_LOW);
1801 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
1802 * @hw: pointer to hardware structure
1803 * @data: read data value
1805 * Clocks in one bit via I2C data/clock
1807 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
1809 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1811 ixgbe_raise_i2c_clk(hw, &i2cctl);
1813 /* Minimum high period of clock is 4us */
1814 udelay(IXGBE_I2C_T_HIGH);
1816 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1817 *data = ixgbe_get_i2c_data(&i2cctl);
1819 ixgbe_lower_i2c_clk(hw, &i2cctl);
1821 /* Minimum low period of clock is 4.7 us */
1822 udelay(IXGBE_I2C_T_LOW);
1828 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
1829 * @hw: pointer to hardware structure
1830 * @data: data value to write
1832 * Clocks out one bit via I2C data/clock
1834 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
1837 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1839 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
1841 ixgbe_raise_i2c_clk(hw, &i2cctl);
1843 /* Minimum high period of clock is 4us */
1844 udelay(IXGBE_I2C_T_HIGH);
1846 ixgbe_lower_i2c_clk(hw, &i2cctl);
1848 /* Minimum low period of clock is 4.7 us.
1849 * This also takes care of the data hold time.
1851 udelay(IXGBE_I2C_T_LOW);
1853 status = IXGBE_ERR_I2C;
1854 hw_dbg(hw, "I2C data was not set to %X\n", data);
1860 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
1861 * @hw: pointer to hardware structure
1862 * @i2cctl: Current value of I2CCTL register
1864 * Raises the I2C clock line '0'->'1'
1866 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1869 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
1872 for (i = 0; i < timeout; i++) {
1873 *i2cctl |= IXGBE_I2C_CLK_OUT;
1874 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1875 IXGBE_WRITE_FLUSH(hw);
1876 /* SCL rise time (1000ns) */
1877 udelay(IXGBE_I2C_T_RISE);
1879 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1880 if (i2cctl_r & IXGBE_I2C_CLK_IN)
1886 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
1887 * @hw: pointer to hardware structure
1888 * @i2cctl: Current value of I2CCTL register
1890 * Lowers the I2C clock line '1'->'0'
1892 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1895 *i2cctl &= ~IXGBE_I2C_CLK_OUT;
1897 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1898 IXGBE_WRITE_FLUSH(hw);
1900 /* SCL fall time (300ns) */
1901 udelay(IXGBE_I2C_T_FALL);
1905 * ixgbe_set_i2c_data - Sets the I2C data bit
1906 * @hw: pointer to hardware structure
1907 * @i2cctl: Current value of I2CCTL register
1908 * @data: I2C data value (0 or 1) to set
1910 * Sets the I2C data bit
1912 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
1917 *i2cctl |= IXGBE_I2C_DATA_OUT;
1919 *i2cctl &= ~IXGBE_I2C_DATA_OUT;
1921 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1922 IXGBE_WRITE_FLUSH(hw);
1924 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
1925 udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
1927 /* Verify data was set correctly */
1928 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1929 if (data != ixgbe_get_i2c_data(i2cctl)) {
1930 status = IXGBE_ERR_I2C;
1931 hw_dbg(hw, "Error - I2C data was not set to %X.\n", data);
1938 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
1939 * @hw: pointer to hardware structure
1940 * @i2cctl: Current value of I2CCTL register
1942 * Returns the I2C data bit value
1944 static bool ixgbe_get_i2c_data(u32 *i2cctl)
1948 if (*i2cctl & IXGBE_I2C_DATA_IN)
1957 * ixgbe_i2c_bus_clear - Clears the I2C bus
1958 * @hw: pointer to hardware structure
1960 * Clears the I2C bus by sending nine clock pulses.
1961 * Used when data line is stuck low.
1963 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
1965 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1968 ixgbe_i2c_start(hw);
1970 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1972 for (i = 0; i < 9; i++) {
1973 ixgbe_raise_i2c_clk(hw, &i2cctl);
1975 /* Min high period of clock is 4us */
1976 udelay(IXGBE_I2C_T_HIGH);
1978 ixgbe_lower_i2c_clk(hw, &i2cctl);
1980 /* Min low period of clock is 4.7us*/
1981 udelay(IXGBE_I2C_T_LOW);
1984 ixgbe_i2c_start(hw);
1986 /* Put the i2c bus back to default state */
1991 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
1992 * @hw: pointer to hardware structure
1994 * Checks if the LASI temp alarm status was triggered due to overtemp
1996 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2001 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2004 /* Check that the LASI temp alarm status was triggered */
2005 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2006 MDIO_MMD_PMAPMD, &phy_data);
2008 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2011 status = IXGBE_ERR_OVERTEMP;