2 * Atmel MACB Ethernet Controller driver
4 * Copyright (C) 2004-2006 Atmel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
13 #define MACB_GREGS_NBR 16
14 #define MACB_GREGS_VERSION 1
15 #define MACB_MAX_QUEUES 8
17 /* MACB register offsets */
18 #define MACB_NCR 0x0000 /* Network Control */
19 #define MACB_NCFGR 0x0004 /* Network Config */
20 #define MACB_NSR 0x0008 /* Network Status */
21 #define MACB_TAR 0x000c /* AT91RM9200 only */
22 #define MACB_TCR 0x0010 /* AT91RM9200 only */
23 #define MACB_TSR 0x0014 /* Transmit Status */
24 #define MACB_RBQP 0x0018 /* RX Q Base Address */
25 #define MACB_TBQP 0x001c /* TX Q Base Address */
26 #define MACB_RSR 0x0020 /* Receive Status */
27 #define MACB_ISR 0x0024 /* Interrupt Status */
28 #define MACB_IER 0x0028 /* Interrupt Enable */
29 #define MACB_IDR 0x002c /* Interrupt Disable */
30 #define MACB_IMR 0x0030 /* Interrupt Mask */
31 #define MACB_MAN 0x0034 /* PHY Maintenance */
32 #define MACB_PTR 0x0038
33 #define MACB_PFR 0x003c
34 #define MACB_FTO 0x0040
35 #define MACB_SCF 0x0044
36 #define MACB_MCF 0x0048
37 #define MACB_FRO 0x004c
38 #define MACB_FCSE 0x0050
39 #define MACB_ALE 0x0054
40 #define MACB_DTF 0x0058
41 #define MACB_LCOL 0x005c
42 #define MACB_EXCOL 0x0060
43 #define MACB_TUND 0x0064
44 #define MACB_CSE 0x0068
45 #define MACB_RRE 0x006c
46 #define MACB_ROVR 0x0070
47 #define MACB_RSE 0x0074
48 #define MACB_ELE 0x0078
49 #define MACB_RJA 0x007c
50 #define MACB_USF 0x0080
51 #define MACB_STE 0x0084
52 #define MACB_RLE 0x0088
53 #define MACB_TPF 0x008c
54 #define MACB_HRB 0x0090
55 #define MACB_HRT 0x0094
56 #define MACB_SA1B 0x0098
57 #define MACB_SA1T 0x009c
58 #define MACB_SA2B 0x00a0
59 #define MACB_SA2T 0x00a4
60 #define MACB_SA3B 0x00a8
61 #define MACB_SA3T 0x00ac
62 #define MACB_SA4B 0x00b0
63 #define MACB_SA4T 0x00b4
64 #define MACB_TID 0x00b8
65 #define MACB_TPQ 0x00bc
66 #define MACB_USRIO 0x00c0
67 #define MACB_WOL 0x00c4
68 #define MACB_MID 0x00fc
70 /* GEM register offsets. */
71 #define GEM_NCFGR 0x0004 /* Network Config */
72 #define GEM_USRIO 0x000c /* User IO */
73 #define GEM_DMACFG 0x0010 /* DMA Configuration */
74 #define GEM_HRB 0x0080 /* Hash Bottom */
75 #define GEM_HRT 0x0084 /* Hash Top */
76 #define GEM_SA1B 0x0088 /* Specific1 Bottom */
77 #define GEM_SA1T 0x008C /* Specific1 Top */
78 #define GEM_SA2B 0x0090 /* Specific2 Bottom */
79 #define GEM_SA2T 0x0094 /* Specific2 Top */
80 #define GEM_SA3B 0x0098 /* Specific3 Bottom */
81 #define GEM_SA3T 0x009C /* Specific3 Top */
82 #define GEM_SA4B 0x00A0 /* Specific4 Bottom */
83 #define GEM_SA4T 0x00A4 /* Specific4 Top */
84 #define GEM_OTX 0x0100 /* Octets transmitted */
85 #define GEM_OCTTXL 0x0100 /* Octets transmitted [31:0] */
86 #define GEM_OCTTXH 0x0104 /* Octets transmitted [47:32] */
87 #define GEM_TXCNT 0x0108 /* Frames Transmitted counter */
88 #define GEM_TXBCCNT 0x010c /* Broadcast Frames counter */
89 #define GEM_TXMCCNT 0x0110 /* Multicast Frames counter */
90 #define GEM_TXPAUSECNT 0x0114 /* Pause Frames Transmitted Counter */
91 #define GEM_TX64CNT 0x0118 /* 64 byte Frames TX counter */
92 #define GEM_TX65CNT 0x011c /* 65-127 byte Frames TX counter */
93 #define GEM_TX128CNT 0x0120 /* 128-255 byte Frames TX counter */
94 #define GEM_TX256CNT 0x0124 /* 256-511 byte Frames TX counter */
95 #define GEM_TX512CNT 0x0128 /* 512-1023 byte Frames TX counter */
96 #define GEM_TX1024CNT 0x012c /* 1024-1518 byte Frames TX counter */
97 #define GEM_TX1519CNT 0x0130 /* 1519+ byte Frames TX counter */
98 #define GEM_TXURUNCNT 0x0134 /* TX under run error counter */
99 #define GEM_SNGLCOLLCNT 0x0138 /* Single Collision Frame Counter */
100 #define GEM_MULTICOLLCNT 0x013c /* Multiple Collision Frame Counter */
101 #define GEM_EXCESSCOLLCNT 0x0140 /* Excessive Collision Frame Counter */
102 #define GEM_LATECOLLCNT 0x0144 /* Late Collision Frame Counter */
103 #define GEM_TXDEFERCNT 0x0148 /* Deferred Transmission Frame Counter */
104 #define GEM_TXCSENSECNT 0x014c /* Carrier Sense Error Counter */
105 #define GEM_ORX 0x0150 /* Octets received */
106 #define GEM_OCTRXL 0x0150 /* Octets received [31:0] */
107 #define GEM_OCTRXH 0x0154 /* Octets received [47:32] */
108 #define GEM_RXCNT 0x0158 /* Frames Received Counter */
109 #define GEM_RXBROADCNT 0x015c /* Broadcast Frames Received Counter */
110 #define GEM_RXMULTICNT 0x0160 /* Multicast Frames Received Counter */
111 #define GEM_RXPAUSECNT 0x0164 /* Pause Frames Received Counter */
112 #define GEM_RX64CNT 0x0168 /* 64 byte Frames RX Counter */
113 #define GEM_RX65CNT 0x016c /* 65-127 byte Frames RX Counter */
114 #define GEM_RX128CNT 0x0170 /* 128-255 byte Frames RX Counter */
115 #define GEM_RX256CNT 0x0174 /* 256-511 byte Frames RX Counter */
116 #define GEM_RX512CNT 0x0178 /* 512-1023 byte Frames RX Counter */
117 #define GEM_RX1024CNT 0x017c /* 1024-1518 byte Frames RX Counter */
118 #define GEM_RX1519CNT 0x0180 /* 1519+ byte Frames RX Counter */
119 #define GEM_RXUNDRCNT 0x0184 /* Undersize Frames Received Counter */
120 #define GEM_RXOVRCNT 0x0188 /* Oversize Frames Received Counter */
121 #define GEM_RXJABCNT 0x018c /* Jabbers Received Counter */
122 #define GEM_RXFCSCNT 0x0190 /* Frame Check Sequence Error Counter */
123 #define GEM_RXLENGTHCNT 0x0194 /* Length Field Error Counter */
124 #define GEM_RXSYMBCNT 0x0198 /* Symbol Error Counter */
125 #define GEM_RXALIGNCNT 0x019c /* Alignment Error Counter */
126 #define GEM_RXRESERRCNT 0x01a0 /* Receive Resource Error Counter */
127 #define GEM_RXORCNT 0x01a4 /* Receive Overrun Counter */
128 #define GEM_RXIPCCNT 0x01a8 /* IP header Checksum Error Counter */
129 #define GEM_RXTCPCCNT 0x01ac /* TCP Checksum Error Counter */
130 #define GEM_RXUDPCCNT 0x01b0 /* UDP Checksum Error Counter */
131 #define GEM_DCFG1 0x0280 /* Design Config 1 */
132 #define GEM_DCFG2 0x0284 /* Design Config 2 */
133 #define GEM_DCFG3 0x0288 /* Design Config 3 */
134 #define GEM_DCFG4 0x028c /* Design Config 4 */
135 #define GEM_DCFG5 0x0290 /* Design Config 5 */
136 #define GEM_DCFG6 0x0294 /* Design Config 6 */
137 #define GEM_DCFG7 0x0298 /* Design Config 7 */
139 #define GEM_ISR(hw_q) (0x0400 + ((hw_q) << 2))
140 #define GEM_TBQP(hw_q) (0x0440 + ((hw_q) << 2))
141 #define GEM_RBQP(hw_q) (0x0480 + ((hw_q) << 2))
142 #define GEM_IER(hw_q) (0x0600 + ((hw_q) << 2))
143 #define GEM_IDR(hw_q) (0x0620 + ((hw_q) << 2))
144 #define GEM_IMR(hw_q) (0x0640 + ((hw_q) << 2))
146 /* Bitfields in NCR */
147 #define MACB_LB_OFFSET 0 /* reserved */
148 #define MACB_LB_SIZE 1
149 #define MACB_LLB_OFFSET 1 /* Loop back local */
150 #define MACB_LLB_SIZE 1
151 #define MACB_RE_OFFSET 2 /* Receive enable */
152 #define MACB_RE_SIZE 1
153 #define MACB_TE_OFFSET 3 /* Transmit enable */
154 #define MACB_TE_SIZE 1
155 #define MACB_MPE_OFFSET 4 /* Management port enable */
156 #define MACB_MPE_SIZE 1
157 #define MACB_CLRSTAT_OFFSET 5 /* Clear stats regs */
158 #define MACB_CLRSTAT_SIZE 1
159 #define MACB_INCSTAT_OFFSET 6 /* Incremental stats regs */
160 #define MACB_INCSTAT_SIZE 1
161 #define MACB_WESTAT_OFFSET 7 /* Write enable stats regs */
162 #define MACB_WESTAT_SIZE 1
163 #define MACB_BP_OFFSET 8 /* Back pressure */
164 #define MACB_BP_SIZE 1
165 #define MACB_TSTART_OFFSET 9 /* Start transmission */
166 #define MACB_TSTART_SIZE 1
167 #define MACB_THALT_OFFSET 10 /* Transmit halt */
168 #define MACB_THALT_SIZE 1
169 #define MACB_NCR_TPF_OFFSET 11 /* Transmit pause frame */
170 #define MACB_NCR_TPF_SIZE 1
171 #define MACB_TZQ_OFFSET 12 /* Transmit zero quantum pause frame */
172 #define MACB_TZQ_SIZE 1
174 /* Bitfields in NCFGR */
175 #define MACB_SPD_OFFSET 0 /* Speed */
176 #define MACB_SPD_SIZE 1
177 #define MACB_FD_OFFSET 1 /* Full duplex */
178 #define MACB_FD_SIZE 1
179 #define MACB_BIT_RATE_OFFSET 2 /* Discard non-VLAN frames */
180 #define MACB_BIT_RATE_SIZE 1
181 #define MACB_JFRAME_OFFSET 3 /* reserved */
182 #define MACB_JFRAME_SIZE 1
183 #define MACB_CAF_OFFSET 4 /* Copy all frames */
184 #define MACB_CAF_SIZE 1
185 #define MACB_NBC_OFFSET 5 /* No broadcast */
186 #define MACB_NBC_SIZE 1
187 #define MACB_NCFGR_MTI_OFFSET 6 /* Multicast hash enable */
188 #define MACB_NCFGR_MTI_SIZE 1
189 #define MACB_UNI_OFFSET 7 /* Unicast hash enable */
190 #define MACB_UNI_SIZE 1
191 #define MACB_BIG_OFFSET 8 /* Receive 1536 byte frames */
192 #define MACB_BIG_SIZE 1
193 #define MACB_EAE_OFFSET 9 /* External address match enable */
194 #define MACB_EAE_SIZE 1
195 #define MACB_CLK_OFFSET 10
196 #define MACB_CLK_SIZE 2
197 #define MACB_RTY_OFFSET 12 /* Retry test */
198 #define MACB_RTY_SIZE 1
199 #define MACB_PAE_OFFSET 13 /* Pause enable */
200 #define MACB_PAE_SIZE 1
201 #define MACB_RM9200_RMII_OFFSET 13 /* AT91RM9200 only */
202 #define MACB_RM9200_RMII_SIZE 1 /* AT91RM9200 only */
203 #define MACB_RBOF_OFFSET 14 /* Receive buffer offset */
204 #define MACB_RBOF_SIZE 2
205 #define MACB_RLCE_OFFSET 16 /* Length field error frame discard */
206 #define MACB_RLCE_SIZE 1
207 #define MACB_DRFCS_OFFSET 17 /* FCS remove */
208 #define MACB_DRFCS_SIZE 1
209 #define MACB_EFRHD_OFFSET 18
210 #define MACB_EFRHD_SIZE 1
211 #define MACB_IRXFCS_OFFSET 19
212 #define MACB_IRXFCS_SIZE 1
214 /* GEM specific NCFGR bitfields. */
215 #define GEM_GBE_OFFSET 10 /* Gigabit mode enable */
216 #define GEM_GBE_SIZE 1
217 #define GEM_CLK_OFFSET 18 /* MDC clock division */
218 #define GEM_CLK_SIZE 3
219 #define GEM_DBW_OFFSET 21 /* Data bus width */
220 #define GEM_DBW_SIZE 2
221 #define GEM_RXCOEN_OFFSET 24
222 #define GEM_RXCOEN_SIZE 1
224 /* Constants for data bus width. */
225 #define GEM_DBW32 0 /* 32 bit AMBA AHB data bus width */
226 #define GEM_DBW64 1 /* 64 bit AMBA AHB data bus width */
227 #define GEM_DBW128 2 /* 128 bit AMBA AHB data bus width */
229 /* Bitfields in DMACFG. */
230 #define GEM_FBLDO_OFFSET 0 /* fixed burst length for DMA */
231 #define GEM_FBLDO_SIZE 5
232 #define GEM_ENDIA_OFFSET 7 /* endian swap mode for packet data access */
233 #define GEM_ENDIA_SIZE 1
234 #define GEM_RXBMS_OFFSET 8 /* RX packet buffer memory size select */
235 #define GEM_RXBMS_SIZE 2
236 #define GEM_TXPBMS_OFFSET 10 /* TX packet buffer memory size select */
237 #define GEM_TXPBMS_SIZE 1
238 #define GEM_TXCOEN_OFFSET 11 /* TX IP/TCP/UDP checksum gen offload */
239 #define GEM_TXCOEN_SIZE 1
240 #define GEM_RXBS_OFFSET 16 /* DMA receive buffer size */
241 #define GEM_RXBS_SIZE 8
242 #define GEM_DDRP_OFFSET 24 /* disc_when_no_ahb */
243 #define GEM_DDRP_SIZE 1
246 /* Bitfields in NSR */
247 #define MACB_NSR_LINK_OFFSET 0 /* pcs_link_state */
248 #define MACB_NSR_LINK_SIZE 1
249 #define MACB_MDIO_OFFSET 1 /* status of the mdio_in pin */
250 #define MACB_MDIO_SIZE 1
251 #define MACB_IDLE_OFFSET 2 /* The PHY management logic is idle */
252 #define MACB_IDLE_SIZE 1
254 /* Bitfields in TSR */
255 #define MACB_UBR_OFFSET 0 /* Used bit read */
256 #define MACB_UBR_SIZE 1
257 #define MACB_COL_OFFSET 1 /* Collision occurred */
258 #define MACB_COL_SIZE 1
259 #define MACB_TSR_RLE_OFFSET 2 /* Retry limit exceeded */
260 #define MACB_TSR_RLE_SIZE 1
261 #define MACB_TGO_OFFSET 3 /* Transmit go */
262 #define MACB_TGO_SIZE 1
263 #define MACB_BEX_OFFSET 4 /* TX frame corruption due to AHB error */
264 #define MACB_BEX_SIZE 1
265 #define MACB_RM9200_BNQ_OFFSET 4 /* AT91RM9200 only */
266 #define MACB_RM9200_BNQ_SIZE 1 /* AT91RM9200 only */
267 #define MACB_COMP_OFFSET 5 /* Trnasmit complete */
268 #define MACB_COMP_SIZE 1
269 #define MACB_UND_OFFSET 6 /* Trnasmit under run */
270 #define MACB_UND_SIZE 1
272 /* Bitfields in RSR */
273 #define MACB_BNA_OFFSET 0 /* Buffer not available */
274 #define MACB_BNA_SIZE 1
275 #define MACB_REC_OFFSET 1 /* Frame received */
276 #define MACB_REC_SIZE 1
277 #define MACB_OVR_OFFSET 2 /* Receive overrun */
278 #define MACB_OVR_SIZE 1
280 /* Bitfields in ISR/IER/IDR/IMR */
281 #define MACB_MFD_OFFSET 0 /* Management frame sent */
282 #define MACB_MFD_SIZE 1
283 #define MACB_RCOMP_OFFSET 1 /* Receive complete */
284 #define MACB_RCOMP_SIZE 1
285 #define MACB_RXUBR_OFFSET 2 /* RX used bit read */
286 #define MACB_RXUBR_SIZE 1
287 #define MACB_TXUBR_OFFSET 3 /* TX used bit read */
288 #define MACB_TXUBR_SIZE 1
289 #define MACB_ISR_TUND_OFFSET 4 /* Enable TX buffer under run interrupt */
290 #define MACB_ISR_TUND_SIZE 1
291 #define MACB_ISR_RLE_OFFSET 5 /* EN retry exceeded/late coll interrupt */
292 #define MACB_ISR_RLE_SIZE 1
293 #define MACB_TXERR_OFFSET 6 /* EN TX frame corrupt from error interrupt */
294 #define MACB_TXERR_SIZE 1
295 #define MACB_TCOMP_OFFSET 7 /* Enable transmit complete interrupt */
296 #define MACB_TCOMP_SIZE 1
297 #define MACB_ISR_LINK_OFFSET 9 /* Enable link change interrupt */
298 #define MACB_ISR_LINK_SIZE 1
299 #define MACB_ISR_ROVR_OFFSET 10 /* Enable receive overrun interrupt */
300 #define MACB_ISR_ROVR_SIZE 1
301 #define MACB_HRESP_OFFSET 11 /* Enable hrsep not OK interrupt */
302 #define MACB_HRESP_SIZE 1
303 #define MACB_PFR_OFFSET 12 /* Enable pause frame w/ quantum interrupt */
304 #define MACB_PFR_SIZE 1
305 #define MACB_PTZ_OFFSET 13 /* Enable pause time zero interrupt */
306 #define MACB_PTZ_SIZE 1
308 /* Bitfields in MAN */
309 #define MACB_DATA_OFFSET 0 /* data */
310 #define MACB_DATA_SIZE 16
311 #define MACB_CODE_OFFSET 16 /* Must be written to 10 */
312 #define MACB_CODE_SIZE 2
313 #define MACB_REGA_OFFSET 18 /* Register address */
314 #define MACB_REGA_SIZE 5
315 #define MACB_PHYA_OFFSET 23 /* PHY address */
316 #define MACB_PHYA_SIZE 5
317 #define MACB_RW_OFFSET 28 /* Operation. 10 is read. 01 is write. */
318 #define MACB_RW_SIZE 2
319 #define MACB_SOF_OFFSET 30 /* Must be written to 1 for Clause 22 */
320 #define MACB_SOF_SIZE 2
322 /* Bitfields in USRIO (AVR32) */
323 #define MACB_MII_OFFSET 0
324 #define MACB_MII_SIZE 1
325 #define MACB_EAM_OFFSET 1
326 #define MACB_EAM_SIZE 1
327 #define MACB_TX_PAUSE_OFFSET 2
328 #define MACB_TX_PAUSE_SIZE 1
329 #define MACB_TX_PAUSE_ZERO_OFFSET 3
330 #define MACB_TX_PAUSE_ZERO_SIZE 1
332 /* Bitfields in USRIO (AT91) */
333 #define MACB_RMII_OFFSET 0
334 #define MACB_RMII_SIZE 1
335 #define GEM_RGMII_OFFSET 0 /* GEM gigabit mode */
336 #define GEM_RGMII_SIZE 1
337 #define MACB_CLKEN_OFFSET 1
338 #define MACB_CLKEN_SIZE 1
340 /* Bitfields in WOL */
341 #define MACB_IP_OFFSET 0
342 #define MACB_IP_SIZE 16
343 #define MACB_MAG_OFFSET 16
344 #define MACB_MAG_SIZE 1
345 #define MACB_ARP_OFFSET 17
346 #define MACB_ARP_SIZE 1
347 #define MACB_SA1_OFFSET 18
348 #define MACB_SA1_SIZE 1
349 #define MACB_WOL_MTI_OFFSET 19
350 #define MACB_WOL_MTI_SIZE 1
352 /* Bitfields in MID */
353 #define MACB_IDNUM_OFFSET 16
354 #define MACB_IDNUM_SIZE 16
355 #define MACB_REV_OFFSET 0
356 #define MACB_REV_SIZE 16
358 /* Bitfields in DCFG1. */
359 #define GEM_IRQCOR_OFFSET 23
360 #define GEM_IRQCOR_SIZE 1
361 #define GEM_DBWDEF_OFFSET 25
362 #define GEM_DBWDEF_SIZE 3
364 /* Bitfields in DCFG2. */
365 #define GEM_RX_PKT_BUFF_OFFSET 20
366 #define GEM_RX_PKT_BUFF_SIZE 1
367 #define GEM_TX_PKT_BUFF_OFFSET 21
368 #define GEM_TX_PKT_BUFF_SIZE 1
370 /* Constants for CLK */
371 #define MACB_CLK_DIV8 0
372 #define MACB_CLK_DIV16 1
373 #define MACB_CLK_DIV32 2
374 #define MACB_CLK_DIV64 3
376 /* GEM specific constants for CLK. */
377 #define GEM_CLK_DIV8 0
378 #define GEM_CLK_DIV16 1
379 #define GEM_CLK_DIV32 2
380 #define GEM_CLK_DIV48 3
381 #define GEM_CLK_DIV64 4
382 #define GEM_CLK_DIV96 5
384 /* Constants for MAN register */
385 #define MACB_MAN_SOF 1
386 #define MACB_MAN_WRITE 1
387 #define MACB_MAN_READ 2
388 #define MACB_MAN_CODE 2
390 /* Capability mask bits */
391 #define MACB_CAPS_ISR_CLEAR_ON_WRITE 0x00000001
392 #define MACB_CAPS_FIFO_MODE 0x10000000
393 #define MACB_CAPS_GIGABIT_MODE_AVAILABLE 0x20000000
394 #define MACB_CAPS_SG_DISABLED 0x40000000
395 #define MACB_CAPS_MACB_IS_GEM 0x80000000
397 /* Bit manipulation macros */
398 #define MACB_BIT(name) \
399 (1 << MACB_##name##_OFFSET)
400 #define MACB_BF(name,value) \
401 (((value) & ((1 << MACB_##name##_SIZE) - 1)) \
402 << MACB_##name##_OFFSET)
403 #define MACB_BFEXT(name,value)\
404 (((value) >> MACB_##name##_OFFSET) \
405 & ((1 << MACB_##name##_SIZE) - 1))
406 #define MACB_BFINS(name,value,old) \
407 (((old) & ~(((1 << MACB_##name##_SIZE) - 1) \
408 << MACB_##name##_OFFSET)) \
409 | MACB_BF(name,value))
411 #define GEM_BIT(name) \
412 (1 << GEM_##name##_OFFSET)
413 #define GEM_BF(name, value) \
414 (((value) & ((1 << GEM_##name##_SIZE) - 1)) \
415 << GEM_##name##_OFFSET)
416 #define GEM_BFEXT(name, value)\
417 (((value) >> GEM_##name##_OFFSET) \
418 & ((1 << GEM_##name##_SIZE) - 1))
419 #define GEM_BFINS(name, value, old) \
420 (((old) & ~(((1 << GEM_##name##_SIZE) - 1) \
421 << GEM_##name##_OFFSET)) \
422 | GEM_BF(name, value))
424 /* Register access macros */
425 #define macb_readl(port,reg) \
426 __raw_readl((port)->regs + MACB_##reg)
427 #define macb_writel(port,reg,value) \
428 __raw_writel((value), (port)->regs + MACB_##reg)
429 #define gem_readl(port, reg) \
430 __raw_readl((port)->regs + GEM_##reg)
431 #define gem_writel(port, reg, value) \
432 __raw_writel((value), (port)->regs + GEM_##reg)
433 #define queue_readl(queue, reg) \
434 __raw_readl((queue)->bp->regs + (queue)->reg)
435 #define queue_writel(queue, reg, value) \
436 __raw_writel((value), (queue)->bp->regs + (queue)->reg)
438 /* Conditional GEM/MACB macros. These perform the operation to the correct
439 * register dependent on whether the device is a GEM or a MACB. For registers
440 * and bitfields that are common across both devices, use macb_{read,write}l
441 * to avoid the cost of the conditional.
443 #define macb_or_gem_writel(__bp, __reg, __value) \
445 if (macb_is_gem((__bp))) \
446 gem_writel((__bp), __reg, __value); \
448 macb_writel((__bp), __reg, __value); \
451 #define macb_or_gem_readl(__bp, __reg) \
454 if (macb_is_gem((__bp))) \
455 __v = gem_readl((__bp), __reg); \
457 __v = macb_readl((__bp), __reg); \
461 /* struct macb_dma_desc - Hardware DMA descriptor
462 * @addr: DMA address of data buffer
463 * @ctrl: Control and status bits
465 struct macb_dma_desc {
470 /* DMA descriptor bitfields */
471 #define MACB_RX_USED_OFFSET 0
472 #define MACB_RX_USED_SIZE 1
473 #define MACB_RX_WRAP_OFFSET 1
474 #define MACB_RX_WRAP_SIZE 1
475 #define MACB_RX_WADDR_OFFSET 2
476 #define MACB_RX_WADDR_SIZE 30
478 #define MACB_RX_FRMLEN_OFFSET 0
479 #define MACB_RX_FRMLEN_SIZE 12
480 #define MACB_RX_OFFSET_OFFSET 12
481 #define MACB_RX_OFFSET_SIZE 2
482 #define MACB_RX_SOF_OFFSET 14
483 #define MACB_RX_SOF_SIZE 1
484 #define MACB_RX_EOF_OFFSET 15
485 #define MACB_RX_EOF_SIZE 1
486 #define MACB_RX_CFI_OFFSET 16
487 #define MACB_RX_CFI_SIZE 1
488 #define MACB_RX_VLAN_PRI_OFFSET 17
489 #define MACB_RX_VLAN_PRI_SIZE 3
490 #define MACB_RX_PRI_TAG_OFFSET 20
491 #define MACB_RX_PRI_TAG_SIZE 1
492 #define MACB_RX_VLAN_TAG_OFFSET 21
493 #define MACB_RX_VLAN_TAG_SIZE 1
494 #define MACB_RX_TYPEID_MATCH_OFFSET 22
495 #define MACB_RX_TYPEID_MATCH_SIZE 1
496 #define MACB_RX_SA4_MATCH_OFFSET 23
497 #define MACB_RX_SA4_MATCH_SIZE 1
498 #define MACB_RX_SA3_MATCH_OFFSET 24
499 #define MACB_RX_SA3_MATCH_SIZE 1
500 #define MACB_RX_SA2_MATCH_OFFSET 25
501 #define MACB_RX_SA2_MATCH_SIZE 1
502 #define MACB_RX_SA1_MATCH_OFFSET 26
503 #define MACB_RX_SA1_MATCH_SIZE 1
504 #define MACB_RX_EXT_MATCH_OFFSET 28
505 #define MACB_RX_EXT_MATCH_SIZE 1
506 #define MACB_RX_UHASH_MATCH_OFFSET 29
507 #define MACB_RX_UHASH_MATCH_SIZE 1
508 #define MACB_RX_MHASH_MATCH_OFFSET 30
509 #define MACB_RX_MHASH_MATCH_SIZE 1
510 #define MACB_RX_BROADCAST_OFFSET 31
511 #define MACB_RX_BROADCAST_SIZE 1
513 /* RX checksum offload disabled: bit 24 clear in NCFGR */
514 #define GEM_RX_TYPEID_MATCH_OFFSET 22
515 #define GEM_RX_TYPEID_MATCH_SIZE 2
517 /* RX checksum offload enabled: bit 24 set in NCFGR */
518 #define GEM_RX_CSUM_OFFSET 22
519 #define GEM_RX_CSUM_SIZE 2
521 #define MACB_TX_FRMLEN_OFFSET 0
522 #define MACB_TX_FRMLEN_SIZE 11
523 #define MACB_TX_LAST_OFFSET 15
524 #define MACB_TX_LAST_SIZE 1
525 #define MACB_TX_NOCRC_OFFSET 16
526 #define MACB_TX_NOCRC_SIZE 1
527 #define MACB_TX_BUF_EXHAUSTED_OFFSET 27
528 #define MACB_TX_BUF_EXHAUSTED_SIZE 1
529 #define MACB_TX_UNDERRUN_OFFSET 28
530 #define MACB_TX_UNDERRUN_SIZE 1
531 #define MACB_TX_ERROR_OFFSET 29
532 #define MACB_TX_ERROR_SIZE 1
533 #define MACB_TX_WRAP_OFFSET 30
534 #define MACB_TX_WRAP_SIZE 1
535 #define MACB_TX_USED_OFFSET 31
536 #define MACB_TX_USED_SIZE 1
538 #define GEM_TX_FRMLEN_OFFSET 0
539 #define GEM_TX_FRMLEN_SIZE 14
541 /* Buffer descriptor constants */
542 #define GEM_RX_CSUM_NONE 0
543 #define GEM_RX_CSUM_IP_ONLY 1
544 #define GEM_RX_CSUM_IP_TCP 2
545 #define GEM_RX_CSUM_IP_UDP 3
547 /* limit RX checksum offload to TCP and UDP packets */
548 #define GEM_RX_CSUM_CHECKED_MASK 2
550 /* struct macb_tx_skb - data about an skb which is being transmitted
551 * @skb: skb currently being transmitted, only set for the last buffer
553 * @mapping: DMA address of the skb's fragment buffer
554 * @size: size of the DMA mapped buffer
555 * @mapped_as_page: true when buffer was mapped with skb_frag_dma_map(),
556 * false when buffer was mapped with dma_map_single()
565 /* Hardware-collected statistics. Used when updating the network
566 * device stats by a periodic timer.
572 u32 tx_multiple_cols;
578 u32 tx_excessive_cols;
580 u32 tx_carrier_errors;
581 u32 rx_resource_errors;
583 u32 rx_symbol_errors;
584 u32 rx_oversize_pkts;
586 u32 rx_undersize_pkts;
588 u32 rx_length_mismatch;
596 u32 tx_broadcast_frames;
597 u32 tx_multicast_frames;
599 u32 tx_64_byte_frames;
600 u32 tx_65_127_byte_frames;
601 u32 tx_128_255_byte_frames;
602 u32 tx_256_511_byte_frames;
603 u32 tx_512_1023_byte_frames;
604 u32 tx_1024_1518_byte_frames;
605 u32 tx_greater_than_1518_byte_frames;
607 u32 tx_single_collision_frames;
608 u32 tx_multiple_collision_frames;
609 u32 tx_excessive_collisions;
610 u32 tx_late_collisions;
611 u32 tx_deferred_frames;
612 u32 tx_carrier_sense_errors;
616 u32 rx_broadcast_frames;
617 u32 rx_multicast_frames;
619 u32 rx_64_byte_frames;
620 u32 rx_65_127_byte_frames;
621 u32 rx_128_255_byte_frames;
622 u32 rx_256_511_byte_frames;
623 u32 rx_512_1023_byte_frames;
624 u32 rx_1024_1518_byte_frames;
625 u32 rx_greater_than_1518_byte_frames;
626 u32 rx_undersized_frames;
627 u32 rx_oversize_frames;
629 u32 rx_frame_check_sequence_errors;
630 u32 rx_length_field_frame_errors;
631 u32 rx_symbol_errors;
632 u32 rx_alignment_errors;
633 u32 rx_resource_errors;
635 u32 rx_ip_header_checksum_errors;
636 u32 rx_tcp_checksum_errors;
637 u32 rx_udp_checksum_errors;
640 /* Describes the name and offset of an individual statistic register, as
641 * returned by `ethtool -S`. Also describes which net_device_stats statistics
642 * this register should contribute to.
644 struct gem_statistic {
645 char stat_string[ETH_GSTRING_LEN];
650 /* Bitfield defs for net_device_stat statistics */
651 #define GEM_NDS_RXERR_OFFSET 0
652 #define GEM_NDS_RXLENERR_OFFSET 1
653 #define GEM_NDS_RXOVERERR_OFFSET 2
654 #define GEM_NDS_RXCRCERR_OFFSET 3
655 #define GEM_NDS_RXFRAMEERR_OFFSET 4
656 #define GEM_NDS_RXFIFOERR_OFFSET 5
657 #define GEM_NDS_TXERR_OFFSET 6
658 #define GEM_NDS_TXABORTEDERR_OFFSET 7
659 #define GEM_NDS_TXCARRIERERR_OFFSET 8
660 #define GEM_NDS_TXFIFOERR_OFFSET 9
661 #define GEM_NDS_COLLISIONS_OFFSET 10
663 #define GEM_STAT_TITLE(name, title) GEM_STAT_TITLE_BITS(name, title, 0)
664 #define GEM_STAT_TITLE_BITS(name, title, bits) { \
665 .stat_string = title, \
666 .offset = GEM_##name, \
670 /* list of gem statistic registers. The names MUST match the
671 * corresponding GEM_* definitions.
673 static const struct gem_statistic gem_statistics[] = {
674 GEM_STAT_TITLE(OCTTXL, "tx_octets"), /* OCTTXH combined with OCTTXL */
675 GEM_STAT_TITLE(TXCNT, "tx_frames"),
676 GEM_STAT_TITLE(TXBCCNT, "tx_broadcast_frames"),
677 GEM_STAT_TITLE(TXMCCNT, "tx_multicast_frames"),
678 GEM_STAT_TITLE(TXPAUSECNT, "tx_pause_frames"),
679 GEM_STAT_TITLE(TX64CNT, "tx_64_byte_frames"),
680 GEM_STAT_TITLE(TX65CNT, "tx_65_127_byte_frames"),
681 GEM_STAT_TITLE(TX128CNT, "tx_128_255_byte_frames"),
682 GEM_STAT_TITLE(TX256CNT, "tx_256_511_byte_frames"),
683 GEM_STAT_TITLE(TX512CNT, "tx_512_1023_byte_frames"),
684 GEM_STAT_TITLE(TX1024CNT, "tx_1024_1518_byte_frames"),
685 GEM_STAT_TITLE(TX1519CNT, "tx_greater_than_1518_byte_frames"),
686 GEM_STAT_TITLE_BITS(TXURUNCNT, "tx_underrun",
687 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_TXFIFOERR)),
688 GEM_STAT_TITLE_BITS(SNGLCOLLCNT, "tx_single_collision_frames",
689 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
690 GEM_STAT_TITLE_BITS(MULTICOLLCNT, "tx_multiple_collision_frames",
691 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
692 GEM_STAT_TITLE_BITS(EXCESSCOLLCNT, "tx_excessive_collisions",
694 GEM_BIT(NDS_TXABORTEDERR)|
695 GEM_BIT(NDS_COLLISIONS)),
696 GEM_STAT_TITLE_BITS(LATECOLLCNT, "tx_late_collisions",
697 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
698 GEM_STAT_TITLE(TXDEFERCNT, "tx_deferred_frames"),
699 GEM_STAT_TITLE_BITS(TXCSENSECNT, "tx_carrier_sense_errors",
700 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
701 GEM_STAT_TITLE(OCTRXL, "rx_octets"), /* OCTRXH combined with OCTRXL */
702 GEM_STAT_TITLE(RXCNT, "rx_frames"),
703 GEM_STAT_TITLE(RXBROADCNT, "rx_broadcast_frames"),
704 GEM_STAT_TITLE(RXMULTICNT, "rx_multicast_frames"),
705 GEM_STAT_TITLE(RXPAUSECNT, "rx_pause_frames"),
706 GEM_STAT_TITLE(RX64CNT, "rx_64_byte_frames"),
707 GEM_STAT_TITLE(RX65CNT, "rx_65_127_byte_frames"),
708 GEM_STAT_TITLE(RX128CNT, "rx_128_255_byte_frames"),
709 GEM_STAT_TITLE(RX256CNT, "rx_256_511_byte_frames"),
710 GEM_STAT_TITLE(RX512CNT, "rx_512_1023_byte_frames"),
711 GEM_STAT_TITLE(RX1024CNT, "rx_1024_1518_byte_frames"),
712 GEM_STAT_TITLE(RX1519CNT, "rx_greater_than_1518_byte_frames"),
713 GEM_STAT_TITLE_BITS(RXUNDRCNT, "rx_undersized_frames",
714 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)),
715 GEM_STAT_TITLE_BITS(RXOVRCNT, "rx_oversize_frames",
716 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)),
717 GEM_STAT_TITLE_BITS(RXJABCNT, "rx_jabbers",
718 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)),
719 GEM_STAT_TITLE_BITS(RXFCSCNT, "rx_frame_check_sequence_errors",
720 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXCRCERR)),
721 GEM_STAT_TITLE_BITS(RXLENGTHCNT, "rx_length_field_frame_errors",
723 GEM_STAT_TITLE_BITS(RXSYMBCNT, "rx_symbol_errors",
724 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXFRAMEERR)),
725 GEM_STAT_TITLE_BITS(RXALIGNCNT, "rx_alignment_errors",
726 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXOVERERR)),
727 GEM_STAT_TITLE_BITS(RXRESERRCNT, "rx_resource_errors",
728 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXOVERERR)),
729 GEM_STAT_TITLE_BITS(RXORCNT, "rx_overruns",
730 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXFIFOERR)),
731 GEM_STAT_TITLE_BITS(RXIPCCNT, "rx_ip_header_checksum_errors",
733 GEM_STAT_TITLE_BITS(RXTCPCCNT, "rx_tcp_checksum_errors",
735 GEM_STAT_TITLE_BITS(RXUDPCCNT, "rx_udp_checksum_errors",
739 #define GEM_STATS_LEN ARRAY_SIZE(gem_statistics)
743 struct macb_or_gem_ops {
744 int (*mog_alloc_rx_buffers)(struct macb *bp);
745 void (*mog_free_rx_buffers)(struct macb *bp);
746 void (*mog_init_rings)(struct macb *bp);
747 int (*mog_rx)(struct macb *bp, int budget);
752 unsigned int dma_burst_length;
765 unsigned int tx_head, tx_tail;
766 struct macb_dma_desc *tx_ring;
767 struct macb_tx_skb *tx_skb;
768 dma_addr_t tx_ring_dma;
769 struct work_struct tx_error_task;
775 unsigned int rx_tail;
776 unsigned int rx_prepared_head;
777 struct macb_dma_desc *rx_ring;
778 struct sk_buff **rx_skbuff;
780 size_t rx_buffer_size;
782 unsigned int num_queues;
783 struct macb_queue queues[MACB_MAX_QUEUES];
786 struct platform_device *pdev;
790 struct net_device *dev;
791 struct napi_struct napi;
792 struct net_device_stats stats;
794 struct macb_stats macb;
795 struct gem_stats gem;
798 dma_addr_t rx_ring_dma;
799 dma_addr_t rx_buffers_dma;
801 struct macb_or_gem_ops macbgem_ops;
803 struct mii_bus *mii_bus;
804 struct phy_device *phy_dev;
810 unsigned int dma_burst_length;
812 phy_interface_t phy_interface;
814 /* AT91RM9200 transmit */
815 struct sk_buff *skb; /* holds skb until xmit interrupt completes */
816 dma_addr_t skb_physaddr; /* phys addr from pci_map_single */
817 int skb_length; /* saved skb length for pci_unmap_single */
818 unsigned int max_tx_length;
820 u64 ethtool_stats[GEM_STATS_LEN];
823 extern const struct ethtool_ops macb_ethtool_ops;
825 int macb_mii_init(struct macb *bp);
826 int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
827 struct net_device_stats *macb_get_stats(struct net_device *dev);
828 void macb_set_rx_mode(struct net_device *dev);
829 void macb_set_hwaddr(struct macb *bp);
830 void macb_get_hwaddr(struct macb *bp);
832 static inline bool macb_is_gem(struct macb *bp)
834 return !!(bp->caps & MACB_CAPS_MACB_IS_GEM);
projects / linux-drm-fsl-dcu.git / blob