2 * Copyright © 2004 Texas Instruments, Jian Zhang <jzhang@ti.com>
3 * Copyright © 2004 Micron Technology Inc.
4 * Copyright © 2004 David Brownell
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #include <linux/platform_device.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/delay.h>
14 #include <linux/jiffies.h>
15 #include <linux/sched.h>
16 #include <linux/mtd/mtd.h>
17 #include <linux/mtd/nand.h>
18 #include <linux/mtd/partitions.h>
22 #include <plat/gpmc.h>
23 #include <plat/nand.h>
25 #define GPMC_IRQ_STATUS 0x18
26 #define GPMC_ECC_CONFIG 0x1F4
27 #define GPMC_ECC_CONTROL 0x1F8
28 #define GPMC_ECC_SIZE_CONFIG 0x1FC
29 #define GPMC_ECC1_RESULT 0x200
31 #define DRIVER_NAME "omap2-nand"
34 #define NAND_WP_BIT 0x00000010
36 #define GPMC_BUF_FULL 0x00000001
37 #define GPMC_BUF_EMPTY 0x00000000
39 #define NAND_Ecc_P1e (1 << 0)
40 #define NAND_Ecc_P2e (1 << 1)
41 #define NAND_Ecc_P4e (1 << 2)
42 #define NAND_Ecc_P8e (1 << 3)
43 #define NAND_Ecc_P16e (1 << 4)
44 #define NAND_Ecc_P32e (1 << 5)
45 #define NAND_Ecc_P64e (1 << 6)
46 #define NAND_Ecc_P128e (1 << 7)
47 #define NAND_Ecc_P256e (1 << 8)
48 #define NAND_Ecc_P512e (1 << 9)
49 #define NAND_Ecc_P1024e (1 << 10)
50 #define NAND_Ecc_P2048e (1 << 11)
52 #define NAND_Ecc_P1o (1 << 16)
53 #define NAND_Ecc_P2o (1 << 17)
54 #define NAND_Ecc_P4o (1 << 18)
55 #define NAND_Ecc_P8o (1 << 19)
56 #define NAND_Ecc_P16o (1 << 20)
57 #define NAND_Ecc_P32o (1 << 21)
58 #define NAND_Ecc_P64o (1 << 22)
59 #define NAND_Ecc_P128o (1 << 23)
60 #define NAND_Ecc_P256o (1 << 24)
61 #define NAND_Ecc_P512o (1 << 25)
62 #define NAND_Ecc_P1024o (1 << 26)
63 #define NAND_Ecc_P2048o (1 << 27)
65 #define TF(value) (value ? 1 : 0)
67 #define P2048e(a) (TF(a & NAND_Ecc_P2048e) << 0)
68 #define P2048o(a) (TF(a & NAND_Ecc_P2048o) << 1)
69 #define P1e(a) (TF(a & NAND_Ecc_P1e) << 2)
70 #define P1o(a) (TF(a & NAND_Ecc_P1o) << 3)
71 #define P2e(a) (TF(a & NAND_Ecc_P2e) << 4)
72 #define P2o(a) (TF(a & NAND_Ecc_P2o) << 5)
73 #define P4e(a) (TF(a & NAND_Ecc_P4e) << 6)
74 #define P4o(a) (TF(a & NAND_Ecc_P4o) << 7)
76 #define P8e(a) (TF(a & NAND_Ecc_P8e) << 0)
77 #define P8o(a) (TF(a & NAND_Ecc_P8o) << 1)
78 #define P16e(a) (TF(a & NAND_Ecc_P16e) << 2)
79 #define P16o(a) (TF(a & NAND_Ecc_P16o) << 3)
80 #define P32e(a) (TF(a & NAND_Ecc_P32e) << 4)
81 #define P32o(a) (TF(a & NAND_Ecc_P32o) << 5)
82 #define P64e(a) (TF(a & NAND_Ecc_P64e) << 6)
83 #define P64o(a) (TF(a & NAND_Ecc_P64o) << 7)
85 #define P128e(a) (TF(a & NAND_Ecc_P128e) << 0)
86 #define P128o(a) (TF(a & NAND_Ecc_P128o) << 1)
87 #define P256e(a) (TF(a & NAND_Ecc_P256e) << 2)
88 #define P256o(a) (TF(a & NAND_Ecc_P256o) << 3)
89 #define P512e(a) (TF(a & NAND_Ecc_P512e) << 4)
90 #define P512o(a) (TF(a & NAND_Ecc_P512o) << 5)
91 #define P1024e(a) (TF(a & NAND_Ecc_P1024e) << 6)
92 #define P1024o(a) (TF(a & NAND_Ecc_P1024o) << 7)
94 #define P8e_s(a) (TF(a & NAND_Ecc_P8e) << 0)
95 #define P8o_s(a) (TF(a & NAND_Ecc_P8o) << 1)
96 #define P16e_s(a) (TF(a & NAND_Ecc_P16e) << 2)
97 #define P16o_s(a) (TF(a & NAND_Ecc_P16o) << 3)
98 #define P1e_s(a) (TF(a & NAND_Ecc_P1e) << 4)
99 #define P1o_s(a) (TF(a & NAND_Ecc_P1o) << 5)
100 #define P2e_s(a) (TF(a & NAND_Ecc_P2e) << 6)
101 #define P2o_s(a) (TF(a & NAND_Ecc_P2o) << 7)
103 #define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0)
104 #define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1)
106 #ifdef CONFIG_MTD_PARTITIONS
107 static const char *part_probes[] = { "cmdlinepart", NULL };
110 #ifdef CONFIG_MTD_NAND_OMAP_PREFETCH
111 static int use_prefetch = 1;
113 /* "modprobe ... use_prefetch=0" etc */
114 module_param(use_prefetch, bool, 0);
115 MODULE_PARM_DESC(use_prefetch, "enable/disable use of PREFETCH");
117 #ifdef CONFIG_MTD_NAND_OMAP_PREFETCH_DMA
118 static int use_dma = 1;
120 /* "modprobe ... use_dma=0" etc */
121 module_param(use_dma, bool, 0);
122 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
127 const int use_prefetch;
131 struct omap_nand_info {
132 struct nand_hw_control controller;
133 struct omap_nand_platform_data *pdata;
135 struct mtd_partition *parts;
136 struct nand_chip nand;
137 struct platform_device *pdev;
140 unsigned long phys_base;
141 void __iomem *gpmc_cs_baseaddr;
142 void __iomem *gpmc_baseaddr;
143 void __iomem *nand_pref_fifo_add;
144 struct completion comp;
149 * omap_nand_wp - This function enable or disable the Write Protect feature
150 * @mtd: MTD device structure
153 static void omap_nand_wp(struct mtd_info *mtd, int mode)
155 struct omap_nand_info *info = container_of(mtd,
156 struct omap_nand_info, mtd);
158 unsigned long config = __raw_readl(info->gpmc_baseaddr + GPMC_CONFIG);
161 config &= ~(NAND_WP_BIT); /* WP is ON */
163 config |= (NAND_WP_BIT); /* WP is OFF */
165 __raw_writel(config, (info->gpmc_baseaddr + GPMC_CONFIG));
169 * omap_hwcontrol - hardware specific access to control-lines
170 * @mtd: MTD device structure
171 * @cmd: command to device
173 * NAND_NCE: bit 0 -> don't care
174 * NAND_CLE: bit 1 -> Command Latch
175 * NAND_ALE: bit 2 -> Address Latch
177 * NOTE: boards may use different bits for these!!
179 static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
181 struct omap_nand_info *info = container_of(mtd,
182 struct omap_nand_info, mtd);
184 case NAND_CTRL_CHANGE | NAND_CTRL_CLE:
185 info->nand.IO_ADDR_W = info->gpmc_cs_baseaddr +
186 GPMC_CS_NAND_COMMAND;
187 info->nand.IO_ADDR_R = info->gpmc_cs_baseaddr +
191 case NAND_CTRL_CHANGE | NAND_CTRL_ALE:
192 info->nand.IO_ADDR_W = info->gpmc_cs_baseaddr +
193 GPMC_CS_NAND_ADDRESS;
194 info->nand.IO_ADDR_R = info->gpmc_cs_baseaddr +
198 case NAND_CTRL_CHANGE | NAND_NCE:
199 info->nand.IO_ADDR_W = info->gpmc_cs_baseaddr +
201 info->nand.IO_ADDR_R = info->gpmc_cs_baseaddr +
206 if (cmd != NAND_CMD_NONE)
207 __raw_writeb(cmd, info->nand.IO_ADDR_W);
211 * omap_read_buf8 - read data from NAND controller into buffer
212 * @mtd: MTD device structure
213 * @buf: buffer to store date
214 * @len: number of bytes to read
216 static void omap_read_buf8(struct mtd_info *mtd, u_char *buf, int len)
218 struct nand_chip *nand = mtd->priv;
220 ioread8_rep(nand->IO_ADDR_R, buf, len);
224 * omap_write_buf8 - write buffer to NAND controller
225 * @mtd: MTD device structure
227 * @len: number of bytes to write
229 static void omap_write_buf8(struct mtd_info *mtd, const u_char *buf, int len)
231 struct omap_nand_info *info = container_of(mtd,
232 struct omap_nand_info, mtd);
233 u_char *p = (u_char *)buf;
236 iowrite8(*p++, info->nand.IO_ADDR_W);
237 while (GPMC_BUF_EMPTY == (readl(info->gpmc_baseaddr +
238 GPMC_STATUS) & GPMC_BUF_FULL));
243 * omap_read_buf16 - read data from NAND controller into buffer
244 * @mtd: MTD device structure
245 * @buf: buffer to store date
246 * @len: number of bytes to read
248 static void omap_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
250 struct nand_chip *nand = mtd->priv;
252 ioread16_rep(nand->IO_ADDR_R, buf, len / 2);
256 * omap_write_buf16 - write buffer to NAND controller
257 * @mtd: MTD device structure
259 * @len: number of bytes to write
261 static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len)
263 struct omap_nand_info *info = container_of(mtd,
264 struct omap_nand_info, mtd);
265 u16 *p = (u16 *) buf;
267 /* FIXME try bursts of writesw() or DMA ... */
271 iowrite16(*p++, info->nand.IO_ADDR_W);
273 while (GPMC_BUF_EMPTY == (readl(info->gpmc_baseaddr +
274 GPMC_STATUS) & GPMC_BUF_FULL))
280 * omap_read_buf_pref - read data from NAND controller into buffer
281 * @mtd: MTD device structure
282 * @buf: buffer to store date
283 * @len: number of bytes to read
285 static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len)
287 struct omap_nand_info *info = container_of(mtd,
288 struct omap_nand_info, mtd);
289 uint32_t pfpw_status = 0, r_count = 0;
293 /* take care of subpage reads */
295 if (info->nand.options & NAND_BUSWIDTH_16)
296 omap_read_buf16(mtd, buf, len % 4);
298 omap_read_buf8(mtd, buf, len % 4);
299 p = (u32 *) (buf + len % 4);
303 /* configure and start prefetch transfer */
304 ret = gpmc_prefetch_enable(info->gpmc_cs, 0x0, len, 0x0);
306 /* PFPW engine is busy, use cpu copy method */
307 if (info->nand.options & NAND_BUSWIDTH_16)
308 omap_read_buf16(mtd, buf, len);
310 omap_read_buf8(mtd, buf, len);
313 pfpw_status = gpmc_prefetch_status();
314 r_count = ((pfpw_status >> 24) & 0x7F) >> 2;
315 ioread32_rep(info->nand_pref_fifo_add, p, r_count);
320 /* disable and stop the PFPW engine */
321 gpmc_prefetch_reset();
326 * omap_write_buf_pref - write buffer to NAND controller
327 * @mtd: MTD device structure
329 * @len: number of bytes to write
331 static void omap_write_buf_pref(struct mtd_info *mtd,
332 const u_char *buf, int len)
334 struct omap_nand_info *info = container_of(mtd,
335 struct omap_nand_info, mtd);
336 uint32_t pfpw_status = 0, w_count = 0;
338 u16 *p = (u16 *) buf;
340 /* take care of subpage writes */
342 writeb(*buf, info->nand.IO_ADDR_R);
343 p = (u16 *)(buf + 1);
347 /* configure and start prefetch transfer */
348 ret = gpmc_prefetch_enable(info->gpmc_cs, 0x0, len, 0x1);
350 /* PFPW engine is busy, use cpu copy method */
351 if (info->nand.options & NAND_BUSWIDTH_16)
352 omap_write_buf16(mtd, buf, len);
354 omap_write_buf8(mtd, buf, len);
356 pfpw_status = gpmc_prefetch_status();
357 while (pfpw_status & 0x3FFF) {
358 w_count = ((pfpw_status >> 24) & 0x7F) >> 1;
359 for (i = 0; (i < w_count) && len; i++, len -= 2)
360 iowrite16(*p++, info->nand_pref_fifo_add);
361 pfpw_status = gpmc_prefetch_status();
364 /* disable and stop the PFPW engine */
365 gpmc_prefetch_reset();
369 #ifdef CONFIG_MTD_NAND_OMAP_PREFETCH_DMA
371 * omap_nand_dma_cb: callback on the completion of dma transfer
372 * @lch: logical channel
373 * @ch_satuts: channel status
374 * @data: pointer to completion data structure
376 static void omap_nand_dma_cb(int lch, u16 ch_status, void *data)
378 complete((struct completion *) data);
382 * omap_nand_dma_transfer: configer and start dma transfer
383 * @mtd: MTD device structure
384 * @addr: virtual address in RAM of source/destination
385 * @len: number of data bytes to be transferred
386 * @is_write: flag for read/write operation
388 static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
389 unsigned int len, int is_write)
391 struct omap_nand_info *info = container_of(mtd,
392 struct omap_nand_info, mtd);
393 uint32_t prefetch_status = 0;
394 enum dma_data_direction dir = is_write ? DMA_TO_DEVICE :
399 /* The fifo depth is 64 bytes. We have a sync at each frame and frame
400 * length is 64 bytes.
402 int buf_len = len >> 6;
404 if (addr >= high_memory) {
407 if (((size_t)addr & PAGE_MASK) !=
408 ((size_t)(addr + len - 1) & PAGE_MASK))
410 p1 = vmalloc_to_page(addr);
413 addr = page_address(p1) + ((size_t)addr & ~PAGE_MASK);
416 dma_addr = dma_map_single(&info->pdev->dev, addr, len, dir);
417 if (dma_mapping_error(&info->pdev->dev, dma_addr)) {
418 dev_err(&info->pdev->dev,
419 "Couldn't DMA map a %d byte buffer\n", len);
424 omap_set_dma_dest_params(info->dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
425 info->phys_base, 0, 0);
426 omap_set_dma_src_params(info->dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
428 omap_set_dma_transfer_params(info->dma_ch, OMAP_DMA_DATA_TYPE_S32,
429 0x10, buf_len, OMAP_DMA_SYNC_FRAME,
430 OMAP24XX_DMA_GPMC, OMAP_DMA_DST_SYNC);
432 omap_set_dma_src_params(info->dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
433 info->phys_base, 0, 0);
434 omap_set_dma_dest_params(info->dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
436 omap_set_dma_transfer_params(info->dma_ch, OMAP_DMA_DATA_TYPE_S32,
437 0x10, buf_len, OMAP_DMA_SYNC_FRAME,
438 OMAP24XX_DMA_GPMC, OMAP_DMA_SRC_SYNC);
440 /* configure and start prefetch transfer */
441 ret = gpmc_prefetch_enable(info->gpmc_cs, 0x1, len, is_write);
443 /* PFPW engine is busy, use cpu copy methode */
446 init_completion(&info->comp);
448 omap_start_dma(info->dma_ch);
450 /* setup and start DMA using dma_addr */
451 wait_for_completion(&info->comp);
453 while (0x3fff & (prefetch_status = gpmc_prefetch_status()))
455 /* disable and stop the PFPW engine */
456 gpmc_prefetch_reset();
458 dma_unmap_single(&info->pdev->dev, dma_addr, len, dir);
462 if (info->nand.options & NAND_BUSWIDTH_16)
463 is_write == 0 ? omap_read_buf16(mtd, (u_char *) addr, len)
464 : omap_write_buf16(mtd, (u_char *) addr, len);
466 is_write == 0 ? omap_read_buf8(mtd, (u_char *) addr, len)
467 : omap_write_buf8(mtd, (u_char *) addr, len);
471 static void omap_nand_dma_cb(int lch, u16 ch_status, void *data) {}
472 static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
473 unsigned int len, int is_write)
480 * omap_read_buf_dma_pref - read data from NAND controller into buffer
481 * @mtd: MTD device structure
482 * @buf: buffer to store date
483 * @len: number of bytes to read
485 static void omap_read_buf_dma_pref(struct mtd_info *mtd, u_char *buf, int len)
487 if (len <= mtd->oobsize)
488 omap_read_buf_pref(mtd, buf, len);
490 /* start transfer in DMA mode */
491 omap_nand_dma_transfer(mtd, buf, len, 0x0);
495 * omap_write_buf_dma_pref - write buffer to NAND controller
496 * @mtd: MTD device structure
498 * @len: number of bytes to write
500 static void omap_write_buf_dma_pref(struct mtd_info *mtd,
501 const u_char *buf, int len)
503 if (len <= mtd->oobsize)
504 omap_write_buf_pref(mtd, buf, len);
506 /* start transfer in DMA mode */
507 omap_nand_dma_transfer(mtd, (u_char *) buf, len, 0x1);
511 * omap_verify_buf - Verify chip data against buffer
512 * @mtd: MTD device structure
513 * @buf: buffer containing the data to compare
514 * @len: number of bytes to compare
516 static int omap_verify_buf(struct mtd_info *mtd, const u_char * buf, int len)
518 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
520 u16 *p = (u16 *) buf;
524 if (*p++ != cpu_to_le16(readw(info->nand.IO_ADDR_R)))
531 #ifdef CONFIG_MTD_NAND_OMAP_HWECC
533 * omap_hwecc_init - Initialize the HW ECC for NAND flash in GPMC controller
534 * @mtd: MTD device structure
536 static void omap_hwecc_init(struct mtd_info *mtd)
538 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
540 struct nand_chip *chip = mtd->priv;
541 unsigned long val = 0x0;
543 /* Read from ECC Control Register */
544 val = __raw_readl(info->gpmc_baseaddr + GPMC_ECC_CONTROL);
545 /* Clear all ECC | Enable Reg1 */
546 val = ((0x00000001<<8) | 0x00000001);
547 __raw_writel(val, info->gpmc_baseaddr + GPMC_ECC_CONTROL);
549 /* Read from ECC Size Config Register */
550 val = __raw_readl(info->gpmc_baseaddr + GPMC_ECC_SIZE_CONFIG);
551 /* ECCSIZE1=512 | Select eccResultsize[0-3] */
552 val = ((((chip->ecc.size >> 1) - 1) << 22) | (0x0000000F));
553 __raw_writel(val, info->gpmc_baseaddr + GPMC_ECC_SIZE_CONFIG);
557 * gen_true_ecc - This function will generate true ECC value
558 * @ecc_buf: buffer to store ecc code
560 * This generated true ECC value can be used when correcting
561 * data read from NAND flash memory core
563 static void gen_true_ecc(u8 *ecc_buf)
565 u32 tmp = ecc_buf[0] | (ecc_buf[1] << 16) |
566 ((ecc_buf[2] & 0xF0) << 20) | ((ecc_buf[2] & 0x0F) << 8);
568 ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) |
569 P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp));
570 ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) |
571 P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp));
572 ecc_buf[2] = ~(P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) |
573 P1e(tmp) | P2048o(tmp) | P2048e(tmp));
577 * omap_compare_ecc - Detect (2 bits) and correct (1 bit) error in data
578 * @ecc_data1: ecc code from nand spare area
579 * @ecc_data2: ecc code from hardware register obtained from hardware ecc
580 * @page_data: page data
582 * This function compares two ECC's and indicates if there is an error.
583 * If the error can be corrected it will be corrected to the buffer.
585 static int omap_compare_ecc(u8 *ecc_data1, /* read from NAND memory */
586 u8 *ecc_data2, /* read from register */
590 u8 tmp0_bit[8], tmp1_bit[8], tmp2_bit[8];
591 u8 comp0_bit[8], comp1_bit[8], comp2_bit[8];
598 isEccFF = ((*(u32 *)ecc_data1 & 0xFFFFFF) == 0xFFFFFF);
600 gen_true_ecc(ecc_data1);
601 gen_true_ecc(ecc_data2);
603 for (i = 0; i <= 2; i++) {
604 *(ecc_data1 + i) = ~(*(ecc_data1 + i));
605 *(ecc_data2 + i) = ~(*(ecc_data2 + i));
608 for (i = 0; i < 8; i++) {
609 tmp0_bit[i] = *ecc_data1 % 2;
610 *ecc_data1 = *ecc_data1 / 2;
613 for (i = 0; i < 8; i++) {
614 tmp1_bit[i] = *(ecc_data1 + 1) % 2;
615 *(ecc_data1 + 1) = *(ecc_data1 + 1) / 2;
618 for (i = 0; i < 8; i++) {
619 tmp2_bit[i] = *(ecc_data1 + 2) % 2;
620 *(ecc_data1 + 2) = *(ecc_data1 + 2) / 2;
623 for (i = 0; i < 8; i++) {
624 comp0_bit[i] = *ecc_data2 % 2;
625 *ecc_data2 = *ecc_data2 / 2;
628 for (i = 0; i < 8; i++) {
629 comp1_bit[i] = *(ecc_data2 + 1) % 2;
630 *(ecc_data2 + 1) = *(ecc_data2 + 1) / 2;
633 for (i = 0; i < 8; i++) {
634 comp2_bit[i] = *(ecc_data2 + 2) % 2;
635 *(ecc_data2 + 2) = *(ecc_data2 + 2) / 2;
638 for (i = 0; i < 6; i++)
639 ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2];
641 for (i = 0; i < 8; i++)
642 ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i];
644 for (i = 0; i < 8; i++)
645 ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i];
647 ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0];
648 ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1];
650 for (i = 0; i < 24; i++)
651 ecc_sum += ecc_bit[i];
655 /* Not reached because this function is not called if
656 * ECC values are equal
661 /* Uncorrectable error */
662 DEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n");
666 /* UN-Correctable error */
667 DEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR B\n");
671 /* Correctable error */
672 find_byte = (ecc_bit[23] << 8) +
682 find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1];
684 DEBUG(MTD_DEBUG_LEVEL0, "Correcting single bit ECC error at "
685 "offset: %d, bit: %d\n", find_byte, find_bit);
687 page_data[find_byte] ^= (1 << find_bit);
692 if (ecc_data2[0] == 0 &&
697 DEBUG(MTD_DEBUG_LEVEL0, "UNCORRECTED_ERROR default\n");
703 * omap_correct_data - Compares the ECC read with HW generated ECC
704 * @mtd: MTD device structure
706 * @read_ecc: ecc read from nand flash
707 * @calc_ecc: ecc read from HW ECC registers
709 * Compares the ecc read from nand spare area with ECC registers values
710 * and if ECC's mismached, it will call 'omap_compare_ecc' for error detection
713 static int omap_correct_data(struct mtd_info *mtd, u_char *dat,
714 u_char *read_ecc, u_char *calc_ecc)
716 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
718 int blockCnt = 0, i = 0, ret = 0;
720 /* Ex NAND_ECC_HW12_2048 */
721 if ((info->nand.ecc.mode == NAND_ECC_HW) &&
722 (info->nand.ecc.size == 2048))
727 for (i = 0; i < blockCnt; i++) {
728 if (memcmp(read_ecc, calc_ecc, 3) != 0) {
729 ret = omap_compare_ecc(read_ecc, calc_ecc, dat);
741 * omap_calcuate_ecc - Generate non-inverted ECC bytes.
742 * @mtd: MTD device structure
743 * @dat: The pointer to data on which ecc is computed
744 * @ecc_code: The ecc_code buffer
746 * Using noninverted ECC can be considered ugly since writing a blank
747 * page ie. padding will clear the ECC bytes. This is no problem as long
748 * nobody is trying to write data on the seemingly unused page. Reading
749 * an erased page will produce an ECC mismatch between generated and read
750 * ECC bytes that has to be dealt with separately.
752 static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
755 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
757 unsigned long val = 0x0;
760 /* Start Reading from HW ECC1_Result = 0x200 */
761 reg = (unsigned long)(info->gpmc_baseaddr + GPMC_ECC1_RESULT);
762 val = __raw_readl(reg);
763 *ecc_code++ = val; /* P128e, ..., P1e */
764 *ecc_code++ = val >> 16; /* P128o, ..., P1o */
765 /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
766 *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0);
773 * omap_enable_hwecc - This function enables the hardware ecc functionality
774 * @mtd: MTD device structure
775 * @mode: Read/Write mode
777 static void omap_enable_hwecc(struct mtd_info *mtd, int mode)
779 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
781 struct nand_chip *chip = mtd->priv;
782 unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
783 unsigned long val = __raw_readl(info->gpmc_baseaddr + GPMC_ECC_CONFIG);
787 __raw_writel(0x101, info->gpmc_baseaddr + GPMC_ECC_CONTROL);
788 /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */
789 val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1);
791 case NAND_ECC_READSYN:
792 __raw_writel(0x100, info->gpmc_baseaddr + GPMC_ECC_CONTROL);
793 /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */
794 val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1);
797 __raw_writel(0x101, info->gpmc_baseaddr + GPMC_ECC_CONTROL);
798 /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */
799 val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1);
802 DEBUG(MTD_DEBUG_LEVEL0, "Error: Unrecognized Mode[%d]!\n",
807 __raw_writel(val, info->gpmc_baseaddr + GPMC_ECC_CONFIG);
812 * omap_wait - wait until the command is done
813 * @mtd: MTD device structure
814 * @chip: NAND Chip structure
816 * Wait function is called during Program and erase operations and
817 * the way it is called from MTD layer, we should wait till the NAND
818 * chip is ready after the programming/erase operation has completed.
820 * Erase can take up to 400ms and program up to 20ms according to
821 * general NAND and SmartMedia specs
823 static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip)
825 struct nand_chip *this = mtd->priv;
826 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
828 unsigned long timeo = jiffies;
829 int status = NAND_STATUS_FAIL, state = this->state;
831 if (state == FL_ERASING)
832 timeo += (HZ * 400) / 1000;
834 timeo += (HZ * 20) / 1000;
836 this->IO_ADDR_W = (void *) info->gpmc_cs_baseaddr +
837 GPMC_CS_NAND_COMMAND;
838 this->IO_ADDR_R = (void *) info->gpmc_cs_baseaddr + GPMC_CS_NAND_DATA;
840 __raw_writeb(NAND_CMD_STATUS & 0xFF, this->IO_ADDR_W);
842 while (time_before(jiffies, timeo)) {
843 status = __raw_readb(this->IO_ADDR_R);
844 if (status & NAND_STATUS_READY)
852 * omap_dev_ready - calls the platform specific dev_ready function
853 * @mtd: MTD device structure
855 static int omap_dev_ready(struct mtd_info *mtd)
857 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
859 unsigned int val = __raw_readl(info->gpmc_baseaddr + GPMC_IRQ_STATUS);
861 if ((val & 0x100) == 0x100) {
862 /* Clear IRQ Interrupt */
865 __raw_writel(val, info->gpmc_baseaddr + GPMC_IRQ_STATUS);
867 unsigned int cnt = 0;
868 while (cnt++ < 0x1FF) {
869 if ((val & 0x100) == 0x100)
871 val = __raw_readl(info->gpmc_baseaddr +
879 static int __devinit omap_nand_probe(struct platform_device *pdev)
881 struct omap_nand_info *info;
882 struct omap_nand_platform_data *pdata;
885 pdata = pdev->dev.platform_data;
887 dev_err(&pdev->dev, "platform data missing\n");
891 info = kzalloc(sizeof(struct omap_nand_info), GFP_KERNEL);
895 platform_set_drvdata(pdev, info);
897 spin_lock_init(&info->controller.lock);
898 init_waitqueue_head(&info->controller.wq);
902 info->gpmc_cs = pdata->cs;
903 info->gpmc_baseaddr = pdata->gpmc_baseaddr;
904 info->gpmc_cs_baseaddr = pdata->gpmc_cs_baseaddr;
905 info->phys_base = pdata->phys_base;
907 info->mtd.priv = &info->nand;
908 info->mtd.name = dev_name(&pdev->dev);
909 info->mtd.owner = THIS_MODULE;
911 info->nand.options |= pdata->devsize ? NAND_BUSWIDTH_16 : 0;
912 info->nand.options |= NAND_SKIP_BBTSCAN;
914 /* NAND write protect off */
915 omap_nand_wp(&info->mtd, NAND_WP_OFF);
917 if (!request_mem_region(info->phys_base, NAND_IO_SIZE,
918 pdev->dev.driver->name)) {
923 info->nand.IO_ADDR_R = ioremap(info->phys_base, NAND_IO_SIZE);
924 if (!info->nand.IO_ADDR_R) {
926 goto out_release_mem_region;
929 info->nand.controller = &info->controller;
931 info->nand.IO_ADDR_W = info->nand.IO_ADDR_R;
932 info->nand.cmd_ctrl = omap_hwcontrol;
935 * If RDY/BSY line is connected to OMAP then use the omap ready
936 * funcrtion and the generic nand_wait function which reads the status
937 * register after monitoring the RDY/BSY line.Otherwise use a standard
938 * chip delay which is slightly more than tR (AC Timing) of the NAND
939 * device and read status register until you get a failure or success
941 if (pdata->dev_ready) {
942 info->nand.dev_ready = omap_dev_ready;
943 info->nand.chip_delay = 0;
945 info->nand.waitfunc = omap_wait;
946 info->nand.chip_delay = 50;
950 /* copy the virtual address of nand base for fifo access */
951 info->nand_pref_fifo_add = info->nand.IO_ADDR_R;
953 info->nand.read_buf = omap_read_buf_pref;
954 info->nand.write_buf = omap_write_buf_pref;
956 err = omap_request_dma(OMAP24XX_DMA_GPMC, "NAND",
957 omap_nand_dma_cb, &info->comp, &info->dma_ch);
960 printk(KERN_WARNING "DMA request failed."
961 " Non-dma data transfer mode\n");
963 omap_set_dma_dest_burst_mode(info->dma_ch,
964 OMAP_DMA_DATA_BURST_16);
965 omap_set_dma_src_burst_mode(info->dma_ch,
966 OMAP_DMA_DATA_BURST_16);
968 info->nand.read_buf = omap_read_buf_dma_pref;
969 info->nand.write_buf = omap_write_buf_dma_pref;
973 if (info->nand.options & NAND_BUSWIDTH_16) {
974 info->nand.read_buf = omap_read_buf16;
975 info->nand.write_buf = omap_write_buf16;
977 info->nand.read_buf = omap_read_buf8;
978 info->nand.write_buf = omap_write_buf8;
981 info->nand.verify_buf = omap_verify_buf;
983 #ifdef CONFIG_MTD_NAND_OMAP_HWECC
984 info->nand.ecc.bytes = 3;
985 info->nand.ecc.size = 512;
986 info->nand.ecc.calculate = omap_calculate_ecc;
987 info->nand.ecc.hwctl = omap_enable_hwecc;
988 info->nand.ecc.correct = omap_correct_data;
989 info->nand.ecc.mode = NAND_ECC_HW;
992 omap_hwecc_init(&info->mtd);
994 info->nand.ecc.mode = NAND_ECC_SOFT;
997 /* DIP switches on some boards change between 8 and 16 bit
998 * bus widths for flash. Try the other width if the first try fails.
1000 if (nand_scan(&info->mtd, 1)) {
1001 info->nand.options ^= NAND_BUSWIDTH_16;
1002 if (nand_scan(&info->mtd, 1)) {
1004 goto out_release_mem_region;
1008 #ifdef CONFIG_MTD_PARTITIONS
1009 err = parse_mtd_partitions(&info->mtd, part_probes, &info->parts, 0);
1011 add_mtd_partitions(&info->mtd, info->parts, err);
1012 else if (pdata->parts)
1013 add_mtd_partitions(&info->mtd, pdata->parts, pdata->nr_parts);
1016 add_mtd_device(&info->mtd);
1018 platform_set_drvdata(pdev, &info->mtd);
1022 out_release_mem_region:
1023 release_mem_region(info->phys_base, NAND_IO_SIZE);
1030 static int omap_nand_remove(struct platform_device *pdev)
1032 struct mtd_info *mtd = platform_get_drvdata(pdev);
1033 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1036 platform_set_drvdata(pdev, NULL);
1038 omap_free_dma(info->dma_ch);
1040 /* Release NAND device, its internal structures and partitions */
1041 nand_release(&info->mtd);
1042 iounmap(info->nand_pref_fifo_add);
1047 static struct platform_driver omap_nand_driver = {
1048 .probe = omap_nand_probe,
1049 .remove = omap_nand_remove,
1051 .name = DRIVER_NAME,
1052 .owner = THIS_MODULE,
1056 static int __init omap_nand_init(void)
1058 printk(KERN_INFO "%s driver initializing\n", DRIVER_NAME);
1060 /* This check is required if driver is being
1061 * loaded run time as a module
1063 if ((1 == use_dma) && (0 == use_prefetch)) {
1064 printk(KERN_INFO"Wrong parameters: 'use_dma' can not be 1 "
1065 "without use_prefetch'. Prefetch will not be"
1066 " used in either mode (mpu or dma)\n");
1068 return platform_driver_register(&omap_nand_driver);
1071 static void __exit omap_nand_exit(void)
1073 platform_driver_unregister(&omap_nand_driver);
1076 module_init(omap_nand_init);
1077 module_exit(omap_nand_exit);
1079 MODULE_ALIAS(DRIVER_NAME);
1080 MODULE_LICENSE("GPL");
1081 MODULE_DESCRIPTION("Glue layer for NAND flash on TI OMAP boards");