drivers/memory/omap-gpmc.c

   1 /*
   2  * GPMC support functions
   3  *
   4  * Copyright (C) 2005-2006 Nokia Corporation
   5  *
   6  * Author: Juha Yrjola
   7  *
   8  * Copyright (C) 2009 Texas Instruments
   9  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15 #include <linux/irq.h>
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/err.h>
  19 #include <linux/clk.h>
  20 #include <linux/ioport.h>
  21 #include <linux/spinlock.h>
  22 #include <linux/io.h>
  23 #include <linux/module.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/of.h>
  27 #include <linux/of_address.h>
  28 #include <linux/of_mtd.h>
  29 #include <linux/of_device.h>
  30 #include <linux/of_platform.h>
  31 #include <linux/omap-gpmc.h>
  32 #include <linux/mtd/nand.h>
  33 #include <linux/pm_runtime.h>
  34
  35 #include <linux/platform_data/mtd-nand-omap2.h>
  36 #include <linux/platform_data/mtd-onenand-omap2.h>
  37
  38 #include <asm/mach-types.h>
  39
  40 #define DEVICE_NAME             "omap-gpmc"
  41
  42 /* GPMC register offsets */
  43 #define GPMC_REVISION           0x00
  44 #define GPMC_SYSCONFIG          0x10
  45 #define GPMC_SYSSTATUS          0x14
  46 #define GPMC_IRQSTATUS          0x18
  47 #define GPMC_IRQENABLE          0x1c
  48 #define GPMC_TIMEOUT_CONTROL    0x40
  49 #define GPMC_ERR_ADDRESS        0x44
  50 #define GPMC_ERR_TYPE           0x48
  51 #define GPMC_CONFIG             0x50
  52 #define GPMC_STATUS             0x54
  53 #define GPMC_PREFETCH_CONFIG1   0x1e0
  54 #define GPMC_PREFETCH_CONFIG2   0x1e4
  55 #define GPMC_PREFETCH_CONTROL   0x1ec
  56 #define GPMC_PREFETCH_STATUS    0x1f0
  57 #define GPMC_ECC_CONFIG         0x1f4
  58 #define GPMC_ECC_CONTROL        0x1f8
  59 #define GPMC_ECC_SIZE_CONFIG    0x1fc
  60 #define GPMC_ECC1_RESULT        0x200
  61 #define GPMC_ECC_BCH_RESULT_0   0x240   /* not available on OMAP2 */
  62 #define GPMC_ECC_BCH_RESULT_1   0x244   /* not available on OMAP2 */
  63 #define GPMC_ECC_BCH_RESULT_2   0x248   /* not available on OMAP2 */
  64 #define GPMC_ECC_BCH_RESULT_3   0x24c   /* not available on OMAP2 */
  65 #define GPMC_ECC_BCH_RESULT_4   0x300   /* not available on OMAP2 */
  66 #define GPMC_ECC_BCH_RESULT_5   0x304   /* not available on OMAP2 */
  67 #define GPMC_ECC_BCH_RESULT_6   0x308   /* not available on OMAP2 */
  68
  69 /* GPMC ECC control settings */
  70 #define GPMC_ECC_CTRL_ECCCLEAR          0x100
  71 #define GPMC_ECC_CTRL_ECCDISABLE        0x000
  72 #define GPMC_ECC_CTRL_ECCREG1           0x001
  73 #define GPMC_ECC_CTRL_ECCREG2           0x002
  74 #define GPMC_ECC_CTRL_ECCREG3           0x003
  75 #define GPMC_ECC_CTRL_ECCREG4           0x004
  76 #define GPMC_ECC_CTRL_ECCREG5           0x005
  77 #define GPMC_ECC_CTRL_ECCREG6           0x006
  78 #define GPMC_ECC_CTRL_ECCREG7           0x007
  79 #define GPMC_ECC_CTRL_ECCREG8           0x008
  80 #define GPMC_ECC_CTRL_ECCREG9           0x009
  81
  82 #define GPMC_CONFIG_LIMITEDADDRESS              BIT(1)
  83
  84 #define GPMC_CONFIG2_CSEXTRADELAY               BIT(7)
  85 #define GPMC_CONFIG3_ADVEXTRADELAY              BIT(7)
  86 #define GPMC_CONFIG4_OEEXTRADELAY               BIT(7)
  87 #define GPMC_CONFIG4_WEEXTRADELAY               BIT(23)
  88 #define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN        BIT(6)
  89 #define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN        BIT(7)
  90
  91 #define GPMC_CS0_OFFSET         0x60
  92 #define GPMC_CS_SIZE            0x30
  93 #define GPMC_BCH_SIZE           0x10
  94
  95 #define GPMC_MEM_END            0x3FFFFFFF
  96
  97 #define GPMC_CHUNK_SHIFT        24              /* 16 MB */
  98 #define GPMC_SECTION_SHIFT      28              /* 128 MB */
  99
 100 #define CS_NUM_SHIFT            24
 101 #define ENABLE_PREFETCH         (0x1 << 7)
 102 #define DMA_MPU_MODE            2
 103
 104 #define GPMC_REVISION_MAJOR(l)          ((l >> 4) & 0xf)
 105 #define GPMC_REVISION_MINOR(l)          (l & 0xf)
 106
 107 #define GPMC_HAS_WR_ACCESS              0x1
 108 #define GPMC_HAS_WR_DATA_MUX_BUS        0x2
 109 #define GPMC_HAS_MUX_AAD                0x4
 110
 111 #define GPMC_NR_WAITPINS                4
 112
 113 #define GPMC_CS_CONFIG1         0x00
 114 #define GPMC_CS_CONFIG2         0x04
 115 #define GPMC_CS_CONFIG3         0x08
 116 #define GPMC_CS_CONFIG4         0x0c
 117 #define GPMC_CS_CONFIG5         0x10
 118 #define GPMC_CS_CONFIG6         0x14
 119 #define GPMC_CS_CONFIG7         0x18
 120 #define GPMC_CS_NAND_COMMAND    0x1c
 121 #define GPMC_CS_NAND_ADDRESS    0x20
 122 #define GPMC_CS_NAND_DATA       0x24
 123
 124 /* Control Commands */
 125 #define GPMC_CONFIG_RDY_BSY     0x00000001
 126 #define GPMC_CONFIG_DEV_SIZE    0x00000002
 127 #define GPMC_CONFIG_DEV_TYPE    0x00000003
 128 #define GPMC_SET_IRQ_STATUS     0x00000004
 129
 130 #define GPMC_CONFIG1_WRAPBURST_SUPP     (1 << 31)
 131 #define GPMC_CONFIG1_READMULTIPLE_SUPP  (1 << 30)
 132 #define GPMC_CONFIG1_READTYPE_ASYNC     (0 << 29)
 133 #define GPMC_CONFIG1_READTYPE_SYNC      (1 << 29)
 134 #define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
 135 #define GPMC_CONFIG1_WRITETYPE_ASYNC    (0 << 27)
 136 #define GPMC_CONFIG1_WRITETYPE_SYNC     (1 << 27)
 137 #define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25)
 138 /** CLKACTIVATIONTIME Max Ticks */
 139 #define GPMC_CONFIG1_CLKACTIVATIONTIME_MAX 2
 140 #define GPMC_CONFIG1_PAGE_LEN(val)      ((val & 3) << 23)
 141 /** ATTACHEDDEVICEPAGELENGTH Max Value */
 142 #define GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX 2
 143 #define GPMC_CONFIG1_WAIT_READ_MON      (1 << 22)
 144 #define GPMC_CONFIG1_WAIT_WRITE_MON     (1 << 21)
 145 #define GPMC_CONFIG1_WAIT_MON_TIME(val) ((val & 3) << 18)
 146 /** WAITMONITORINGTIME Max Ticks */
 147 #define GPMC_CONFIG1_WAITMONITORINGTIME_MAX  2
 148 #define GPMC_CONFIG1_WAIT_PIN_SEL(val)  ((val & 3) << 16)
 149 #define GPMC_CONFIG1_DEVICESIZE(val)    ((val & 3) << 12)
 150 #define GPMC_CONFIG1_DEVICESIZE_16      GPMC_CONFIG1_DEVICESIZE(1)
 151 /** DEVICESIZE Max Value */
 152 #define GPMC_CONFIG1_DEVICESIZE_MAX     1
 153 #define GPMC_CONFIG1_DEVICETYPE(val)    ((val & 3) << 10)
 154 #define GPMC_CONFIG1_DEVICETYPE_NOR     GPMC_CONFIG1_DEVICETYPE(0)
 155 #define GPMC_CONFIG1_MUXTYPE(val)       ((val & 3) << 8)
 156 #define GPMC_CONFIG1_TIME_PARA_GRAN     (1 << 4)
 157 #define GPMC_CONFIG1_FCLK_DIV(val)      (val & 3)
 158 #define GPMC_CONFIG1_FCLK_DIV2          (GPMC_CONFIG1_FCLK_DIV(1))
 159 #define GPMC_CONFIG1_FCLK_DIV3          (GPMC_CONFIG1_FCLK_DIV(2))
 160 #define GPMC_CONFIG1_FCLK_DIV4          (GPMC_CONFIG1_FCLK_DIV(3))
 161 #define GPMC_CONFIG7_CSVALID            (1 << 6)
 162
 163 #define GPMC_CONFIG7_BASEADDRESS_MASK   0x3f
 164 #define GPMC_CONFIG7_CSVALID_MASK       BIT(6)
 165 #define GPMC_CONFIG7_MASKADDRESS_OFFSET 8
 166 #define GPMC_CONFIG7_MASKADDRESS_MASK   (0xf << GPMC_CONFIG7_MASKADDRESS_OFFSET)
 167 /* All CONFIG7 bits except reserved bits */
 168 #define GPMC_CONFIG7_MASK               (GPMC_CONFIG7_BASEADDRESS_MASK | \
 169                                          GPMC_CONFIG7_CSVALID_MASK |     \
 170                                          GPMC_CONFIG7_MASKADDRESS_MASK)
 171
 172 #define GPMC_DEVICETYPE_NOR             0
 173 #define GPMC_DEVICETYPE_NAND            2
 174 #define GPMC_CONFIG_WRITEPROTECT        0x00000010
 175 #define WR_RD_PIN_MONITORING            0x00600000
 176
 177 #define GPMC_ENABLE_IRQ         0x0000000d
 178
 179 /* ECC commands */
 180 #define GPMC_ECC_READ           0 /* Reset Hardware ECC for read */
 181 #define GPMC_ECC_WRITE          1 /* Reset Hardware ECC for write */
 182 #define GPMC_ECC_READSYN        2 /* Reset before syndrom is read back */
 183
 184 /* XXX: Only NAND irq has been considered,currently these are the only ones used
 185  */
 186 #define GPMC_NR_IRQ             2
 187
 188 enum gpmc_clk_domain {
 189         GPMC_CD_FCLK,
 190         GPMC_CD_CLK
 191 };
 192
 193 struct gpmc_cs_data {
 194         const char *name;
 195
 196 #define GPMC_CS_RESERVED        (1 << 0)
 197         u32 flags;
 198
 199         struct resource mem;
 200 };
 201
 202 struct gpmc_client_irq  {
 203         unsigned                irq;
 204         u32                     bitmask;
 205 };
 206
 207 /* Structure to save gpmc cs context */
 208 struct gpmc_cs_config {
 209         u32 config1;
 210         u32 config2;
 211         u32 config3;
 212         u32 config4;
 213         u32 config5;
 214         u32 config6;
 215         u32 config7;
 216         int is_valid;
 217 };
 218
 219 /*
 220  * Structure to save/restore gpmc context
 221  * to support core off on OMAP3
 222  */
 223 struct omap3_gpmc_regs {
 224         u32 sysconfig;
 225         u32 irqenable;
 226         u32 timeout_ctrl;
 227         u32 config;
 228         u32 prefetch_config1;
 229         u32 prefetch_config2;
 230         u32 prefetch_control;
 231         struct gpmc_cs_config cs_context[GPMC_CS_NUM];
 232 };
 233
 234 static struct gpmc_client_irq gpmc_client_irq[GPMC_NR_IRQ];
 235 static struct irq_chip gpmc_irq_chip;
 236 static int gpmc_irq_start;
 237
 238 static struct resource  gpmc_mem_root;
 239 static struct gpmc_cs_data gpmc_cs[GPMC_CS_NUM];
 240 static DEFINE_SPINLOCK(gpmc_mem_lock);
 241 /* Define chip-selects as reserved by default until probe completes */
 242 static unsigned int gpmc_cs_num = GPMC_CS_NUM;
 243 static unsigned int gpmc_nr_waitpins;
 244 static struct device *gpmc_dev;
 245 static int gpmc_irq;
 246 static resource_size_t phys_base, mem_size;
 247 static unsigned gpmc_capability;
 248 static void __iomem *gpmc_base;
 249
 250 static struct clk *gpmc_l3_clk;
 251
 252 static irqreturn_t gpmc_handle_irq(int irq, void *dev);
 253
 254 static void gpmc_write_reg(int idx, u32 val)
 255 {
 256         writel_relaxed(val, gpmc_base + idx);
 257 }
 258
 259 static u32 gpmc_read_reg(int idx)
 260 {
 261         return readl_relaxed(gpmc_base + idx);
 262 }
 263
 264 void gpmc_cs_write_reg(int cs, int idx, u32 val)
 265 {
 266         void __iomem *reg_addr;
 267
 268         reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
 269         writel_relaxed(val, reg_addr);
 270 }
 271
 272 static u32 gpmc_cs_read_reg(int cs, int idx)
 273 {
 274         void __iomem *reg_addr;
 275
 276         reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
 277         return readl_relaxed(reg_addr);
 278 }
 279
 280 /* TODO: Add support for gpmc_fck to clock framework and use it */
 281 static unsigned long gpmc_get_fclk_period(void)
 282 {
 283         unsigned long rate = clk_get_rate(gpmc_l3_clk);
 284
 285         rate /= 1000;
 286         rate = 1000000000 / rate;       /* In picoseconds */
 287
 288         return rate;
 289 }
 290
 291 /**
 292  * gpmc_get_clk_period - get period of selected clock domain in ps
 293  * @cs Chip Select Region.
 294  * @cd Clock Domain.
 295  *
 296  * GPMC_CS_CONFIG1 GPMCFCLKDIVIDER for cs has to be setup
 297  * prior to calling this function with GPMC_CD_CLK.
 298  */
 299 static unsigned long gpmc_get_clk_period(int cs, enum gpmc_clk_domain cd)
 300 {
 301
 302         unsigned long tick_ps = gpmc_get_fclk_period();
 303         u32 l;
 304         int div;
 305
 306         switch (cd) {
 307         case GPMC_CD_CLK:
 308                 /* get current clk divider */
 309                 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
 310                 div = (l & 0x03) + 1;
 311                 /* get GPMC_CLK period */
 312                 tick_ps *= div;
 313                 break;
 314         case GPMC_CD_FCLK:
 315                 /* FALL-THROUGH */
 316         default:
 317                 break;
 318         }
 319
 320         return tick_ps;
 321
 322 }
 323
 324 static unsigned int gpmc_ns_to_clk_ticks(unsigned int time_ns, int cs,
 325                                          enum gpmc_clk_domain cd)
 326 {
 327         unsigned long tick_ps;
 328
 329         /* Calculate in picosecs to yield more exact results */
 330         tick_ps = gpmc_get_clk_period(cs, cd);
 331
 332         return (time_ns * 1000 + tick_ps - 1) / tick_ps;
 333 }
 334
 335 static unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
 336 {
 337         return gpmc_ns_to_clk_ticks(time_ns, /* any CS */ 0, GPMC_CD_FCLK);
 338 }
 339
 340 static unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
 341 {
 342         unsigned long tick_ps;
 343
 344         /* Calculate in picosecs to yield more exact results */
 345         tick_ps = gpmc_get_fclk_period();
 346
 347         return (time_ps + tick_ps - 1) / tick_ps;
 348 }
 349
 350 unsigned int gpmc_clk_ticks_to_ns(unsigned ticks, int cs,
 351                                   enum gpmc_clk_domain cd)
 352 {
 353         return ticks * gpmc_get_clk_period(cs, cd) / 1000;
 354 }
 355
 356 unsigned int gpmc_ticks_to_ns(unsigned int ticks)
 357 {
 358         return gpmc_clk_ticks_to_ns(ticks, /* any CS */ 0, GPMC_CD_FCLK);
 359 }
 360
 361 static unsigned int gpmc_ticks_to_ps(unsigned int ticks)
 362 {
 363         return ticks * gpmc_get_fclk_period();
 364 }
 365
 366 static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps)
 367 {
 368         unsigned long ticks = gpmc_ps_to_ticks(time_ps);
 369
 370         return ticks * gpmc_get_fclk_period();
 371 }
 372
 373 static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value)
 374 {
 375         u32 l;
 376
 377         l = gpmc_cs_read_reg(cs, reg);
 378         if (value)
 379                 l |= mask;
 380         else
 381                 l &= ~mask;
 382         gpmc_cs_write_reg(cs, reg, l);
 383 }
 384
 385 static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
 386 {
 387         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1,
 388                            GPMC_CONFIG1_TIME_PARA_GRAN,
 389                            p->time_para_granularity);
 390         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2,
 391                            GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay);
 392         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3,
 393                            GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay);
 394         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
 395                            GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay);
 396         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
 397                            GPMC_CONFIG4_OEEXTRADELAY, p->we_extra_delay);
 398         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
 399                            GPMC_CONFIG6_CYCLE2CYCLESAMECSEN,
 400                            p->cycle2cyclesamecsen);
 401         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
 402                            GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN,
 403                            p->cycle2cyclediffcsen);
 404 }
 405
 406 #ifdef CONFIG_OMAP_GPMC_DEBUG
 407 /**
 408  * get_gpmc_timing_reg - read a timing parameter and print DTS settings for it.
 409  * @cs:      Chip Select Region
 410  * @reg:     GPMC_CS_CONFIGn register offset.
 411  * @st_bit:  Start Bit
 412  * @end_bit: End Bit. Must be >= @st_bit.
 413  * @ma:x     Maximum parameter value (before optional @shift).
 414  *           If 0, maximum is as high as @st_bit and @end_bit allow.
 415  * @name:    DTS node name, w/o "gpmc,"
 416  * @cd:      Clock Domain of timing parameter.
 417  * @shift:   Parameter value left shifts @shift, which is then printed instead of value.
 418  * @raw:     Raw Format Option.
 419  *           raw format:  gpmc,name = <value>
 420  *           tick format: gpmc,name = <value> /&zwj;* x ns -- y ns; x ticks *&zwj;/
 421  *           Where x ns -- y ns result in the same tick value.
 422  *           When @max is exceeded, "invalid" is printed inside comment.
 423  * @noval:   Parameter values equal to 0 are not printed.
 424  * @return:  Specified timing parameter (after optional @shift).
 425  *
 426  */
 427 static int get_gpmc_timing_reg(
 428         /* timing specifiers */
 429         int cs, int reg, int st_bit, int end_bit, int max,
 430         const char *name, const enum gpmc_clk_domain cd,
 431         /* value transform */
 432         int shift,
 433         /* format specifiers */
 434         bool raw, bool noval)
 435 {
 436         u32 l;
 437         int nr_bits;
 438         int mask;
 439         bool invalid;
 440
 441         l = gpmc_cs_read_reg(cs, reg);
 442         nr_bits = end_bit - st_bit + 1;
 443         mask = (1 << nr_bits) - 1;
 444         l = (l >> st_bit) & mask;
 445         if (!max)
 446                 max = mask;
 447         invalid = l > max;
 448         if (shift)
 449                 l = (shift << l);
 450         if (noval && (l == 0))
 451                 return 0;
 452         if (!raw) {
 453                 /* DTS tick format for timings in ns */
 454                 unsigned int time_ns;
 455                 unsigned int time_ns_min = 0;
 456
 457                 if (l)
 458                         time_ns_min = gpmc_clk_ticks_to_ns(l - 1, cs, cd) + 1;
 459                 time_ns = gpmc_clk_ticks_to_ns(l, cs, cd);
 460                 pr_info("gpmc,%s = <%u> /* %u ns - %u ns; %i ticks%s*/\n",
 461                         name, time_ns, time_ns_min, time_ns, l,
 462                         invalid ? "; invalid " : " ");
 463         } else {
 464                 /* raw format */
 465                 pr_info("gpmc,%s = <%u>%s\n", name, l,
 466                         invalid ? " /* invalid */" : "");
 467         }
 468
 469         return l;
 470 }
 471
 472 #define GPMC_PRINT_CONFIG(cs, config) \
 473         pr_info("cs%i %s: 0x%08x\n", cs, #config, \
 474                 gpmc_cs_read_reg(cs, config))
 475 #define GPMC_GET_RAW(reg, st, end, field) \
 476         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 0)
 477 #define GPMC_GET_RAW_MAX(reg, st, end, max, field) \
 478         get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, 0, 1, 0)
 479 #define GPMC_GET_RAW_BOOL(reg, st, end, field) \
 480         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 1)
 481 #define GPMC_GET_RAW_SHIFT_MAX(reg, st, end, shift, max, field) \
 482         get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, (shift), 1, 1)
 483 #define GPMC_GET_TICKS(reg, st, end, field) \
 484         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 0, 0)
 485 #define GPMC_GET_TICKS_CD(reg, st, end, field, cd) \
 486         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, (cd), 0, 0, 0)
 487 #define GPMC_GET_TICKS_CD_MAX(reg, st, end, max, field, cd) \
 488         get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, (cd), 0, 0, 0)
 489
 490 static void gpmc_show_regs(int cs, const char *desc)
 491 {
 492         pr_info("gpmc cs%i %s:\n", cs, desc);
 493         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG1);
 494         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG2);
 495         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG3);
 496         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG4);
 497         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG5);
 498         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG6);
 499 }
 500
 501 /*
 502  * Note that gpmc,wait-pin handing wrongly assumes bit 8 is available,
 503  * see commit c9fb809.
 504  */
 505 static void gpmc_cs_show_timings(int cs, const char *desc)
 506 {
 507         gpmc_show_regs(cs, desc);
 508
 509         pr_info("gpmc cs%i access configuration:\n", cs);
 510         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1,  4,  4, "time-para-granularity");
 511         GPMC_GET_RAW(GPMC_CS_CONFIG1,  8,  9, "mux-add-data");
 512         GPMC_GET_RAW_MAX(GPMC_CS_CONFIG1, 12, 13,
 513                          GPMC_CONFIG1_DEVICESIZE_MAX, "device-width");
 514         GPMC_GET_RAW(GPMC_CS_CONFIG1, 16, 17, "wait-pin");
 515         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 21, 21, "wait-on-write");
 516         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 22, 22, "wait-on-read");
 517         GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 23, 24, 4,
 518                                GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX,
 519                                "burst-length");
 520         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 27, 27, "sync-write");
 521         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 28, 28, "burst-write");
 522         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 29, 29, "gpmc,sync-read");
 523         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 30, 30, "burst-read");
 524         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 31, 31, "burst-wrap");
 525
 526         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG2,  7,  7, "cs-extra-delay");
 527
 528         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG3,  7,  7, "adv-extra-delay");
 529
 530         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 23, 23, "we-extra-delay");
 531         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4,  7,  7, "oe-extra-delay");
 532
 533         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6,  7,  7, "cycle2cycle-samecsen");
 534         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6,  6,  6, "cycle2cycle-diffcsen");
 535
 536         pr_info("gpmc cs%i timings configuration:\n", cs);
 537         GPMC_GET_TICKS(GPMC_CS_CONFIG2,  0,  3, "cs-on-ns");
 538         GPMC_GET_TICKS(GPMC_CS_CONFIG2,  8, 12, "cs-rd-off-ns");
 539         GPMC_GET_TICKS(GPMC_CS_CONFIG2, 16, 20, "cs-wr-off-ns");
 540
 541         GPMC_GET_TICKS(GPMC_CS_CONFIG3,  0,  3, "adv-on-ns");
 542         GPMC_GET_TICKS(GPMC_CS_CONFIG3,  8, 12, "adv-rd-off-ns");
 543         GPMC_GET_TICKS(GPMC_CS_CONFIG3, 16, 20, "adv-wr-off-ns");
 544
 545         GPMC_GET_TICKS(GPMC_CS_CONFIG4,  0,  3, "oe-on-ns");
 546         GPMC_GET_TICKS(GPMC_CS_CONFIG4,  8, 12, "oe-off-ns");
 547         GPMC_GET_TICKS(GPMC_CS_CONFIG4, 16, 19, "we-on-ns");
 548         GPMC_GET_TICKS(GPMC_CS_CONFIG4, 24, 28, "we-off-ns");
 549
 550         GPMC_GET_TICKS(GPMC_CS_CONFIG5,  0,  4, "rd-cycle-ns");
 551         GPMC_GET_TICKS(GPMC_CS_CONFIG5,  8, 12, "wr-cycle-ns");
 552         GPMC_GET_TICKS(GPMC_CS_CONFIG5, 16, 20, "access-ns");
 553
 554         GPMC_GET_TICKS(GPMC_CS_CONFIG5, 24, 27, "page-burst-access-ns");
 555
 556         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 0, 3, "bus-turnaround-ns");
 557         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 8, 11, "cycle2cycle-delay-ns");
 558
 559         GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 18, 19,
 560                               GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
 561                               "wait-monitoring-ns", GPMC_CD_CLK);
 562         GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 25, 26,
 563                               GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
 564                               "clk-activation-ns", GPMC_CD_FCLK);
 565
 566         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 16, 19, "wr-data-mux-bus-ns");
 567         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 24, 28, "wr-access-ns");
 568 }
 569 #else
 570 static inline void gpmc_cs_show_timings(int cs, const char *desc)
 571 {
 572 }
 573 #endif
 574
 575 /**
 576  * set_gpmc_timing_reg - set a single timing parameter for Chip Select Region.
 577  * Caller is expected to have initialized CONFIG1 GPMCFCLKDIVIDER
 578  * prior to calling this function with @cd equal to GPMC_CD_CLK.
 579  *
 580  * @cs:      Chip Select Region.
 581  * @reg:     GPMC_CS_CONFIGn register offset.
 582  * @st_bit:  Start Bit
 583  * @end_bit: End Bit. Must be >= @st_bit.
 584  * @max:     Maximum parameter value.
 585  *           If 0, maximum is as high as @st_bit and @end_bit allow.
 586  * @time:    Timing parameter in ns.
 587  * @cd:      Timing parameter clock domain.
 588  * @name:    Timing parameter name.
 589  * @return:  0 on success, -1 on error.
 590  */
 591 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int max,
 592                                int time, enum gpmc_clk_domain cd, const char *name)
 593 {
 594         u32 l;
 595         int ticks, mask, nr_bits;
 596
 597         if (time == 0)
 598                 ticks = 0;
 599         else
 600                 ticks = gpmc_ns_to_clk_ticks(time, cs, cd);
 601         nr_bits = end_bit - st_bit + 1;
 602         mask = (1 << nr_bits) - 1;
 603
 604         if (!max)
 605                 max = mask;
 606
 607         if (ticks > max) {
 608                 pr_err("%s: GPMC CS%d: %s %d ns, %d ticks > %d ticks\n",
 609                        __func__, cs, name, time, ticks, max);
 610
 611                 return -1;
 612         }
 613
 614         l = gpmc_cs_read_reg(cs, reg);
 615 #ifdef CONFIG_OMAP_GPMC_DEBUG
 616         pr_info(
 617                 "GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
 618                cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000,
 619                         (l >> st_bit) & mask, time);
 620 #endif
 621         l &= ~(mask << st_bit);
 622         l |= ticks << st_bit;
 623         gpmc_cs_write_reg(cs, reg, l);
 624
 625         return 0;
 626 }
 627
 628 #define GPMC_SET_ONE_CD_MAX(reg, st, end, max, field, cd)  \
 629         if (set_gpmc_timing_reg(cs, (reg), (st), (end), (max), \
 630             t->field, (cd), #field) < 0)                       \
 631                 return -1
 632
 633 #define GPMC_SET_ONE(reg, st, end, field) \
 634         GPMC_SET_ONE_CD_MAX(reg, st, end, 0, field, GPMC_CD_FCLK)
 635
 636 /**
 637  * gpmc_calc_waitmonitoring_divider - calculate proper GPMCFCLKDIVIDER based on WAITMONITORINGTIME
 638  * WAITMONITORINGTIME will be _at least_ as long as desired, i.e.
 639  * read  --> don't sample bus too early
 640  * write --> data is longer on bus
 641  *
 642  * Formula:
 643  * gpmc_clk_div + 1 = ceil(ceil(waitmonitoringtime_ns / gpmc_fclk_ns)
 644  *                    / waitmonitoring_ticks)
 645  * WAITMONITORINGTIME resulting in 0 or 1 tick with div = 1 are caught by
 646  * div <= 0 check.
 647  *
 648  * @wait_monitoring: WAITMONITORINGTIME in ns.
 649  * @return:          -1 on failure to scale, else proper divider > 0.
 650  */
 651 static int gpmc_calc_waitmonitoring_divider(unsigned int wait_monitoring)
 652 {
 653
 654         int div = gpmc_ns_to_ticks(wait_monitoring);
 655
 656         div += GPMC_CONFIG1_WAITMONITORINGTIME_MAX - 1;
 657         div /= GPMC_CONFIG1_WAITMONITORINGTIME_MAX;
 658
 659         if (div > 4)
 660                 return -1;
 661         if (div <= 0)
 662                 div = 1;
 663
 664         return div;
 665
 666 }
 667
 668 /**
 669  * gpmc_calc_divider - calculate GPMC_FCLK divider for sync_clk GPMC_CLK period.
 670  * @sync_clk: GPMC_CLK period in ps.
 671  * @return:   Returns at least 1 if GPMC_FCLK can be divided to GPMC_CLK.
 672  *            Else, returns -1.
 673  */
 674 int gpmc_calc_divider(unsigned int sync_clk)
 675 {
 676         int div = gpmc_ps_to_ticks(sync_clk);
 677
 678         if (div > 4)
 679                 return -1;
 680         if (div <= 0)
 681                 div = 1;
 682
 683         return div;
 684 }
 685
 686 /**
 687  * gpmc_cs_set_timings - program timing parameters for Chip Select Region.
 688  * @cs:     Chip Select Region.
 689  * @t:      GPMC timing parameters.
 690  * @s:      GPMC timing settings.
 691  * @return: 0 on success, -1 on error.
 692  */
 693 int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t,
 694                         const struct gpmc_settings *s)
 695 {
 696         int div;
 697         u32 l;
 698
 699         gpmc_cs_show_timings(cs, "before gpmc_cs_set_timings");
 700         div = gpmc_calc_divider(t->sync_clk);
 701         if (div < 0)
 702                 return div;
 703
 704         /*
 705          * See if we need to change the divider for waitmonitoringtime.
 706          *
 707          * Calculate GPMCFCLKDIVIDER independent of gpmc,sync-clk-ps in DT for
 708          * pure asynchronous accesses, i.e. both read and write asynchronous.
 709          * However, only do so if WAITMONITORINGTIME is actually used, i.e.
 710          * either WAITREADMONITORING or WAITWRITEMONITORING is set.
 711          *
 712          * This statement must not change div to scale async WAITMONITORINGTIME
 713          * to protect mixed synchronous and asynchronous accesses.
 714          *
 715          * We raise an error later if WAITMONITORINGTIME does not fit.
 716          */
 717         if (!s->sync_read && !s->sync_write &&
 718             (s->wait_on_read || s->wait_on_write)
 719            ) {
 720
 721                 div = gpmc_calc_waitmonitoring_divider(t->wait_monitoring);
 722                 if (div < 0) {
 723                         pr_err("%s: waitmonitoringtime %3d ns too large for greatest gpmcfclkdivider.\n",
 724                                __func__,
 725                                t->wait_monitoring
 726                                );
 727                         return -1;
 728                 }
 729         }
 730
 731         GPMC_SET_ONE(GPMC_CS_CONFIG2,  0,  3, cs_on);
 732         GPMC_SET_ONE(GPMC_CS_CONFIG2,  8, 12, cs_rd_off);
 733         GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
 734
 735         GPMC_SET_ONE(GPMC_CS_CONFIG3,  0,  3, adv_on);
 736         GPMC_SET_ONE(GPMC_CS_CONFIG3,  8, 12, adv_rd_off);
 737         GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
 738
 739         GPMC_SET_ONE(GPMC_CS_CONFIG4,  0,  3, oe_on);
 740         GPMC_SET_ONE(GPMC_CS_CONFIG4,  8, 12, oe_off);
 741         GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
 742         GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
 743
 744         GPMC_SET_ONE(GPMC_CS_CONFIG5,  0,  4, rd_cycle);
 745         GPMC_SET_ONE(GPMC_CS_CONFIG5,  8, 12, wr_cycle);
 746         GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
 747
 748         GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
 749
 750         GPMC_SET_ONE(GPMC_CS_CONFIG6, 0, 3, bus_turnaround);
 751         GPMC_SET_ONE(GPMC_CS_CONFIG6, 8, 11, cycle2cycle_delay);
 752
 753         if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
 754                 GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
 755         if (gpmc_capability & GPMC_HAS_WR_ACCESS)
 756                 GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
 757
 758         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
 759         l &= ~0x03;
 760         l |= (div - 1);
 761         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
 762
 763         GPMC_SET_ONE_CD_MAX(GPMC_CS_CONFIG1, 18, 19,
 764                             GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
 765                             wait_monitoring, GPMC_CD_CLK);
 766         GPMC_SET_ONE_CD_MAX(GPMC_CS_CONFIG1, 25, 26,
 767                             GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
 768                             clk_activation, GPMC_CD_FCLK);
 769
 770 #ifdef CONFIG_OMAP_GPMC_DEBUG
 771         pr_info("GPMC CS%d CLK period is %lu ns (div %d)\n",
 772                         cs, (div * gpmc_get_fclk_period()) / 1000, div);
 773 #endif
 774
 775         gpmc_cs_bool_timings(cs, &t->bool_timings);
 776         gpmc_cs_show_timings(cs, "after gpmc_cs_set_timings");
 777
 778         return 0;
 779 }
 780
 781 static int gpmc_cs_set_memconf(int cs, u32 base, u32 size)
 782 {
 783         u32 l;
 784         u32 mask;
 785
 786         /*
 787          * Ensure that base address is aligned on a
 788          * boundary equal to or greater than size.
 789          */
 790         if (base & (size - 1))
 791                 return -EINVAL;
 792
 793         base >>= GPMC_CHUNK_SHIFT;
 794         mask = (1 << GPMC_SECTION_SHIFT) - size;
 795         mask >>= GPMC_CHUNK_SHIFT;
 796         mask <<= GPMC_CONFIG7_MASKADDRESS_OFFSET;
 797
 798         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 799         l &= ~GPMC_CONFIG7_MASK;
 800         l |= base & GPMC_CONFIG7_BASEADDRESS_MASK;
 801         l |= mask & GPMC_CONFIG7_MASKADDRESS_MASK;
 802         l |= GPMC_CONFIG7_CSVALID;
 803         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 804
 805         return 0;
 806 }
 807
 808 static void gpmc_cs_enable_mem(int cs)
 809 {
 810         u32 l;
 811
 812         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 813         l |= GPMC_CONFIG7_CSVALID;
 814         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 815 }
 816
 817 static void gpmc_cs_disable_mem(int cs)
 818 {
 819         u32 l;
 820
 821         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 822         l &= ~GPMC_CONFIG7_CSVALID;
 823         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 824 }
 825
 826 static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
 827 {
 828         u32 l;
 829         u32 mask;
 830
 831         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 832         *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
 833         mask = (l >> 8) & 0x0f;
 834         *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
 835 }
 836
 837 static int gpmc_cs_mem_enabled(int cs)
 838 {
 839         u32 l;
 840
 841         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 842         return l & GPMC_CONFIG7_CSVALID;
 843 }
 844
 845 static void gpmc_cs_set_reserved(int cs, int reserved)
 846 {
 847         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 848
 849         gpmc->flags |= GPMC_CS_RESERVED;
 850 }
 851
 852 static bool gpmc_cs_reserved(int cs)
 853 {
 854         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 855
 856         return gpmc->flags & GPMC_CS_RESERVED;
 857 }
 858
 859 static void gpmc_cs_set_name(int cs, const char *name)
 860 {
 861         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 862
 863         gpmc->name = name;
 864 }
 865
 866 static const char *gpmc_cs_get_name(int cs)
 867 {
 868         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 869
 870         return gpmc->name;
 871 }
 872
 873 static unsigned long gpmc_mem_align(unsigned long size)
 874 {
 875         int order;
 876
 877         size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
 878         order = GPMC_CHUNK_SHIFT - 1;
 879         do {
 880                 size >>= 1;
 881                 order++;
 882         } while (size);
 883         size = 1 << order;
 884         return size;
 885 }
 886
 887 static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
 888 {
 889         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 890         struct resource *res = &gpmc->mem;
 891         int r;
 892
 893         size = gpmc_mem_align(size);
 894         spin_lock(&gpmc_mem_lock);
 895         res->start = base;
 896         res->end = base + size - 1;
 897         r = request_resource(&gpmc_mem_root, res);
 898         spin_unlock(&gpmc_mem_lock);
 899
 900         return r;
 901 }
 902
 903 static int gpmc_cs_delete_mem(int cs)
 904 {
 905         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 906         struct resource *res = &gpmc->mem;
 907         int r;
 908
 909         spin_lock(&gpmc_mem_lock);
 910         r = release_resource(res);
 911         res->start = 0;
 912         res->end = 0;
 913         spin_unlock(&gpmc_mem_lock);
 914
 915         return r;
 916 }
 917
 918 /**
 919  * gpmc_cs_remap - remaps a chip-select physical base address
 920  * @cs:         chip-select to remap
 921  * @base:       physical base address to re-map chip-select to
 922  *
 923  * Re-maps a chip-select to a new physical base address specified by
 924  * "base". Returns 0 on success and appropriate negative error code
 925  * on failure.
 926  */
 927 static int gpmc_cs_remap(int cs, u32 base)
 928 {
 929         int ret;
 930         u32 old_base, size;
 931
 932         if (cs > gpmc_cs_num) {
 933                 pr_err("%s: requested chip-select is disabled\n", __func__);
 934                 return -ENODEV;
 935         }
 936
 937         /*
 938          * Make sure we ignore any device offsets from the GPMC partition
 939          * allocated for the chip select and that the new base confirms
 940          * to the GPMC 16MB minimum granularity.
 941          */
 942         base &= ~(SZ_16M - 1);
 943
 944         gpmc_cs_get_memconf(cs, &old_base, &size);
 945         if (base == old_base)
 946                 return 0;
 947
 948         ret = gpmc_cs_delete_mem(cs);
 949         if (ret < 0)
 950                 return ret;
 951
 952         ret = gpmc_cs_insert_mem(cs, base, size);
 953         if (ret < 0)
 954                 return ret;
 955
 956         ret = gpmc_cs_set_memconf(cs, base, size);
 957
 958         return ret;
 959 }
 960
 961 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
 962 {
 963         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 964         struct resource *res = &gpmc->mem;
 965         int r = -1;
 966
 967         if (cs > gpmc_cs_num) {
 968                 pr_err("%s: requested chip-select is disabled\n", __func__);
 969                 return -ENODEV;
 970         }
 971         size = gpmc_mem_align(size);
 972         if (size > (1 << GPMC_SECTION_SHIFT))
 973                 return -ENOMEM;
 974
 975         spin_lock(&gpmc_mem_lock);
 976         if (gpmc_cs_reserved(cs)) {
 977                 r = -EBUSY;
 978                 goto out;
 979         }
 980         if (gpmc_cs_mem_enabled(cs))
 981                 r = adjust_resource(res, res->start & ~(size - 1), size);
 982         if (r < 0)
 983                 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
 984                                       size, NULL, NULL);
 985         if (r < 0)
 986                 goto out;
 987
 988         /* Disable CS while changing base address and size mask */
 989         gpmc_cs_disable_mem(cs);
 990
 991         r = gpmc_cs_set_memconf(cs, res->start, resource_size(res));
 992         if (r < 0) {
 993                 release_resource(res);
 994                 goto out;
 995         }
 996
 997         /* Enable CS */
 998         gpmc_cs_enable_mem(cs);
 999         *base = res->start;
1000         gpmc_cs_set_reserved(cs, 1);
1001 out:
1002         spin_unlock(&gpmc_mem_lock);
1003         return r;
1004 }
1005 EXPORT_SYMBOL(gpmc_cs_request);
1006
1007 void gpmc_cs_free(int cs)
1008 {
1009         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
1010         struct resource *res = &gpmc->mem;
1011
1012         spin_lock(&gpmc_mem_lock);
1013         if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) {
1014                 printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
1015                 BUG();
1016                 spin_unlock(&gpmc_mem_lock);
1017                 return;
1018         }
1019         gpmc_cs_disable_mem(cs);
1020         if (res->flags)
1021                 release_resource(res);
1022         gpmc_cs_set_reserved(cs, 0);
1023         spin_unlock(&gpmc_mem_lock);
1024 }
1025 EXPORT_SYMBOL(gpmc_cs_free);
1026
1027 /**
1028  * gpmc_configure - write request to configure gpmc
1029  * @cmd: command type
1030  * @wval: value to write
1031  * @return status of the operation
1032  */
1033 int gpmc_configure(int cmd, int wval)
1034 {
1035         u32 regval;
1036
1037         switch (cmd) {
1038         case GPMC_ENABLE_IRQ:
1039                 gpmc_write_reg(GPMC_IRQENABLE, wval);
1040                 break;
1041
1042         case GPMC_SET_IRQ_STATUS:
1043                 gpmc_write_reg(GPMC_IRQSTATUS, wval);
1044                 break;
1045
1046         case GPMC_CONFIG_WP:
1047                 regval = gpmc_read_reg(GPMC_CONFIG);
1048                 if (wval)
1049                         regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
1050                 else
1051                         regval |= GPMC_CONFIG_WRITEPROTECT;  /* WP is OFF */
1052                 gpmc_write_reg(GPMC_CONFIG, regval);
1053                 break;
1054
1055         default:
1056                 pr_err("%s: command not supported\n", __func__);
1057                 return -EINVAL;
1058         }
1059
1060         return 0;
1061 }
1062 EXPORT_SYMBOL(gpmc_configure);
1063
1064 void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs)
1065 {
1066         int i;
1067
1068         reg->gpmc_status = gpmc_base + GPMC_STATUS;
1069         reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
1070                                 GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
1071         reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET +
1072                                 GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs;
1073         reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET +
1074                                 GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs;
1075         reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1;
1076         reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2;
1077         reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL;
1078         reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS;
1079         reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG;
1080         reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL;
1081         reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG;
1082         reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT;
1083
1084         for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) {
1085                 reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 +
1086                                            GPMC_BCH_SIZE * i;
1087                 reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 +
1088                                            GPMC_BCH_SIZE * i;
1089                 reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 +
1090                                            GPMC_BCH_SIZE * i;
1091                 reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 +
1092                                            GPMC_BCH_SIZE * i;
1093                 reg->gpmc_bch_result4[i] = gpmc_base + GPMC_ECC_BCH_RESULT_4 +
1094                                            i * GPMC_BCH_SIZE;
1095                 reg->gpmc_bch_result5[i] = gpmc_base + GPMC_ECC_BCH_RESULT_5 +
1096                                            i * GPMC_BCH_SIZE;
1097                 reg->gpmc_bch_result6[i] = gpmc_base + GPMC_ECC_BCH_RESULT_6 +
1098                                            i * GPMC_BCH_SIZE;
1099         }
1100 }
1101
1102 int gpmc_get_client_irq(unsigned irq_config)
1103 {
1104         int i;
1105
1106         if (hweight32(irq_config) > 1)
1107                 return 0;
1108
1109         for (i = 0; i < GPMC_NR_IRQ; i++)
1110                 if (gpmc_client_irq[i].bitmask & irq_config)
1111                         return gpmc_client_irq[i].irq;
1112
1113         return 0;
1114 }
1115
1116 static int gpmc_irq_endis(unsigned irq, bool endis)
1117 {
1118         int i;
1119         u32 regval;
1120
1121         for (i = 0; i < GPMC_NR_IRQ; i++)
1122                 if (irq == gpmc_client_irq[i].irq) {
1123                         regval = gpmc_read_reg(GPMC_IRQENABLE);
1124                         if (endis)
1125                                 regval |= gpmc_client_irq[i].bitmask;
1126                         else
1127                                 regval &= ~gpmc_client_irq[i].bitmask;
1128                         gpmc_write_reg(GPMC_IRQENABLE, regval);
1129                         break;
1130                 }
1131
1132         return 0;
1133 }
1134
1135 static void gpmc_irq_disable(struct irq_data *p)
1136 {
1137         gpmc_irq_endis(p->irq, false);
1138 }
1139
1140 static void gpmc_irq_enable(struct irq_data *p)
1141 {
1142         gpmc_irq_endis(p->irq, true);
1143 }
1144
1145 static void gpmc_irq_noop(struct irq_data *data) { }
1146
1147 static unsigned int gpmc_irq_noop_ret(struct irq_data *data) { return 0; }
1148
1149 static int gpmc_setup_irq(void)
1150 {
1151         int i;
1152         u32 regval;
1153
1154         if (!gpmc_irq)
1155                 return -EINVAL;
1156
1157         gpmc_irq_start = irq_alloc_descs(-1, 0, GPMC_NR_IRQ, 0);
1158         if (gpmc_irq_start < 0) {
1159                 pr_err("irq_alloc_descs failed\n");
1160                 return gpmc_irq_start;
1161         }
1162
1163         gpmc_irq_chip.name = "gpmc";
1164         gpmc_irq_chip.irq_startup = gpmc_irq_noop_ret;
1165         gpmc_irq_chip.irq_enable = gpmc_irq_enable;
1166         gpmc_irq_chip.irq_disable = gpmc_irq_disable;
1167         gpmc_irq_chip.irq_shutdown = gpmc_irq_noop;
1168         gpmc_irq_chip.irq_ack = gpmc_irq_noop;
1169         gpmc_irq_chip.irq_mask = gpmc_irq_noop;
1170         gpmc_irq_chip.irq_unmask = gpmc_irq_noop;
1171
1172         gpmc_client_irq[0].bitmask = GPMC_IRQ_FIFOEVENTENABLE;
1173         gpmc_client_irq[1].bitmask = GPMC_IRQ_COUNT_EVENT;
1174
1175         for (i = 0; i < GPMC_NR_IRQ; i++) {
1176                 gpmc_client_irq[i].irq = gpmc_irq_start + i;
1177                 irq_set_chip_and_handler(gpmc_client_irq[i].irq,
1178                                         &gpmc_irq_chip, handle_simple_irq);
1179                 set_irq_flags(gpmc_client_irq[i].irq,
1180                                 IRQF_VALID | IRQF_NOAUTOEN);
1181         }
1182
1183         /* Disable interrupts */
1184         gpmc_write_reg(GPMC_IRQENABLE, 0);
1185
1186         /* clear interrupts */
1187         regval = gpmc_read_reg(GPMC_IRQSTATUS);
1188         gpmc_write_reg(GPMC_IRQSTATUS, regval);
1189
1190         return request_irq(gpmc_irq, gpmc_handle_irq, 0, "gpmc", NULL);
1191 }
1192
1193 static int gpmc_free_irq(void)
1194 {
1195         int i;
1196
1197         if (gpmc_irq)
1198                 free_irq(gpmc_irq, NULL);
1199
1200         for (i = 0; i < GPMC_NR_IRQ; i++) {
1201                 irq_set_handler(gpmc_client_irq[i].irq, NULL);
1202                 irq_set_chip(gpmc_client_irq[i].irq, &no_irq_chip);
1203                 irq_modify_status(gpmc_client_irq[i].irq, 0, 0);
1204         }
1205
1206         irq_free_descs(gpmc_irq_start, GPMC_NR_IRQ);
1207
1208         return 0;
1209 }
1210
1211 static void gpmc_mem_exit(void)
1212 {
1213         int cs;
1214
1215         for (cs = 0; cs < gpmc_cs_num; cs++) {
1216                 if (!gpmc_cs_mem_enabled(cs))
1217                         continue;
1218                 gpmc_cs_delete_mem(cs);
1219         }
1220
1221 }
1222
1223 static void gpmc_mem_init(void)
1224 {
1225         int cs;
1226
1227         /*
1228          * The first 1MB of GPMC address space is typically mapped to
1229          * the internal ROM. Never allocate the first page, to
1230          * facilitate bug detection; even if we didn't boot from ROM.
1231          */
1232         gpmc_mem_root.start = SZ_1M;
1233         gpmc_mem_root.end = GPMC_MEM_END;
1234
1235         /* Reserve all regions that has been set up by bootloader */
1236         for (cs = 0; cs < gpmc_cs_num; cs++) {
1237                 u32 base, size;
1238
1239                 if (!gpmc_cs_mem_enabled(cs))
1240                         continue;
1241                 gpmc_cs_get_memconf(cs, &base, &size);
1242                 if (gpmc_cs_insert_mem(cs, base, size)) {
1243                         pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n",
1244                                 __func__, cs, base, base + size);
1245                         gpmc_cs_disable_mem(cs);
1246                 }
1247         }
1248 }
1249
1250 static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
1251 {
1252         u32 temp;
1253         int div;
1254
1255         div = gpmc_calc_divider(sync_clk);
1256         temp = gpmc_ps_to_ticks(time_ps);
1257         temp = (temp + div - 1) / div;
1258         return gpmc_ticks_to_ps(temp * div);
1259 }
1260
1261 /* XXX: can the cycles be avoided ? */
1262 static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
1263                                        struct gpmc_device_timings *dev_t,
1264                                        bool mux)
1265 {
1266         u32 temp;
1267
1268         /* adv_rd_off */
1269         temp = dev_t->t_avdp_r;
1270         /* XXX: mux check required ? */
1271         if (mux) {
1272                 /* XXX: t_avdp not to be required for sync, only added for tusb
1273                  * this indirectly necessitates requirement of t_avdp_r and
1274                  * t_avdp_w instead of having a single t_avdp
1275                  */
1276                 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_avdh);
1277                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1278         }
1279         gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1280
1281         /* oe_on */
1282         temp = dev_t->t_oeasu; /* XXX: remove this ? */
1283         if (mux) {
1284                 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_ach);
1285                 temp = max_t(u32, temp, gpmc_t->adv_rd_off +
1286                                 gpmc_ticks_to_ps(dev_t->cyc_aavdh_oe));
1287         }
1288         gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1289
1290         /* access */
1291         /* XXX: any scope for improvement ?, by combining oe_on
1292          * and clk_activation, need to check whether
1293          * access = clk_activation + round to sync clk ?
1294          */
1295         temp = max_t(u32, dev_t->t_iaa, dev_t->cyc_iaa * gpmc_t->sync_clk);
1296         temp += gpmc_t->clk_activation;
1297         if (dev_t->cyc_oe)
1298                 temp = max_t(u32, temp, gpmc_t->oe_on +
1299                                 gpmc_ticks_to_ps(dev_t->cyc_oe));
1300         gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1301
1302         gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1303         gpmc_t->cs_rd_off = gpmc_t->oe_off;
1304
1305         /* rd_cycle */
1306         temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez);
1307         temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) +
1308                                                         gpmc_t->access;
1309         /* XXX: barter t_ce_rdyz with t_cez_r ? */
1310         if (dev_t->t_ce_rdyz)
1311                 temp = max_t(u32, temp, gpmc_t->cs_rd_off + dev_t->t_ce_rdyz);
1312         gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1313
1314         return 0;
1315 }
1316
1317 static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
1318                                         struct gpmc_device_timings *dev_t,
1319                                         bool mux)
1320 {
1321         u32 temp;
1322
1323         /* adv_wr_off */
1324         temp = dev_t->t_avdp_w;
1325         if (mux) {
1326                 temp = max_t(u32, temp,
1327                         gpmc_t->clk_activation + dev_t->t_avdh);
1328                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1329         }
1330         gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1331
1332         /* wr_data_mux_bus */
1333         temp = max_t(u32, dev_t->t_weasu,
1334                         gpmc_t->clk_activation + dev_t->t_rdyo);
1335         /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?,
1336          * and in that case remember to handle we_on properly
1337          */
1338         if (mux) {
1339                 temp = max_t(u32, temp,
1340                         gpmc_t->adv_wr_off + dev_t->t_aavdh);
1341                 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1342                                 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1343         }
1344         gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1345
1346         /* we_on */
1347         if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1348                 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1349         else
1350                 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1351
1352         /* wr_access */
1353         /* XXX: gpmc_capability check reqd ? , even if not, will not harm */
1354         gpmc_t->wr_access = gpmc_t->access;
1355
1356         /* we_off */
1357         temp = gpmc_t->we_on + dev_t->t_wpl;
1358         temp = max_t(u32, temp,
1359                         gpmc_t->wr_access + gpmc_ticks_to_ps(1));
1360         temp = max_t(u32, temp,
1361                 gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl));
1362         gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1363
1364         gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1365                                                         dev_t->t_wph);
1366
1367         /* wr_cycle */
1368         temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk);
1369         temp += gpmc_t->wr_access;
1370         /* XXX: barter t_ce_rdyz with t_cez_w ? */
1371         if (dev_t->t_ce_rdyz)
1372                 temp = max_t(u32, temp,
1373                                  gpmc_t->cs_wr_off + dev_t->t_ce_rdyz);
1374         gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1375
1376         return 0;
1377 }
1378
1379 static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
1380                                         struct gpmc_device_timings *dev_t,
1381                                         bool mux)
1382 {
1383         u32 temp;
1384
1385         /* adv_rd_off */
1386         temp = dev_t->t_avdp_r;
1387         if (mux)
1388                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1389         gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1390
1391         /* oe_on */
1392         temp = dev_t->t_oeasu;
1393         if (mux)
1394                 temp = max_t(u32, temp,
1395                         gpmc_t->adv_rd_off + dev_t->t_aavdh);
1396         gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1397
1398         /* access */
1399         temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */
1400                                 gpmc_t->oe_on + dev_t->t_oe);
1401         temp = max_t(u32, temp,
1402                                 gpmc_t->cs_on + dev_t->t_ce);
1403         temp = max_t(u32, temp,
1404                                 gpmc_t->adv_on + dev_t->t_aa);
1405         gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1406
1407         gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1408         gpmc_t->cs_rd_off = gpmc_t->oe_off;
1409
1410         /* rd_cycle */
1411         temp = max_t(u32, dev_t->t_rd_cycle,
1412                         gpmc_t->cs_rd_off + dev_t->t_cez_r);
1413         temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez);
1414         gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1415
1416         return 0;
1417 }
1418
1419 static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t,
1420                                          struct gpmc_device_timings *dev_t,
1421                                          bool mux)
1422 {
1423         u32 temp;
1424
1425         /* adv_wr_off */
1426         temp = dev_t->t_avdp_w;
1427         if (mux)
1428                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1429         gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1430
1431         /* wr_data_mux_bus */
1432         temp = dev_t->t_weasu;
1433         if (mux) {
1434                 temp = max_t(u32, temp, gpmc_t->adv_wr_off + dev_t->t_aavdh);
1435                 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1436                                 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1437         }
1438         gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1439
1440         /* we_on */
1441         if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1442                 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1443         else
1444                 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1445
1446         /* we_off */
1447         temp = gpmc_t->we_on + dev_t->t_wpl;
1448         gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1449
1450         gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1451                                                         dev_t->t_wph);
1452
1453         /* wr_cycle */
1454         temp = max_t(u32, dev_t->t_wr_cycle,
1455                                 gpmc_t->cs_wr_off + dev_t->t_cez_w);
1456         gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1457
1458         return 0;
1459 }
1460
1461 static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t,
1462                         struct gpmc_device_timings *dev_t)
1463 {
1464         u32 temp;
1465
1466         gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) *
1467                                                 gpmc_get_fclk_period();
1468
1469         gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk(
1470                                         dev_t->t_bacc,
1471                                         gpmc_t->sync_clk);
1472
1473         temp = max_t(u32, dev_t->t_ces, dev_t->t_avds);
1474         gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp);
1475
1476         if (gpmc_calc_divider(gpmc_t->sync_clk) != 1)
1477                 return 0;
1478
1479         if (dev_t->ce_xdelay)
1480                 gpmc_t->bool_timings.cs_extra_delay = true;
1481         if (dev_t->avd_xdelay)
1482                 gpmc_t->bool_timings.adv_extra_delay = true;
1483         if (dev_t->oe_xdelay)
1484                 gpmc_t->bool_timings.oe_extra_delay = true;
1485         if (dev_t->we_xdelay)
1486                 gpmc_t->bool_timings.we_extra_delay = true;
1487
1488         return 0;
1489 }
1490
1491 static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
1492                                     struct gpmc_device_timings *dev_t,
1493                                     bool sync)
1494 {
1495         u32 temp;
1496
1497         /* cs_on */
1498         gpmc_t->cs_on = gpmc_round_ps_to_ticks(dev_t->t_ceasu);
1499
1500         /* adv_on */
1501         temp = dev_t->t_avdasu;
1502         if (dev_t->t_ce_avd)
1503                 temp = max_t(u32, temp,
1504                                 gpmc_t->cs_on + dev_t->t_ce_avd);
1505         gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp);
1506
1507         if (sync)
1508                 gpmc_calc_sync_common_timings(gpmc_t, dev_t);
1509
1510         return 0;
1511 }
1512
1513 /* TODO: remove this function once all peripherals are confirmed to
1514  * work with generic timing. Simultaneously gpmc_cs_set_timings()
1515  * has to be modified to handle timings in ps instead of ns
1516 */
1517 static void gpmc_convert_ps_to_ns(struct gpmc_timings *t)
1518 {
1519         t->cs_on /= 1000;
1520         t->cs_rd_off /= 1000;
1521         t->cs_wr_off /= 1000;
1522         t->adv_on /= 1000;
1523         t->adv_rd_off /= 1000;
1524         t->adv_wr_off /= 1000;
1525         t->we_on /= 1000;
1526         t->we_off /= 1000;
1527         t->oe_on /= 1000;
1528         t->oe_off /= 1000;
1529         t->page_burst_access /= 1000;
1530         t->access /= 1000;
1531         t->rd_cycle /= 1000;
1532         t->wr_cycle /= 1000;
1533         t->bus_turnaround /= 1000;
1534         t->cycle2cycle_delay /= 1000;
1535         t->wait_monitoring /= 1000;
1536         t->clk_activation /= 1000;
1537         t->wr_access /= 1000;
1538         t->wr_data_mux_bus /= 1000;
1539 }
1540
1541 int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
1542                       struct gpmc_settings *gpmc_s,
1543                       struct gpmc_device_timings *dev_t)
1544 {
1545         bool mux = false, sync = false;
1546
1547         if (gpmc_s) {
1548                 mux = gpmc_s->mux_add_data ? true : false;
1549                 sync = (gpmc_s->sync_read || gpmc_s->sync_write);
1550         }
1551
1552         memset(gpmc_t, 0, sizeof(*gpmc_t));
1553
1554         gpmc_calc_common_timings(gpmc_t, dev_t, sync);
1555
1556         if (gpmc_s && gpmc_s->sync_read)
1557                 gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux);
1558         else
1559                 gpmc_calc_async_read_timings(gpmc_t, dev_t, mux);
1560
1561         if (gpmc_s && gpmc_s->sync_write)
1562                 gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux);
1563         else
1564                 gpmc_calc_async_write_timings(gpmc_t, dev_t, mux);
1565
1566         /* TODO: remove, see function definition */
1567         gpmc_convert_ps_to_ns(gpmc_t);
1568
1569         return 0;
1570 }
1571
1572 /**
1573  * gpmc_cs_program_settings - programs non-timing related settings
1574  * @cs:         GPMC chip-select to program
1575  * @p:          pointer to GPMC settings structure
1576  *
1577  * Programs non-timing related settings for a GPMC chip-select, such as
1578  * bus-width, burst configuration, etc. Function should be called once
1579  * for each chip-select that is being used and must be called before
1580  * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1
1581  * register will be initialised to zero by this function. Returns 0 on
1582  * success and appropriate negative error code on failure.
1583  */
1584 int gpmc_cs_program_settings(int cs, struct gpmc_settings *p)
1585 {
1586         u32 config1;
1587
1588         if ((!p->device_width) || (p->device_width > GPMC_DEVWIDTH_16BIT)) {
1589                 pr_err("%s: invalid width %d!", __func__, p->device_width);
1590                 return -EINVAL;
1591         }
1592
1593         /* Address-data multiplexing not supported for NAND devices */
1594         if (p->device_nand && p->mux_add_data) {
1595                 pr_err("%s: invalid configuration!\n", __func__);
1596                 return -EINVAL;
1597         }
1598
1599         if ((p->mux_add_data > GPMC_MUX_AD) ||
1600             ((p->mux_add_data == GPMC_MUX_AAD) &&
1601              !(gpmc_capability & GPMC_HAS_MUX_AAD))) {
1602                 pr_err("%s: invalid multiplex configuration!\n", __func__);
1603                 return -EINVAL;
1604         }
1605
1606         /* Page/burst mode supports lengths of 4, 8 and 16 bytes */
1607         if (p->burst_read || p->burst_write) {
1608                 switch (p->burst_len) {
1609                 case GPMC_BURST_4:
1610                 case GPMC_BURST_8:
1611                 case GPMC_BURST_16:
1612                         break;
1613                 default:
1614                         pr_err("%s: invalid page/burst-length (%d)\n",
1615                                __func__, p->burst_len);
1616                         return -EINVAL;
1617                 }
1618         }
1619
1620         if (p->wait_pin > gpmc_nr_waitpins) {
1621                 pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin);
1622                 return -EINVAL;
1623         }
1624
1625         config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1));
1626
1627         if (p->sync_read)
1628                 config1 |= GPMC_CONFIG1_READTYPE_SYNC;
1629         if (p->sync_write)
1630                 config1 |= GPMC_CONFIG1_WRITETYPE_SYNC;
1631         if (p->wait_on_read)
1632                 config1 |= GPMC_CONFIG1_WAIT_READ_MON;
1633         if (p->wait_on_write)
1634                 config1 |= GPMC_CONFIG1_WAIT_WRITE_MON;
1635         if (p->wait_on_read || p->wait_on_write)
1636                 config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin);
1637         if (p->device_nand)
1638                 config1 |= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND);
1639         if (p->mux_add_data)
1640                 config1 |= GPMC_CONFIG1_MUXTYPE(p->mux_add_data);
1641         if (p->burst_read)
1642                 config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP;
1643         if (p->burst_write)
1644                 config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP;
1645         if (p->burst_read || p->burst_write) {
1646                 config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3);
1647                 config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0;
1648         }
1649
1650         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1);
1651
1652         return 0;
1653 }
1654
1655 #ifdef CONFIG_OF
1656 static const struct of_device_id gpmc_dt_ids[] = {
1657         { .compatible = "ti,omap2420-gpmc" },
1658         { .compatible = "ti,omap2430-gpmc" },
1659         { .compatible = "ti,omap3430-gpmc" },   /* omap3430 & omap3630 */
1660         { .compatible = "ti,omap4430-gpmc" },   /* omap4430 & omap4460 & omap543x */
1661         { .compatible = "ti,am3352-gpmc" },     /* am335x devices */
1662         { }
1663 };
1664 MODULE_DEVICE_TABLE(of, gpmc_dt_ids);
1665
1666 /**
1667  * gpmc_read_settings_dt - read gpmc settings from device-tree
1668  * @np:         pointer to device-tree node for a gpmc child device
1669  * @p:          pointer to gpmc settings structure
1670  *
1671  * Reads the GPMC settings for a GPMC child device from device-tree and
1672  * stores them in the GPMC settings structure passed. The GPMC settings
1673  * structure is initialised to zero by this function and so any
1674  * previously stored settings will be cleared.
1675  */
1676 void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
1677 {
1678         memset(p, 0, sizeof(struct gpmc_settings));
1679
1680         p->sync_read = of_property_read_bool(np, "gpmc,sync-read");
1681         p->sync_write = of_property_read_bool(np, "gpmc,sync-write");
1682         of_property_read_u32(np, "gpmc,device-width", &p->device_width);
1683         of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data);
1684
1685         if (!of_property_read_u32(np, "gpmc,burst-length", &p->burst_len)) {
1686                 p->burst_wrap = of_property_read_bool(np, "gpmc,burst-wrap");
1687                 p->burst_read = of_property_read_bool(np, "gpmc,burst-read");
1688                 p->burst_write = of_property_read_bool(np, "gpmc,burst-write");
1689                 if (!p->burst_read && !p->burst_write)
1690                         pr_warn("%s: page/burst-length set but not used!\n",
1691                                 __func__);
1692         }
1693
1694         if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) {
1695                 p->wait_on_read = of_property_read_bool(np,
1696                                                         "gpmc,wait-on-read");
1697                 p->wait_on_write = of_property_read_bool(np,
1698                                                          "gpmc,wait-on-write");
1699                 if (!p->wait_on_read && !p->wait_on_write)
1700                         pr_debug("%s: rd/wr wait monitoring not enabled!\n",
1701                                  __func__);
1702         }
1703 }
1704
1705 static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
1706                                                 struct gpmc_timings *gpmc_t)
1707 {
1708         struct gpmc_bool_timings *p;
1709
1710         if (!np || !gpmc_t)
1711                 return;
1712
1713         memset(gpmc_t, 0, sizeof(*gpmc_t));
1714
1715         /* minimum clock period for syncronous mode */
1716         of_property_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk);
1717
1718         /* chip select timtings */
1719         of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on);
1720         of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off);
1721         of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off);
1722
1723         /* ADV signal timings */
1724         of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on);
1725         of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off);
1726         of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off);
1727
1728         /* WE signal timings */
1729         of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on);
1730         of_property_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off);
1731
1732         /* OE signal timings */
1733         of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on);
1734         of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off);
1735
1736         /* access and cycle timings */
1737         of_property_read_u32(np, "gpmc,page-burst-access-ns",
1738                              &gpmc_t->page_burst_access);
1739         of_property_read_u32(np, "gpmc,access-ns", &gpmc_t->access);
1740         of_property_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle);
1741         of_property_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle);
1742         of_property_read_u32(np, "gpmc,bus-turnaround-ns",
1743                              &gpmc_t->bus_turnaround);
1744         of_property_read_u32(np, "gpmc,cycle2cycle-delay-ns",
1745                              &gpmc_t->cycle2cycle_delay);
1746         of_property_read_u32(np, "gpmc,wait-monitoring-ns",
1747                              &gpmc_t->wait_monitoring);
1748         of_property_read_u32(np, "gpmc,clk-activation-ns",
1749                              &gpmc_t->clk_activation);
1750
1751         /* only applicable to OMAP3+ */
1752         of_property_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access);
1753         of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns",
1754                              &gpmc_t->wr_data_mux_bus);
1755
1756         /* bool timing parameters */
1757         p = &gpmc_t->bool_timings;
1758
1759         p->cycle2cyclediffcsen =
1760                 of_property_read_bool(np, "gpmc,cycle2cycle-diffcsen");
1761         p->cycle2cyclesamecsen =
1762                 of_property_read_bool(np, "gpmc,cycle2cycle-samecsen");
1763         p->we_extra_delay = of_property_read_bool(np, "gpmc,we-extra-delay");
1764         p->oe_extra_delay = of_property_read_bool(np, "gpmc,oe-extra-delay");
1765         p->adv_extra_delay = of_property_read_bool(np, "gpmc,adv-extra-delay");
1766         p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay");
1767         p->time_para_granularity =
1768                 of_property_read_bool(np, "gpmc,time-para-granularity");
1769 }
1770
1771 #if IS_ENABLED(CONFIG_MTD_NAND)
1772
1773 static const char * const nand_xfer_types[] = {
1774         [NAND_OMAP_PREFETCH_POLLED]             = "prefetch-polled",
1775         [NAND_OMAP_POLLED]                      = "polled",
1776         [NAND_OMAP_PREFETCH_DMA]                = "prefetch-dma",
1777         [NAND_OMAP_PREFETCH_IRQ]                = "prefetch-irq",
1778 };
1779
1780 static int gpmc_probe_nand_child(struct platform_device *pdev,
1781                                  struct device_node *child)
1782 {
1783         u32 val;
1784         const char *s;
1785         struct gpmc_timings gpmc_t;
1786         struct omap_nand_platform_data *gpmc_nand_data;
1787
1788         if (of_property_read_u32(child, "reg", &val) < 0) {
1789                 dev_err(&pdev->dev, "%s has no 'reg' property\n",
1790                         child->full_name);
1791                 return -ENODEV;
1792         }
1793
1794         gpmc_nand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_nand_data),
1795                                       GFP_KERNEL);
1796         if (!gpmc_nand_data)
1797                 return -ENOMEM;
1798
1799         gpmc_nand_data->cs = val;
1800         gpmc_nand_data->of_node = child;
1801
1802         /* Detect availability of ELM module */
1803         gpmc_nand_data->elm_of_node = of_parse_phandle(child, "ti,elm-id", 0);
1804         if (gpmc_nand_data->elm_of_node == NULL)
1805                 gpmc_nand_data->elm_of_node =
1806                                         of_parse_phandle(child, "elm_id", 0);
1807
1808         /* select ecc-scheme for NAND */
1809         if (of_property_read_string(child, "ti,nand-ecc-opt", &s)) {
1810                 pr_err("%s: ti,nand-ecc-opt not found\n", __func__);
1811                 return -ENODEV;
1812         }
1813
1814         if (!strcmp(s, "sw"))
1815                 gpmc_nand_data->ecc_opt = OMAP_ECC_HAM1_CODE_SW;
1816         else if (!strcmp(s, "ham1") ||
1817                  !strcmp(s, "hw") || !strcmp(s, "hw-romcode"))
1818                 gpmc_nand_data->ecc_opt =
1819                                 OMAP_ECC_HAM1_CODE_HW;
1820         else if (!strcmp(s, "bch4"))
1821                 if (gpmc_nand_data->elm_of_node)
1822                         gpmc_nand_data->ecc_opt =
1823                                 OMAP_ECC_BCH4_CODE_HW;
1824                 else
1825                         gpmc_nand_data->ecc_opt =
1826                                 OMAP_ECC_BCH4_CODE_HW_DETECTION_SW;
1827         else if (!strcmp(s, "bch8"))
1828                 if (gpmc_nand_data->elm_of_node)
1829                         gpmc_nand_data->ecc_opt =
1830                                 OMAP_ECC_BCH8_CODE_HW;
1831                 else
1832                         gpmc_nand_data->ecc_opt =
1833                                 OMAP_ECC_BCH8_CODE_HW_DETECTION_SW;
1834         else if (!strcmp(s, "bch16"))
1835                 if (gpmc_nand_data->elm_of_node)
1836                         gpmc_nand_data->ecc_opt =
1837                                 OMAP_ECC_BCH16_CODE_HW;
1838                 else
1839                         pr_err("%s: BCH16 requires ELM support\n", __func__);
1840         else
1841                 pr_err("%s: ti,nand-ecc-opt invalid value\n", __func__);
1842
1843         /* select data transfer mode for NAND controller */
1844         if (!of_property_read_string(child, "ti,nand-xfer-type", &s))
1845                 for (val = 0; val < ARRAY_SIZE(nand_xfer_types); val++)
1846                         if (!strcasecmp(s, nand_xfer_types[val])) {
1847                                 gpmc_nand_data->xfer_type = val;
1848                                 break;
1849                         }
1850
1851         gpmc_nand_data->flash_bbt = of_get_nand_on_flash_bbt(child);
1852
1853         val = of_get_nand_bus_width(child);
1854         if (val == 16)
1855                 gpmc_nand_data->devsize = NAND_BUSWIDTH_16;
1856
1857         gpmc_read_timings_dt(child, &gpmc_t);
1858         gpmc_nand_init(gpmc_nand_data, &gpmc_t);
1859
1860         return 0;
1861 }
1862 #else
1863 static int gpmc_probe_nand_child(struct platform_device *pdev,
1864                                  struct device_node *child)
1865 {
1866         return 0;
1867 }
1868 #endif
1869
1870 #if IS_ENABLED(CONFIG_MTD_ONENAND)
1871 static int gpmc_probe_onenand_child(struct platform_device *pdev,
1872                                  struct device_node *child)
1873 {
1874         u32 val;
1875         struct omap_onenand_platform_data *gpmc_onenand_data;
1876
1877         if (of_property_read_u32(child, "reg", &val) < 0) {
1878                 dev_err(&pdev->dev, "%s has no 'reg' property\n",
1879                         child->full_name);
1880                 return -ENODEV;
1881         }
1882
1883         gpmc_onenand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_onenand_data),
1884                                          GFP_KERNEL);
1885         if (!gpmc_onenand_data)
1886                 return -ENOMEM;
1887
1888         gpmc_onenand_data->cs = val;
1889         gpmc_onenand_data->of_node = child;
1890         gpmc_onenand_data->dma_channel = -1;
1891
1892         if (!of_property_read_u32(child, "dma-channel", &val))
1893                 gpmc_onenand_data->dma_channel = val;
1894
1895         gpmc_onenand_init(gpmc_onenand_data);
1896
1897         return 0;
1898 }
1899 #else
1900 static int gpmc_probe_onenand_child(struct platform_device *pdev,
1901                                     struct device_node *child)
1902 {
1903         return 0;
1904 }
1905 #endif
1906
1907 /**
1908  * gpmc_probe_generic_child - configures the gpmc for a child device
1909  * @pdev:       pointer to gpmc platform device
1910  * @child:      pointer to device-tree node for child device
1911  *
1912  * Allocates and configures a GPMC chip-select for a child device.
1913  * Returns 0 on success and appropriate negative error code on failure.
1914  */
1915 static int gpmc_probe_generic_child(struct platform_device *pdev,
1916                                 struct device_node *child)
1917 {
1918         struct gpmc_settings gpmc_s;
1919         struct gpmc_timings gpmc_t;
1920         struct resource res;
1921         unsigned long base;
1922         const char *name;
1923         int ret, cs;
1924         u32 val;
1925
1926         if (of_property_read_u32(child, "reg", &cs) < 0) {
1927                 dev_err(&pdev->dev, "%s has no 'reg' property\n",
1928                         child->full_name);
1929                 return -ENODEV;
1930         }
1931
1932         if (of_address_to_resource(child, 0, &res) < 0) {
1933                 dev_err(&pdev->dev, "%s has malformed 'reg' property\n",
1934                         child->full_name);
1935                 return -ENODEV;
1936         }
1937
1938         /*
1939          * Check if we have multiple instances of the same device
1940          * on a single chip select. If so, use the already initialized
1941          * timings.
1942          */
1943         name = gpmc_cs_get_name(cs);
1944         if (name && child->name && of_node_cmp(child->name, name) == 0)
1945                         goto no_timings;
1946
1947         ret = gpmc_cs_request(cs, resource_size(&res), &base);
1948         if (ret < 0) {
1949                 dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs);
1950                 return ret;
1951         }
1952         gpmc_cs_set_name(cs, child->name);
1953
1954         gpmc_read_settings_dt(child, &gpmc_s);
1955         gpmc_read_timings_dt(child, &gpmc_t);
1956
1957         /*
1958          * For some GPMC devices we still need to rely on the bootloader
1959          * timings because the devices can be connected via FPGA.
1960          * REVISIT: Add timing support from slls644g.pdf.
1961          */
1962         if (!gpmc_t.cs_rd_off) {
1963                 WARN(1, "enable GPMC debug to configure .dts timings for CS%i\n",
1964                         cs);
1965                 gpmc_cs_show_timings(cs,
1966                                      "please add GPMC bootloader timings to .dts");
1967                 goto no_timings;
1968         }
1969
1970         /* CS must be disabled while making changes to gpmc configuration */
1971         gpmc_cs_disable_mem(cs);
1972
1973         /*
1974          * FIXME: gpmc_cs_request() will map the CS to an arbitary
1975          * location in the gpmc address space. When booting with
1976          * device-tree we want the NOR flash to be mapped to the
1977          * location specified in the device-tree blob. So remap the
1978          * CS to this location. Once DT migration is complete should
1979          * just make gpmc_cs_request() map a specific address.
1980          */
1981         ret = gpmc_cs_remap(cs, res.start);
1982         if (ret < 0) {
1983                 dev_err(&pdev->dev, "cannot remap GPMC CS %d to %pa\n",
1984                         cs, &res.start);
1985                 goto err;
1986         }
1987
1988         ret = of_property_read_u32(child, "bank-width", &gpmc_s.device_width);
1989         if (ret < 0)
1990                 goto err;
1991
1992         ret = gpmc_cs_program_settings(cs, &gpmc_s);
1993         if (ret < 0)
1994                 goto err;
1995
1996         ret = gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
1997         if (ret) {
1998                 dev_err(&pdev->dev, "failed to set gpmc timings for: %s\n",
1999                         child->name);
2000                 goto err;
2001         }
2002
2003         /* Clear limited address i.e. enable A26-A11 */
2004         val = gpmc_read_reg(GPMC_CONFIG);
2005         val &= ~GPMC_CONFIG_LIMITEDADDRESS;
2006         gpmc_write_reg(GPMC_CONFIG, val);
2007
2008         /* Enable CS region */
2009         gpmc_cs_enable_mem(cs);
2010
2011 no_timings:
2012
2013         /* create platform device, NULL on error or when disabled */
2014         if (!of_platform_device_create(child, NULL, &pdev->dev))
2015                 goto err_child_fail;
2016
2017         /* is child a common bus? */
2018         if (of_match_node(of_default_bus_match_table, child))
2019                 /* create children and other common bus children */
2020                 if (of_platform_populate(child, of_default_bus_match_table,
2021                                          NULL, &pdev->dev))
2022                         goto err_child_fail;
2023
2024         return 0;
2025
2026 err_child_fail:
2027
2028         dev_err(&pdev->dev, "failed to create gpmc child %s\n", child->name);
2029         ret = -ENODEV;
2030
2031 err:
2032         gpmc_cs_free(cs);
2033
2034         return ret;
2035 }
2036
2037 static int gpmc_probe_dt(struct platform_device *pdev)
2038 {
2039         int ret;
2040         struct device_node *child;
2041         const struct of_device_id *of_id =
2042                 of_match_device(gpmc_dt_ids, &pdev->dev);
2043
2044         if (!of_id)
2045                 return 0;
2046
2047         ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-cs",
2048                                    &gpmc_cs_num);
2049         if (ret < 0) {
2050                 pr_err("%s: number of chip-selects not defined\n", __func__);
2051                 return ret;
2052         } else if (gpmc_cs_num < 1) {
2053                 pr_err("%s: all chip-selects are disabled\n", __func__);
2054                 return -EINVAL;
2055         } else if (gpmc_cs_num > GPMC_CS_NUM) {
2056                 pr_err("%s: number of supported chip-selects cannot be > %d\n",
2057                                          __func__, GPMC_CS_NUM);
2058                 return -EINVAL;
2059         }
2060
2061         ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins",
2062                                    &gpmc_nr_waitpins);
2063         if (ret < 0) {
2064                 pr_err("%s: number of wait pins not found!\n", __func__);
2065                 return ret;
2066         }
2067
2068         for_each_available_child_of_node(pdev->dev.of_node, child) {
2069
2070                 if (!child->name)
2071                         continue;
2072
2073                 if (of_node_cmp(child->name, "nand") == 0)
2074                         ret = gpmc_probe_nand_child(pdev, child);
2075                 else if (of_node_cmp(child->name, "onenand") == 0)
2076                         ret = gpmc_probe_onenand_child(pdev, child);
2077                 else
2078                         ret = gpmc_probe_generic_child(pdev, child);
2079         }
2080
2081         return 0;
2082 }
2083 #else
2084 static int gpmc_probe_dt(struct platform_device *pdev)
2085 {
2086         return 0;
2087 }
2088 #endif
2089
2090 static int gpmc_probe(struct platform_device *pdev)
2091 {
2092         int rc;
2093         u32 l;
2094         struct resource *res;
2095
2096         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2097         if (res == NULL)
2098                 return -ENOENT;
2099
2100         phys_base = res->start;
2101         mem_size = resource_size(res);
2102
2103         gpmc_base = devm_ioremap_resource(&pdev->dev, res);
2104         if (IS_ERR(gpmc_base))
2105                 return PTR_ERR(gpmc_base);
2106
2107         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2108         if (res == NULL)
2109                 dev_warn(&pdev->dev, "Failed to get resource: irq\n");
2110         else
2111                 gpmc_irq = res->start;
2112
2113         gpmc_l3_clk = devm_clk_get(&pdev->dev, "fck");
2114         if (IS_ERR(gpmc_l3_clk)) {
2115                 dev_err(&pdev->dev, "Failed to get GPMC fck\n");
2116                 gpmc_irq = 0;
2117                 return PTR_ERR(gpmc_l3_clk);
2118         }
2119
2120         if (!clk_get_rate(gpmc_l3_clk)) {
2121                 dev_err(&pdev->dev, "Invalid GPMC fck clock rate\n");
2122                 return -EINVAL;
2123         }
2124
2125         pm_runtime_enable(&pdev->dev);
2126         pm_runtime_get_sync(&pdev->dev);
2127
2128         gpmc_dev = &pdev->dev;
2129
2130         l = gpmc_read_reg(GPMC_REVISION);
2131
2132         /*
2133          * FIXME: Once device-tree migration is complete the below flags
2134          * should be populated based upon the device-tree compatible
2135          * string. For now just use the IP revision. OMAP3+ devices have
2136          * the wr_access and wr_data_mux_bus register fields. OMAP4+
2137          * devices support the addr-addr-data multiplex protocol.
2138          *
2139          * GPMC IP revisions:
2140          * - OMAP24xx                   = 2.0
2141          * - OMAP3xxx                   = 5.0
2142          * - OMAP44xx/54xx/AM335x       = 6.0
2143          */
2144         if (GPMC_REVISION_MAJOR(l) > 0x4)
2145                 gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
2146         if (GPMC_REVISION_MAJOR(l) > 0x5)
2147                 gpmc_capability |= GPMC_HAS_MUX_AAD;
2148         dev_info(gpmc_dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
2149                  GPMC_REVISION_MINOR(l));
2150
2151         gpmc_mem_init();
2152
2153         if (gpmc_setup_irq() < 0)
2154                 dev_warn(gpmc_dev, "gpmc_setup_irq failed\n");
2155
2156         if (!pdev->dev.of_node) {
2157                 gpmc_cs_num      = GPMC_CS_NUM;
2158                 gpmc_nr_waitpins = GPMC_NR_WAITPINS;
2159         }
2160
2161         rc = gpmc_probe_dt(pdev);
2162         if (rc < 0) {
2163                 pm_runtime_put_sync(&pdev->dev);
2164                 dev_err(gpmc_dev, "failed to probe DT parameters\n");
2165                 return rc;
2166         }
2167
2168         return 0;
2169 }
2170
2171 static int gpmc_remove(struct platform_device *pdev)
2172 {
2173         gpmc_free_irq();
2174         gpmc_mem_exit();
2175         pm_runtime_put_sync(&pdev->dev);
2176         pm_runtime_disable(&pdev->dev);
2177         gpmc_dev = NULL;
2178         return 0;
2179 }
2180
2181 #ifdef CONFIG_PM_SLEEP
2182 static int gpmc_suspend(struct device *dev)
2183 {
2184         omap3_gpmc_save_context();
2185         pm_runtime_put_sync(dev);
2186         return 0;
2187 }
2188
2189 static int gpmc_resume(struct device *dev)
2190 {
2191         pm_runtime_get_sync(dev);
2192         omap3_gpmc_restore_context();
2193         return 0;
2194 }
2195 #endif
2196
2197 static SIMPLE_DEV_PM_OPS(gpmc_pm_ops, gpmc_suspend, gpmc_resume);
2198
2199 static struct platform_driver gpmc_driver = {
2200         .probe          = gpmc_probe,
2201         .remove         = gpmc_remove,
2202         .driver         = {
2203                 .name   = DEVICE_NAME,
2204                 .of_match_table = of_match_ptr(gpmc_dt_ids),
2205                 .pm     = &gpmc_pm_ops,
2206         },
2207 };
2208
2209 static __init int gpmc_init(void)
2210 {
2211         return platform_driver_register(&gpmc_driver);
2212 }
2213
2214 static __exit void gpmc_exit(void)
2215 {
2216         platform_driver_unregister(&gpmc_driver);
2217
2218 }
2219
2220 postcore_initcall(gpmc_init);
2221 module_exit(gpmc_exit);
2222
2223 static irqreturn_t gpmc_handle_irq(int irq, void *dev)
2224 {
2225         int i;
2226         u32 regval;
2227
2228         regval = gpmc_read_reg(GPMC_IRQSTATUS);
2229
2230         if (!regval)
2231                 return IRQ_NONE;
2232
2233         for (i = 0; i < GPMC_NR_IRQ; i++)
2234                 if (regval & gpmc_client_irq[i].bitmask)
2235                         generic_handle_irq(gpmc_client_irq[i].irq);
2236
2237         gpmc_write_reg(GPMC_IRQSTATUS, regval);
2238
2239         return IRQ_HANDLED;
2240 }
2241
2242 static struct omap3_gpmc_regs gpmc_context;
2243
2244 void omap3_gpmc_save_context(void)
2245 {
2246         int i;
2247
2248         gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
2249         gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE);
2250         gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
2251         gpmc_context.config = gpmc_read_reg(GPMC_CONFIG);
2252         gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
2253         gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
2254         gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
2255         for (i = 0; i < gpmc_cs_num; i++) {
2256                 gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
2257                 if (gpmc_context.cs_context[i].is_valid) {
2258                         gpmc_context.cs_context[i].config1 =
2259                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
2260                         gpmc_context.cs_context[i].config2 =
2261                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
2262                         gpmc_context.cs_context[i].config3 =
2263                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
2264                         gpmc_context.cs_context[i].config4 =
2265                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
2266                         gpmc_context.cs_context[i].config5 =
2267                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
2268                         gpmc_context.cs_context[i].config6 =
2269                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
2270                         gpmc_context.cs_context[i].config7 =
2271                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
2272                 }
2273         }
2274 }
2275
2276 void omap3_gpmc_restore_context(void)
2277 {
2278         int i;
2279
2280         gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig);
2281         gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable);
2282         gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl);
2283         gpmc_write_reg(GPMC_CONFIG, gpmc_context.config);
2284         gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
2285         gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
2286         gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
2287         for (i = 0; i < gpmc_cs_num; i++) {
2288                 if (gpmc_context.cs_context[i].is_valid) {
2289                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
2290                                 gpmc_context.cs_context[i].config1);
2291                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
2292                                 gpmc_context.cs_context[i].config2);
2293                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
2294                                 gpmc_context.cs_context[i].config3);
2295                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
2296                                 gpmc_context.cs_context[i].config4);
2297                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
2298                                 gpmc_context.cs_context[i].config5);
2299                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
2300                                 gpmc_context.cs_context[i].config6);
2301                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
2302                                 gpmc_context.cs_context[i].config7);
2303                 }
2304         }
2305 }