2 * Elonics E4000 silicon tuner driver
4 * Copyright (C) 2012 Antti Palosaari <crope@iki.fi>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
21 #include "e4000_priv.h"
23 /* Max transfer size done by I2C transfer functions */
24 #define MAX_XFER_SIZE 64
26 /* write multiple registers */
27 static int e4000_wr_regs(struct e4000_priv *priv, u8 reg, u8 *val, int len)
30 u8 buf[MAX_XFER_SIZE];
31 struct i2c_msg msg[1] = {
33 .addr = priv->cfg->i2c_addr,
40 if (1 + len > sizeof(buf)) {
41 dev_warn(&priv->i2c->dev,
42 "%s: i2c wr reg=%04x: len=%d is too big!\n",
43 KBUILD_MODNAME, reg, len);
48 memcpy(&buf[1], val, len);
50 ret = i2c_transfer(priv->i2c, msg, 1);
54 dev_warn(&priv->i2c->dev,
55 "%s: i2c wr failed=%d reg=%02x len=%d\n",
56 KBUILD_MODNAME, ret, reg, len);
62 /* read multiple registers */
63 static int e4000_rd_regs(struct e4000_priv *priv, u8 reg, u8 *val, int len)
66 u8 buf[MAX_XFER_SIZE];
67 struct i2c_msg msg[2] = {
69 .addr = priv->cfg->i2c_addr,
74 .addr = priv->cfg->i2c_addr,
81 if (len > sizeof(buf)) {
82 dev_warn(&priv->i2c->dev,
83 "%s: i2c rd reg=%04x: len=%d is too big!\n",
84 KBUILD_MODNAME, reg, len);
88 ret = i2c_transfer(priv->i2c, msg, 2);
90 memcpy(val, buf, len);
93 dev_warn(&priv->i2c->dev,
94 "%s: i2c rd failed=%d reg=%02x len=%d\n",
95 KBUILD_MODNAME, ret, reg, len);
102 /* write single register */
103 static int e4000_wr_reg(struct e4000_priv *priv, u8 reg, u8 val)
105 return e4000_wr_regs(priv, reg, &val, 1);
108 /* read single register */
109 static int e4000_rd_reg(struct e4000_priv *priv, u8 reg, u8 *val)
111 return e4000_rd_regs(priv, reg, val, 1);
114 static int e4000_init(struct dvb_frontend *fe)
116 struct e4000_priv *priv = fe->tuner_priv;
119 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
121 if (fe->ops.i2c_gate_ctrl)
122 fe->ops.i2c_gate_ctrl(fe, 1);
124 /* dummy I2C to ensure I2C wakes up */
125 ret = e4000_wr_reg(priv, 0x02, 0x40);
128 ret = e4000_wr_reg(priv, 0x00, 0x01);
132 /* disable output clock */
133 ret = e4000_wr_reg(priv, 0x06, 0x00);
137 ret = e4000_wr_reg(priv, 0x7a, 0x96);
141 /* configure gains */
142 ret = e4000_wr_regs(priv, 0x7e, "\x01\xfe", 2);
146 ret = e4000_wr_reg(priv, 0x82, 0x00);
150 ret = e4000_wr_reg(priv, 0x24, 0x05);
154 ret = e4000_wr_regs(priv, 0x87, "\x20\x01", 2);
158 ret = e4000_wr_regs(priv, 0x9f, "\x7f\x07", 2);
162 /* DC offset control */
163 ret = e4000_wr_reg(priv, 0x2d, 0x1f);
167 ret = e4000_wr_regs(priv, 0x70, "\x01\x01", 2);
172 ret = e4000_wr_reg(priv, 0x1a, 0x17);
176 ret = e4000_wr_reg(priv, 0x1f, 0x1a);
180 if (fe->ops.i2c_gate_ctrl)
181 fe->ops.i2c_gate_ctrl(fe, 0);
185 if (fe->ops.i2c_gate_ctrl)
186 fe->ops.i2c_gate_ctrl(fe, 0);
188 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
192 static int e4000_sleep(struct dvb_frontend *fe)
194 struct e4000_priv *priv = fe->tuner_priv;
197 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
199 if (fe->ops.i2c_gate_ctrl)
200 fe->ops.i2c_gate_ctrl(fe, 1);
202 ret = e4000_wr_reg(priv, 0x00, 0x00);
206 if (fe->ops.i2c_gate_ctrl)
207 fe->ops.i2c_gate_ctrl(fe, 0);
211 if (fe->ops.i2c_gate_ctrl)
212 fe->ops.i2c_gate_ctrl(fe, 0);
214 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
218 static int e4000_set_params(struct dvb_frontend *fe)
220 struct e4000_priv *priv = fe->tuner_priv;
221 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
222 int ret, i, sigma_delta;
224 u8 buf[5], i_data[4], q_data[4];
226 dev_dbg(&priv->i2c->dev,
227 "%s: delivery_system=%d frequency=%d bandwidth_hz=%d\n",
228 __func__, c->delivery_system, c->frequency,
231 if (fe->ops.i2c_gate_ctrl)
232 fe->ops.i2c_gate_ctrl(fe, 1);
234 /* gain control manual */
235 ret = e4000_wr_reg(priv, 0x1a, 0x00);
240 for (i = 0; i < ARRAY_SIZE(e4000_pll_lut); i++) {
241 if (c->frequency <= e4000_pll_lut[i].freq)
245 if (i == ARRAY_SIZE(e4000_pll_lut))
249 * Note: Currently f_vco overflows when c->frequency is 1 073 741 824 Hz
252 f_vco = c->frequency * e4000_pll_lut[i].mul;
253 sigma_delta = 0x10000UL * (f_vco % priv->cfg->clock) / priv->cfg->clock;
254 buf[0] = f_vco / priv->cfg->clock;
255 buf[1] = (sigma_delta >> 0) & 0xff;
256 buf[2] = (sigma_delta >> 8) & 0xff;
258 buf[4] = e4000_pll_lut[i].div;
260 dev_dbg(&priv->i2c->dev, "%s: f_vco=%u pll div=%d sigma_delta=%04x\n",
261 __func__, f_vco, buf[0], sigma_delta);
263 ret = e4000_wr_regs(priv, 0x09, buf, 5);
267 /* LNA filter (RF filter) */
268 for (i = 0; i < ARRAY_SIZE(e400_lna_filter_lut); i++) {
269 if (c->frequency <= e400_lna_filter_lut[i].freq)
273 if (i == ARRAY_SIZE(e400_lna_filter_lut))
276 ret = e4000_wr_reg(priv, 0x10, e400_lna_filter_lut[i].val);
281 for (i = 0; i < ARRAY_SIZE(e4000_if_filter_lut); i++) {
282 if (c->bandwidth_hz <= e4000_if_filter_lut[i].freq)
286 if (i == ARRAY_SIZE(e4000_if_filter_lut))
289 buf[0] = e4000_if_filter_lut[i].reg11_val;
290 buf[1] = e4000_if_filter_lut[i].reg12_val;
292 ret = e4000_wr_regs(priv, 0x11, buf, 2);
297 for (i = 0; i < ARRAY_SIZE(e4000_band_lut); i++) {
298 if (c->frequency <= e4000_band_lut[i].freq)
302 if (i == ARRAY_SIZE(e4000_band_lut))
305 ret = e4000_wr_reg(priv, 0x07, e4000_band_lut[i].reg07_val);
309 ret = e4000_wr_reg(priv, 0x78, e4000_band_lut[i].reg78_val);
314 for (i = 0; i < 4; i++) {
316 ret = e4000_wr_regs(priv, 0x15, "\x00\x7e\x24", 3);
318 ret = e4000_wr_regs(priv, 0x15, "\x00\x7f", 2);
320 ret = e4000_wr_regs(priv, 0x15, "\x01", 1);
322 ret = e4000_wr_regs(priv, 0x16, "\x7e", 1);
327 ret = e4000_wr_reg(priv, 0x29, 0x01);
331 ret = e4000_rd_regs(priv, 0x2a, buf, 3);
335 i_data[i] = (((buf[2] >> 0) & 0x3) << 6) | (buf[0] & 0x3f);
336 q_data[i] = (((buf[2] >> 4) & 0x3) << 6) | (buf[1] & 0x3f);
339 swap(q_data[2], q_data[3]);
340 swap(i_data[2], i_data[3]);
342 ret = e4000_wr_regs(priv, 0x50, q_data, 4);
346 ret = e4000_wr_regs(priv, 0x60, i_data, 4);
350 /* gain control auto */
351 ret = e4000_wr_reg(priv, 0x1a, 0x17);
355 if (fe->ops.i2c_gate_ctrl)
356 fe->ops.i2c_gate_ctrl(fe, 0);
360 if (fe->ops.i2c_gate_ctrl)
361 fe->ops.i2c_gate_ctrl(fe, 0);
363 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
367 static int e4000_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
369 struct e4000_priv *priv = fe->tuner_priv;
371 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
373 *frequency = 0; /* Zero-IF */
378 static int e4000_release(struct dvb_frontend *fe)
380 struct e4000_priv *priv = fe->tuner_priv;
382 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
384 kfree(fe->tuner_priv);
389 static const struct dvb_tuner_ops e4000_tuner_ops = {
391 .name = "Elonics E4000",
392 .frequency_min = 174000000,
393 .frequency_max = 862000000,
396 .release = e4000_release,
399 .sleep = e4000_sleep,
400 .set_params = e4000_set_params,
402 .get_if_frequency = e4000_get_if_frequency,
405 struct dvb_frontend *e4000_attach(struct dvb_frontend *fe,
406 struct i2c_adapter *i2c, const struct e4000_config *cfg)
408 struct e4000_priv *priv;
412 if (fe->ops.i2c_gate_ctrl)
413 fe->ops.i2c_gate_ctrl(fe, 1);
415 priv = kzalloc(sizeof(struct e4000_priv), GFP_KERNEL);
418 dev_err(&i2c->dev, "%s: kzalloc() failed\n", KBUILD_MODNAME);
425 /* check if the tuner is there */
426 ret = e4000_rd_reg(priv, 0x02, &chip_id);
430 dev_dbg(&priv->i2c->dev, "%s: chip_id=%02x\n", __func__, chip_id);
435 /* put sleep as chip seems to be in normal mode by default */
436 ret = e4000_wr_reg(priv, 0x00, 0x00);
440 dev_info(&priv->i2c->dev,
441 "%s: Elonics E4000 successfully identified\n",
444 fe->tuner_priv = priv;
445 memcpy(&fe->ops.tuner_ops, &e4000_tuner_ops,
446 sizeof(struct dvb_tuner_ops));
448 if (fe->ops.i2c_gate_ctrl)
449 fe->ops.i2c_gate_ctrl(fe, 0);
453 if (fe->ops.i2c_gate_ctrl)
454 fe->ops.i2c_gate_ctrl(fe, 0);
456 dev_dbg(&i2c->dev, "%s: failed=%d\n", __func__, ret);
460 EXPORT_SYMBOL(e4000_attach);
462 MODULE_DESCRIPTION("Elonics E4000 silicon tuner driver");
463 MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
464 MODULE_LICENSE("GPL");