drivers/irqchip/irq-gic-v3-its.c

   1 /*
   2  * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved.
   3  * Author: Marc Zyngier <marc.zyngier@arm.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include <linux/bitmap.h>
  19 #include <linux/cpu.h>
  20 #include <linux/delay.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/log2.h>
  23 #include <linux/mm.h>
  24 #include <linux/msi.h>
  25 #include <linux/of.h>
  26 #include <linux/of_address.h>
  27 #include <linux/of_irq.h>
  28 #include <linux/of_pci.h>
  29 #include <linux/of_platform.h>
  30 #include <linux/percpu.h>
  31 #include <linux/slab.h>
  32
  33 #include <linux/irqchip/arm-gic-v3.h>
  34
  35 #include <asm/cacheflush.h>
  36 #include <asm/cputype.h>
  37 #include <asm/exception.h>
  38
  39 #include "irqchip.h"
  40
  41 #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING           (1 << 0)
  42
  43 #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING     (1 << 0)
  44
  45 /*
  46  * Collection structure - just an ID, and a redistributor address to
  47  * ping. We use one per CPU as a bag of interrupts assigned to this
  48  * CPU.
  49  */
  50 struct its_collection {
  51         u64                     target_address;
  52         u16                     col_id;
  53 };
  54
  55 /*
  56  * The ITS structure - contains most of the infrastructure, with the
  57  * msi_controller, the command queue, the collections, and the list of
  58  * devices writing to it.
  59  */
  60 struct its_node {
  61         raw_spinlock_t          lock;
  62         struct list_head        entry;
  63         struct msi_controller   msi_chip;
  64         struct irq_domain       *domain;
  65         void __iomem            *base;
  66         unsigned long           phys_base;
  67         struct its_cmd_block    *cmd_base;
  68         struct its_cmd_block    *cmd_write;
  69         void                    *tables[GITS_BASER_NR_REGS];
  70         struct its_collection   *collections;
  71         struct list_head        its_device_list;
  72         u64                     flags;
  73         u32                     ite_size;
  74 };
  75
  76 #define ITS_ITT_ALIGN           SZ_256
  77
  78 /*
  79  * The ITS view of a device - belongs to an ITS, a collection, owns an
  80  * interrupt translation table, and a list of interrupts.
  81  */
  82 struct its_device {
  83         struct list_head        entry;
  84         struct its_node         *its;
  85         struct its_collection   *collection;
  86         void                    *itt;
  87         unsigned long           *lpi_map;
  88         irq_hw_number_t         lpi_base;
  89         int                     nr_lpis;
  90         u32                     nr_ites;
  91         u32                     device_id;
  92 };
  93
  94 static LIST_HEAD(its_nodes);
  95 static DEFINE_SPINLOCK(its_lock);
  96 static struct device_node *gic_root_node;
  97 static struct rdists *gic_rdists;
  98
  99 #define gic_data_rdist()                (raw_cpu_ptr(gic_rdists->rdist))
 100 #define gic_data_rdist_rd_base()        (gic_data_rdist()->rd_base)
 101
 102 /*
 103  * ITS command descriptors - parameters to be encoded in a command
 104  * block.
 105  */
 106 struct its_cmd_desc {
 107         union {
 108                 struct {
 109                         struct its_device *dev;
 110                         u32 event_id;
 111                 } its_inv_cmd;
 112
 113                 struct {
 114                         struct its_device *dev;
 115                         u32 event_id;
 116                 } its_int_cmd;
 117
 118                 struct {
 119                         struct its_device *dev;
 120                         int valid;
 121                 } its_mapd_cmd;
 122
 123                 struct {
 124                         struct its_collection *col;
 125                         int valid;
 126                 } its_mapc_cmd;
 127
 128                 struct {
 129                         struct its_device *dev;
 130                         u32 phys_id;
 131                         u32 event_id;
 132                 } its_mapvi_cmd;
 133
 134                 struct {
 135                         struct its_device *dev;
 136                         struct its_collection *col;
 137                         u32 id;
 138                 } its_movi_cmd;
 139
 140                 struct {
 141                         struct its_device *dev;
 142                         u32 event_id;
 143                 } its_discard_cmd;
 144
 145                 struct {
 146                         struct its_collection *col;
 147                 } its_invall_cmd;
 148         };
 149 };
 150
 151 /*
 152  * The ITS command block, which is what the ITS actually parses.
 153  */
 154 struct its_cmd_block {
 155         u64     raw_cmd[4];
 156 };
 157
 158 #define ITS_CMD_QUEUE_SZ                SZ_64K
 159 #define ITS_CMD_QUEUE_NR_ENTRIES        (ITS_CMD_QUEUE_SZ / sizeof(struct its_cmd_block))
 160
 161 typedef struct its_collection *(*its_cmd_builder_t)(struct its_cmd_block *,
 162                                                     struct its_cmd_desc *);
 163
 164 static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr)
 165 {
 166         cmd->raw_cmd[0] &= ~0xffUL;
 167         cmd->raw_cmd[0] |= cmd_nr;
 168 }
 169
 170 static void its_encode_devid(struct its_cmd_block *cmd, u32 devid)
 171 {
 172         cmd->raw_cmd[0] &= ~(0xffffUL << 32);
 173         cmd->raw_cmd[0] |= ((u64)devid) << 32;
 174 }
 175
 176 static void its_encode_event_id(struct its_cmd_block *cmd, u32 id)
 177 {
 178         cmd->raw_cmd[1] &= ~0xffffffffUL;
 179         cmd->raw_cmd[1] |= id;
 180 }
 181
 182 static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id)
 183 {
 184         cmd->raw_cmd[1] &= 0xffffffffUL;
 185         cmd->raw_cmd[1] |= ((u64)phys_id) << 32;
 186 }
 187
 188 static void its_encode_size(struct its_cmd_block *cmd, u8 size)
 189 {
 190         cmd->raw_cmd[1] &= ~0x1fUL;
 191         cmd->raw_cmd[1] |= size & 0x1f;
 192 }
 193
 194 static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr)
 195 {
 196         cmd->raw_cmd[2] &= ~0xffffffffffffUL;
 197         cmd->raw_cmd[2] |= itt_addr & 0xffffffffff00UL;
 198 }
 199
 200 static void its_encode_valid(struct its_cmd_block *cmd, int valid)
 201 {
 202         cmd->raw_cmd[2] &= ~(1UL << 63);
 203         cmd->raw_cmd[2] |= ((u64)!!valid) << 63;
 204 }
 205
 206 static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr)
 207 {
 208         cmd->raw_cmd[2] &= ~(0xffffffffUL << 16);
 209         cmd->raw_cmd[2] |= (target_addr & (0xffffffffUL << 16));
 210 }
 211
 212 static void its_encode_collection(struct its_cmd_block *cmd, u16 col)
 213 {
 214         cmd->raw_cmd[2] &= ~0xffffUL;
 215         cmd->raw_cmd[2] |= col;
 216 }
 217
 218 static inline void its_fixup_cmd(struct its_cmd_block *cmd)
 219 {
 220         /* Let's fixup BE commands */
 221         cmd->raw_cmd[0] = cpu_to_le64(cmd->raw_cmd[0]);
 222         cmd->raw_cmd[1] = cpu_to_le64(cmd->raw_cmd[1]);
 223         cmd->raw_cmd[2] = cpu_to_le64(cmd->raw_cmd[2]);
 224         cmd->raw_cmd[3] = cpu_to_le64(cmd->raw_cmd[3]);
 225 }
 226
 227 static struct its_collection *its_build_mapd_cmd(struct its_cmd_block *cmd,
 228                                                  struct its_cmd_desc *desc)
 229 {
 230         unsigned long itt_addr;
 231         u8 size = ilog2(desc->its_mapd_cmd.dev->nr_ites);
 232
 233         itt_addr = virt_to_phys(desc->its_mapd_cmd.dev->itt);
 234         itt_addr = ALIGN(itt_addr, ITS_ITT_ALIGN);
 235
 236         its_encode_cmd(cmd, GITS_CMD_MAPD);
 237         its_encode_devid(cmd, desc->its_mapd_cmd.dev->device_id);
 238         its_encode_size(cmd, size - 1);
 239         its_encode_itt(cmd, itt_addr);
 240         its_encode_valid(cmd, desc->its_mapd_cmd.valid);
 241
 242         its_fixup_cmd(cmd);
 243
 244         return desc->its_mapd_cmd.dev->collection;
 245 }
 246
 247 static struct its_collection *its_build_mapc_cmd(struct its_cmd_block *cmd,
 248                                                  struct its_cmd_desc *desc)
 249 {
 250         its_encode_cmd(cmd, GITS_CMD_MAPC);
 251         its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id);
 252         its_encode_target(cmd, desc->its_mapc_cmd.col->target_address);
 253         its_encode_valid(cmd, desc->its_mapc_cmd.valid);
 254
 255         its_fixup_cmd(cmd);
 256
 257         return desc->its_mapc_cmd.col;
 258 }
 259
 260 static struct its_collection *its_build_mapvi_cmd(struct its_cmd_block *cmd,
 261                                                   struct its_cmd_desc *desc)
 262 {
 263         its_encode_cmd(cmd, GITS_CMD_MAPVI);
 264         its_encode_devid(cmd, desc->its_mapvi_cmd.dev->device_id);
 265         its_encode_event_id(cmd, desc->its_mapvi_cmd.event_id);
 266         its_encode_phys_id(cmd, desc->its_mapvi_cmd.phys_id);
 267         its_encode_collection(cmd, desc->its_mapvi_cmd.dev->collection->col_id);
 268
 269         its_fixup_cmd(cmd);
 270
 271         return desc->its_mapvi_cmd.dev->collection;
 272 }
 273
 274 static struct its_collection *its_build_movi_cmd(struct its_cmd_block *cmd,
 275                                                  struct its_cmd_desc *desc)
 276 {
 277         its_encode_cmd(cmd, GITS_CMD_MOVI);
 278         its_encode_devid(cmd, desc->its_movi_cmd.dev->device_id);
 279         its_encode_event_id(cmd, desc->its_movi_cmd.id);
 280         its_encode_collection(cmd, desc->its_movi_cmd.col->col_id);
 281
 282         its_fixup_cmd(cmd);
 283
 284         return desc->its_movi_cmd.dev->collection;
 285 }
 286
 287 static struct its_collection *its_build_discard_cmd(struct its_cmd_block *cmd,
 288                                                     struct its_cmd_desc *desc)
 289 {
 290         its_encode_cmd(cmd, GITS_CMD_DISCARD);
 291         its_encode_devid(cmd, desc->its_discard_cmd.dev->device_id);
 292         its_encode_event_id(cmd, desc->its_discard_cmd.event_id);
 293
 294         its_fixup_cmd(cmd);
 295
 296         return desc->its_discard_cmd.dev->collection;
 297 }
 298
 299 static struct its_collection *its_build_inv_cmd(struct its_cmd_block *cmd,
 300                                                 struct its_cmd_desc *desc)
 301 {
 302         its_encode_cmd(cmd, GITS_CMD_INV);
 303         its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id);
 304         its_encode_event_id(cmd, desc->its_inv_cmd.event_id);
 305
 306         its_fixup_cmd(cmd);
 307
 308         return desc->its_inv_cmd.dev->collection;
 309 }
 310
 311 static struct its_collection *its_build_invall_cmd(struct its_cmd_block *cmd,
 312                                                    struct its_cmd_desc *desc)
 313 {
 314         its_encode_cmd(cmd, GITS_CMD_INVALL);
 315         its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id);
 316
 317         its_fixup_cmd(cmd);
 318
 319         return NULL;
 320 }
 321
 322 static u64 its_cmd_ptr_to_offset(struct its_node *its,
 323                                  struct its_cmd_block *ptr)
 324 {
 325         return (ptr - its->cmd_base) * sizeof(*ptr);
 326 }
 327
 328 static int its_queue_full(struct its_node *its)
 329 {
 330         int widx;
 331         int ridx;
 332
 333         widx = its->cmd_write - its->cmd_base;
 334         ridx = readl_relaxed(its->base + GITS_CREADR) / sizeof(struct its_cmd_block);
 335
 336         /* This is incredibly unlikely to happen, unless the ITS locks up. */
 337         if (((widx + 1) % ITS_CMD_QUEUE_NR_ENTRIES) == ridx)
 338                 return 1;
 339
 340         return 0;
 341 }
 342
 343 static struct its_cmd_block *its_allocate_entry(struct its_node *its)
 344 {
 345         struct its_cmd_block *cmd;
 346         u32 count = 1000000;    /* 1s! */
 347
 348         while (its_queue_full(its)) {
 349                 count--;
 350                 if (!count) {
 351                         pr_err_ratelimited("ITS queue not draining\n");
 352                         return NULL;
 353                 }
 354                 cpu_relax();
 355                 udelay(1);
 356         }
 357
 358         cmd = its->cmd_write++;
 359
 360         /* Handle queue wrapping */
 361         if (its->cmd_write == (its->cmd_base + ITS_CMD_QUEUE_NR_ENTRIES))
 362                 its->cmd_write = its->cmd_base;
 363
 364         return cmd;
 365 }
 366
 367 static struct its_cmd_block *its_post_commands(struct its_node *its)
 368 {
 369         u64 wr = its_cmd_ptr_to_offset(its, its->cmd_write);
 370
 371         writel_relaxed(wr, its->base + GITS_CWRITER);
 372
 373         return its->cmd_write;
 374 }
 375
 376 static void its_flush_cmd(struct its_node *its, struct its_cmd_block *cmd)
 377 {
 378         /*
 379          * Make sure the commands written to memory are observable by
 380          * the ITS.
 381          */
 382         if (its->flags & ITS_FLAGS_CMDQ_NEEDS_FLUSHING)
 383                 __flush_dcache_area(cmd, sizeof(*cmd));
 384         else
 385                 dsb(ishst);
 386 }
 387
 388 static void its_wait_for_range_completion(struct its_node *its,
 389                                           struct its_cmd_block *from,
 390                                           struct its_cmd_block *to)
 391 {
 392         u64 rd_idx, from_idx, to_idx;
 393         u32 count = 1000000;    /* 1s! */
 394
 395         from_idx = its_cmd_ptr_to_offset(its, from);
 396         to_idx = its_cmd_ptr_to_offset(its, to);
 397
 398         while (1) {
 399                 rd_idx = readl_relaxed(its->base + GITS_CREADR);
 400                 if (rd_idx >= to_idx || rd_idx < from_idx)
 401                         break;
 402
 403                 count--;
 404                 if (!count) {
 405                         pr_err_ratelimited("ITS queue timeout\n");
 406                         return;
 407                 }
 408                 cpu_relax();
 409                 udelay(1);
 410         }
 411 }
 412
 413 static void its_send_single_command(struct its_node *its,
 414                                     its_cmd_builder_t builder,
 415                                     struct its_cmd_desc *desc)
 416 {
 417         struct its_cmd_block *cmd, *sync_cmd, *next_cmd;
 418         struct its_collection *sync_col;
 419         unsigned long flags;
 420
 421         raw_spin_lock_irqsave(&its->lock, flags);
 422
 423         cmd = its_allocate_entry(its);
 424         if (!cmd) {             /* We're soooooo screewed... */
 425                 pr_err_ratelimited("ITS can't allocate, dropping command\n");
 426                 raw_spin_unlock_irqrestore(&its->lock, flags);
 427                 return;
 428         }
 429         sync_col = builder(cmd, desc);
 430         its_flush_cmd(its, cmd);
 431
 432         if (sync_col) {
 433                 sync_cmd = its_allocate_entry(its);
 434                 if (!sync_cmd) {
 435                         pr_err_ratelimited("ITS can't SYNC, skipping\n");
 436                         goto post;
 437                 }
 438                 its_encode_cmd(sync_cmd, GITS_CMD_SYNC);
 439                 its_encode_target(sync_cmd, sync_col->target_address);
 440                 its_fixup_cmd(sync_cmd);
 441                 its_flush_cmd(its, sync_cmd);
 442         }
 443
 444 post:
 445         next_cmd = its_post_commands(its);
 446         raw_spin_unlock_irqrestore(&its->lock, flags);
 447
 448         its_wait_for_range_completion(its, cmd, next_cmd);
 449 }
 450
 451 static void its_send_inv(struct its_device *dev, u32 event_id)
 452 {
 453         struct its_cmd_desc desc;
 454
 455         desc.its_inv_cmd.dev = dev;
 456         desc.its_inv_cmd.event_id = event_id;
 457
 458         its_send_single_command(dev->its, its_build_inv_cmd, &desc);
 459 }
 460
 461 static void its_send_mapd(struct its_device *dev, int valid)
 462 {
 463         struct its_cmd_desc desc;
 464
 465         desc.its_mapd_cmd.dev = dev;
 466         desc.its_mapd_cmd.valid = !!valid;
 467
 468         its_send_single_command(dev->its, its_build_mapd_cmd, &desc);
 469 }
 470
 471 static void its_send_mapc(struct its_node *its, struct its_collection *col,
 472                           int valid)
 473 {
 474         struct its_cmd_desc desc;
 475
 476         desc.its_mapc_cmd.col = col;
 477         desc.its_mapc_cmd.valid = !!valid;
 478
 479         its_send_single_command(its, its_build_mapc_cmd, &desc);
 480 }
 481
 482 static void its_send_mapvi(struct its_device *dev, u32 irq_id, u32 id)
 483 {
 484         struct its_cmd_desc desc;
 485
 486         desc.its_mapvi_cmd.dev = dev;
 487         desc.its_mapvi_cmd.phys_id = irq_id;
 488         desc.its_mapvi_cmd.event_id = id;
 489
 490         its_send_single_command(dev->its, its_build_mapvi_cmd, &desc);
 491 }
 492
 493 static void its_send_movi(struct its_device *dev,
 494                           struct its_collection *col, u32 id)
 495 {
 496         struct its_cmd_desc desc;
 497
 498         desc.its_movi_cmd.dev = dev;
 499         desc.its_movi_cmd.col = col;
 500         desc.its_movi_cmd.id = id;
 501
 502         its_send_single_command(dev->its, its_build_movi_cmd, &desc);
 503 }
 504
 505 static void its_send_discard(struct its_device *dev, u32 id)
 506 {
 507         struct its_cmd_desc desc;
 508
 509         desc.its_discard_cmd.dev = dev;
 510         desc.its_discard_cmd.event_id = id;
 511
 512         its_send_single_command(dev->its, its_build_discard_cmd, &desc);
 513 }
 514
 515 static void its_send_invall(struct its_node *its, struct its_collection *col)
 516 {
 517         struct its_cmd_desc desc;
 518
 519         desc.its_invall_cmd.col = col;
 520
 521         its_send_single_command(its, its_build_invall_cmd, &desc);
 522 }
 523
 524 /*
 525  * irqchip functions - assumes MSI, mostly.
 526  */
 527
 528 static inline u32 its_get_event_id(struct irq_data *d)
 529 {
 530         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
 531         return d->hwirq - its_dev->lpi_base;
 532 }
 533
 534 static void lpi_set_config(struct irq_data *d, bool enable)
 535 {
 536         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
 537         irq_hw_number_t hwirq = d->hwirq;
 538         u32 id = its_get_event_id(d);
 539         u8 *cfg = page_address(gic_rdists->prop_page) + hwirq - 8192;
 540
 541         if (enable)
 542                 *cfg |= LPI_PROP_ENABLED;
 543         else
 544                 *cfg &= ~LPI_PROP_ENABLED;
 545
 546         /*
 547          * Make the above write visible to the redistributors.
 548          * And yes, we're flushing exactly: One. Single. Byte.
 549          * Humpf...
 550          */
 551         if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING)
 552                 __flush_dcache_area(cfg, sizeof(*cfg));
 553         else
 554                 dsb(ishst);
 555         its_send_inv(its_dev, id);
 556 }
 557
 558 static void its_mask_irq(struct irq_data *d)
 559 {
 560         lpi_set_config(d, false);
 561 }
 562
 563 static void its_unmask_irq(struct irq_data *d)
 564 {
 565         lpi_set_config(d, true);
 566 }
 567
 568 static void its_eoi_irq(struct irq_data *d)
 569 {
 570         gic_write_eoir(d->hwirq);
 571 }
 572
 573 static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
 574                             bool force)
 575 {
 576         unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask);
 577         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
 578         struct its_collection *target_col;
 579         u32 id = its_get_event_id(d);
 580
 581         if (cpu >= nr_cpu_ids)
 582                 return -EINVAL;
 583
 584         target_col = &its_dev->its->collections[cpu];
 585         its_send_movi(its_dev, target_col, id);
 586         its_dev->collection = target_col;
 587
 588         return IRQ_SET_MASK_OK_DONE;
 589 }
 590
 591 static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg)
 592 {
 593         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
 594         struct its_node *its;
 595         u64 addr;
 596
 597         its = its_dev->its;
 598         addr = its->phys_base + GITS_TRANSLATER;
 599
 600         msg->address_lo         = addr & ((1UL << 32) - 1);
 601         msg->address_hi         = addr >> 32;
 602         msg->data               = its_get_event_id(d);
 603 }
 604
 605 static struct irq_chip its_irq_chip = {
 606         .name                   = "ITS",
 607         .irq_mask               = its_mask_irq,
 608         .irq_unmask             = its_unmask_irq,
 609         .irq_eoi                = its_eoi_irq,
 610         .irq_set_affinity       = its_set_affinity,
 611         .irq_compose_msi_msg    = its_irq_compose_msi_msg,
 612 };
 613
 614 static void its_mask_msi_irq(struct irq_data *d)
 615 {
 616         pci_msi_mask_irq(d);
 617         irq_chip_mask_parent(d);
 618 }
 619
 620 static void its_unmask_msi_irq(struct irq_data *d)
 621 {
 622         pci_msi_unmask_irq(d);
 623         irq_chip_unmask_parent(d);
 624 }
 625
 626 static struct irq_chip its_msi_irq_chip = {
 627         .name                   = "ITS-MSI",
 628         .irq_unmask             = its_unmask_msi_irq,
 629         .irq_mask               = its_mask_msi_irq,
 630         .irq_eoi                = irq_chip_eoi_parent,
 631         .irq_write_msi_msg      = pci_msi_domain_write_msg,
 632 };
 633
 634 /*
 635  * How we allocate LPIs:
 636  *
 637  * The GIC has id_bits bits for interrupt identifiers. From there, we
 638  * must subtract 8192 which are reserved for SGIs/PPIs/SPIs. Then, as
 639  * we allocate LPIs by chunks of 32, we can shift the whole thing by 5
 640  * bits to the right.
 641  *
 642  * This gives us (((1UL << id_bits) - 8192) >> 5) possible allocations.
 643  */
 644 #define IRQS_PER_CHUNK_SHIFT    5
 645 #define IRQS_PER_CHUNK          (1 << IRQS_PER_CHUNK_SHIFT)
 646
 647 static unsigned long *lpi_bitmap;
 648 static u32 lpi_chunks;
 649 static DEFINE_SPINLOCK(lpi_lock);
 650
 651 static int its_lpi_to_chunk(int lpi)
 652 {
 653         return (lpi - 8192) >> IRQS_PER_CHUNK_SHIFT;
 654 }
 655
 656 static int its_chunk_to_lpi(int chunk)
 657 {
 658         return (chunk << IRQS_PER_CHUNK_SHIFT) + 8192;
 659 }
 660
 661 static int its_lpi_init(u32 id_bits)
 662 {
 663         lpi_chunks = its_lpi_to_chunk(1UL << id_bits);
 664
 665         lpi_bitmap = kzalloc(BITS_TO_LONGS(lpi_chunks) * sizeof(long),
 666                              GFP_KERNEL);
 667         if (!lpi_bitmap) {
 668                 lpi_chunks = 0;
 669                 return -ENOMEM;
 670         }
 671
 672         pr_info("ITS: Allocated %d chunks for LPIs\n", (int)lpi_chunks);
 673         return 0;
 674 }
 675
 676 static unsigned long *its_lpi_alloc_chunks(int nr_irqs, int *base, int *nr_ids)
 677 {
 678         unsigned long *bitmap = NULL;
 679         int chunk_id;
 680         int nr_chunks;
 681         int i;
 682
 683         nr_chunks = DIV_ROUND_UP(nr_irqs, IRQS_PER_CHUNK);
 684
 685         spin_lock(&lpi_lock);
 686
 687         do {
 688                 chunk_id = bitmap_find_next_zero_area(lpi_bitmap, lpi_chunks,
 689                                                       0, nr_chunks, 0);
 690                 if (chunk_id < lpi_chunks)
 691                         break;
 692
 693                 nr_chunks--;
 694         } while (nr_chunks > 0);
 695
 696         if (!nr_chunks)
 697                 goto out;
 698
 699         bitmap = kzalloc(BITS_TO_LONGS(nr_chunks * IRQS_PER_CHUNK) * sizeof (long),
 700                          GFP_ATOMIC);
 701         if (!bitmap)
 702                 goto out;
 703
 704         for (i = 0; i < nr_chunks; i++)
 705                 set_bit(chunk_id + i, lpi_bitmap);
 706
 707         *base = its_chunk_to_lpi(chunk_id);
 708         *nr_ids = nr_chunks * IRQS_PER_CHUNK;
 709
 710 out:
 711         spin_unlock(&lpi_lock);
 712
 713         return bitmap;
 714 }
 715
 716 static void its_lpi_free(unsigned long *bitmap, int base, int nr_ids)
 717 {
 718         int lpi;
 719
 720         spin_lock(&lpi_lock);
 721
 722         for (lpi = base; lpi < (base + nr_ids); lpi += IRQS_PER_CHUNK) {
 723                 int chunk = its_lpi_to_chunk(lpi);
 724                 BUG_ON(chunk > lpi_chunks);
 725                 if (test_bit(chunk, lpi_bitmap)) {
 726                         clear_bit(chunk, lpi_bitmap);
 727                 } else {
 728                         pr_err("Bad LPI chunk %d\n", chunk);
 729                 }
 730         }
 731
 732         spin_unlock(&lpi_lock);
 733
 734         kfree(bitmap);
 735 }
 736
 737 /*
 738  * We allocate 64kB for PROPBASE. That gives us at most 64K LPIs to
 739  * deal with (one configuration byte per interrupt). PENDBASE has to
 740  * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI).
 741  */
 742 #define LPI_PROPBASE_SZ         SZ_64K
 743 #define LPI_PENDBASE_SZ         (LPI_PROPBASE_SZ / 8 + SZ_1K)
 744
 745 /*
 746  * This is how many bits of ID we need, including the useless ones.
 747  */
 748 #define LPI_NRBITS              ilog2(LPI_PROPBASE_SZ + SZ_8K)
 749
 750 #define LPI_PROP_DEFAULT_PRIO   0xa0
 751
 752 static int __init its_alloc_lpi_tables(void)
 753 {
 754         phys_addr_t paddr;
 755
 756         gic_rdists->prop_page = alloc_pages(GFP_NOWAIT,
 757                                            get_order(LPI_PROPBASE_SZ));
 758         if (!gic_rdists->prop_page) {
 759                 pr_err("Failed to allocate PROPBASE\n");
 760                 return -ENOMEM;
 761         }
 762
 763         paddr = page_to_phys(gic_rdists->prop_page);
 764         pr_info("GIC: using LPI property table @%pa\n", &paddr);
 765
 766         /* Priority 0xa0, Group-1, disabled */
 767         memset(page_address(gic_rdists->prop_page),
 768                LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1,
 769                LPI_PROPBASE_SZ);
 770
 771         /* Make sure the GIC will observe the written configuration */
 772         __flush_dcache_area(page_address(gic_rdists->prop_page), LPI_PROPBASE_SZ);
 773
 774         return 0;
 775 }
 776
 777 static const char *its_base_type_string[] = {
 778         [GITS_BASER_TYPE_DEVICE]        = "Devices",
 779         [GITS_BASER_TYPE_VCPU]          = "Virtual CPUs",
 780         [GITS_BASER_TYPE_CPU]           = "Physical CPUs",
 781         [GITS_BASER_TYPE_COLLECTION]    = "Interrupt Collections",
 782         [GITS_BASER_TYPE_RESERVED5]     = "Reserved (5)",
 783         [GITS_BASER_TYPE_RESERVED6]     = "Reserved (6)",
 784         [GITS_BASER_TYPE_RESERVED7]     = "Reserved (7)",
 785 };
 786
 787 static void its_free_tables(struct its_node *its)
 788 {
 789         int i;
 790
 791         for (i = 0; i < GITS_BASER_NR_REGS; i++) {
 792                 if (its->tables[i]) {
 793                         free_page((unsigned long)its->tables[i]);
 794                         its->tables[i] = NULL;
 795                 }
 796         }
 797 }
 798
 799 static int its_alloc_tables(struct its_node *its)
 800 {
 801         int err;
 802         int i;
 803         int psz = SZ_64K;
 804         u64 shr = GITS_BASER_InnerShareable;
 805
 806         for (i = 0; i < GITS_BASER_NR_REGS; i++) {
 807                 u64 val = readq_relaxed(its->base + GITS_BASER + i * 8);
 808                 u64 type = GITS_BASER_TYPE(val);
 809                 u64 entry_size = GITS_BASER_ENTRY_SIZE(val);
 810                 int order = get_order(psz);
 811                 int alloc_size;
 812                 u64 tmp;
 813                 void *base;
 814
 815                 if (type == GITS_BASER_TYPE_NONE)
 816                         continue;
 817
 818                 /*
 819                  * Allocate as many entries as required to fit the
 820                  * range of device IDs that the ITS can grok... The ID
 821                  * space being incredibly sparse, this results in a
 822                  * massive waste of memory.
 823                  *
 824                  * For other tables, only allocate a single page.
 825                  */
 826                 if (type == GITS_BASER_TYPE_DEVICE) {
 827                         u64 typer = readq_relaxed(its->base + GITS_TYPER);
 828                         u32 ids = GITS_TYPER_DEVBITS(typer);
 829
 830                         order = get_order((1UL << ids) * entry_size);
 831                         if (order >= MAX_ORDER) {
 832                                 order = MAX_ORDER - 1;
 833                                 pr_warn("%s: Device Table too large, reduce its page order to %u\n",
 834                                         its->msi_chip.of_node->full_name, order);
 835                         }
 836                 }
 837
 838                 alloc_size = (1 << order) * PAGE_SIZE;
 839                 base = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, order);
 840                 if (!base) {
 841                         err = -ENOMEM;
 842                         goto out_free;
 843                 }
 844
 845                 its->tables[i] = base;
 846
 847 retry_baser:
 848                 val = (virt_to_phys(base)                                |
 849                        (type << GITS_BASER_TYPE_SHIFT)                   |
 850                        ((entry_size - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) |
 851                        GITS_BASER_WaWb                                   |
 852                        shr                                               |
 853                        GITS_BASER_VALID);
 854
 855                 switch (psz) {
 856                 case SZ_4K:
 857                         val |= GITS_BASER_PAGE_SIZE_4K;
 858                         break;
 859                 case SZ_16K:
 860                         val |= GITS_BASER_PAGE_SIZE_16K;
 861                         break;
 862                 case SZ_64K:
 863                         val |= GITS_BASER_PAGE_SIZE_64K;
 864                         break;
 865                 }
 866
 867                 val |= (alloc_size / psz) - 1;
 868
 869                 writeq_relaxed(val, its->base + GITS_BASER + i * 8);
 870                 tmp = readq_relaxed(its->base + GITS_BASER + i * 8);
 871
 872                 if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
 873                         /*
 874                          * Shareability didn't stick. Just use
 875                          * whatever the read reported, which is likely
 876                          * to be the only thing this redistributor
 877                          * supports.
 878                          */
 879                         shr = tmp & GITS_BASER_SHAREABILITY_MASK;
 880                         goto retry_baser;
 881                 }
 882
 883                 if ((val ^ tmp) & GITS_BASER_PAGE_SIZE_MASK) {
 884                         /*
 885                          * Page size didn't stick. Let's try a smaller
 886                          * size and retry. If we reach 4K, then
 887                          * something is horribly wrong...
 888                          */
 889                         switch (psz) {
 890                         case SZ_16K:
 891                                 psz = SZ_4K;
 892                                 goto retry_baser;
 893                         case SZ_64K:
 894                                 psz = SZ_16K;
 895                                 goto retry_baser;
 896                         }
 897                 }
 898
 899                 if (val != tmp) {
 900                         pr_err("ITS: %s: GITS_BASER%d doesn't stick: %lx %lx\n",
 901                                its->msi_chip.of_node->full_name, i,
 902                                (unsigned long) val, (unsigned long) tmp);
 903                         err = -ENXIO;
 904                         goto out_free;
 905                 }
 906
 907                 pr_info("ITS: allocated %d %s @%lx (psz %dK, shr %d)\n",
 908                         (int)(alloc_size / entry_size),
 909                         its_base_type_string[type],
 910                         (unsigned long)virt_to_phys(base),
 911                         psz / SZ_1K, (int)shr >> GITS_BASER_SHAREABILITY_SHIFT);
 912         }
 913
 914         return 0;
 915
 916 out_free:
 917         its_free_tables(its);
 918
 919         return err;
 920 }
 921
 922 static int its_alloc_collections(struct its_node *its)
 923 {
 924         its->collections = kzalloc(nr_cpu_ids * sizeof(*its->collections),
 925                                    GFP_KERNEL);
 926         if (!its->collections)
 927                 return -ENOMEM;
 928
 929         return 0;
 930 }
 931
 932 static void its_cpu_init_lpis(void)
 933 {
 934         void __iomem *rbase = gic_data_rdist_rd_base();
 935         struct page *pend_page;
 936         u64 val, tmp;
 937
 938         /* If we didn't allocate the pending table yet, do it now */
 939         pend_page = gic_data_rdist()->pend_page;
 940         if (!pend_page) {
 941                 phys_addr_t paddr;
 942                 /*
 943                  * The pending pages have to be at least 64kB aligned,
 944                  * hence the 'max(LPI_PENDBASE_SZ, SZ_64K)' below.
 945                  */
 946                 pend_page = alloc_pages(GFP_NOWAIT | __GFP_ZERO,
 947                                         get_order(max(LPI_PENDBASE_SZ, SZ_64K)));
 948                 if (!pend_page) {
 949                         pr_err("Failed to allocate PENDBASE for CPU%d\n",
 950                                smp_processor_id());
 951                         return;
 952                 }
 953
 954                 /* Make sure the GIC will observe the zero-ed page */
 955                 __flush_dcache_area(page_address(pend_page), LPI_PENDBASE_SZ);
 956
 957                 paddr = page_to_phys(pend_page);
 958                 pr_info("CPU%d: using LPI pending table @%pa\n",
 959                         smp_processor_id(), &paddr);
 960                 gic_data_rdist()->pend_page = pend_page;
 961         }
 962
 963         /* Disable LPIs */
 964         val = readl_relaxed(rbase + GICR_CTLR);
 965         val &= ~GICR_CTLR_ENABLE_LPIS;
 966         writel_relaxed(val, rbase + GICR_CTLR);
 967
 968         /*
 969          * Make sure any change to the table is observable by the GIC.
 970          */
 971         dsb(sy);
 972
 973         /* set PROPBASE */
 974         val = (page_to_phys(gic_rdists->prop_page) |
 975                GICR_PROPBASER_InnerShareable |
 976                GICR_PROPBASER_WaWb |
 977                ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK));
 978
 979         writeq_relaxed(val, rbase + GICR_PROPBASER);
 980         tmp = readq_relaxed(rbase + GICR_PROPBASER);
 981
 982         if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
 983                 pr_info_once("GIC: using cache flushing for LPI property table\n");
 984                 gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING;
 985         }
 986
 987         /* set PENDBASE */
 988         val = (page_to_phys(pend_page) |
 989                GICR_PROPBASER_InnerShareable |
 990                GICR_PROPBASER_WaWb);
 991
 992         writeq_relaxed(val, rbase + GICR_PENDBASER);
 993
 994         /* Enable LPIs */
 995         val = readl_relaxed(rbase + GICR_CTLR);
 996         val |= GICR_CTLR_ENABLE_LPIS;
 997         writel_relaxed(val, rbase + GICR_CTLR);
 998
 999         /* Make sure the GIC has seen the above */
1000         dsb(sy);
1001 }
1002
1003 static void its_cpu_init_collection(void)
1004 {
1005         struct its_node *its;
1006         int cpu;
1007
1008         spin_lock(&its_lock);
1009         cpu = smp_processor_id();
1010
1011         list_for_each_entry(its, &its_nodes, entry) {
1012                 u64 target;
1013
1014                 /*
1015                  * We now have to bind each collection to its target
1016                  * redistributor.
1017                  */
1018                 if (readq_relaxed(its->base + GITS_TYPER) & GITS_TYPER_PTA) {
1019                         /*
1020                          * This ITS wants the physical address of the
1021                          * redistributor.
1022                          */
1023                         target = gic_data_rdist()->phys_base;
1024                 } else {
1025                         /*
1026                          * This ITS wants a linear CPU number.
1027                          */
1028                         target = readq_relaxed(gic_data_rdist_rd_base() + GICR_TYPER);
1029                         target = GICR_TYPER_CPU_NUMBER(target);
1030                 }
1031
1032                 /* Perform collection mapping */
1033                 its->collections[cpu].target_address = target;
1034                 its->collections[cpu].col_id = cpu;
1035
1036                 its_send_mapc(its, &its->collections[cpu], 1);
1037                 its_send_invall(its, &its->collections[cpu]);
1038         }
1039
1040         spin_unlock(&its_lock);
1041 }
1042
1043 static struct its_device *its_find_device(struct its_node *its, u32 dev_id)
1044 {
1045         struct its_device *its_dev = NULL, *tmp;
1046         unsigned long flags;
1047
1048         raw_spin_lock_irqsave(&its->lock, flags);
1049
1050         list_for_each_entry(tmp, &its->its_device_list, entry) {
1051                 if (tmp->device_id == dev_id) {
1052                         its_dev = tmp;
1053                         break;
1054                 }
1055         }
1056
1057         raw_spin_unlock_irqrestore(&its->lock, flags);
1058
1059         return its_dev;
1060 }
1061
1062 static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
1063                                             int nvecs)
1064 {
1065         struct its_device *dev;
1066         unsigned long *lpi_map;
1067         unsigned long flags;
1068         void *itt;
1069         int lpi_base;
1070         int nr_lpis;
1071         int nr_ites;
1072         int cpu;
1073         int sz;
1074
1075         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1076         /*
1077          * At least one bit of EventID is being used, hence a minimum
1078          * of two entries. No, the architecture doesn't let you
1079          * express an ITT with a single entry.
1080          */
1081         nr_ites = max(2UL, roundup_pow_of_two(nvecs));
1082         sz = nr_ites * its->ite_size;
1083         sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1;
1084         itt = kzalloc(sz, GFP_KERNEL);
1085         lpi_map = its_lpi_alloc_chunks(nvecs, &lpi_base, &nr_lpis);
1086
1087         if (!dev || !itt || !lpi_map) {
1088                 kfree(dev);
1089                 kfree(itt);
1090                 kfree(lpi_map);
1091                 return NULL;
1092         }
1093
1094         dev->its = its;
1095         dev->itt = itt;
1096         dev->nr_ites = nr_ites;
1097         dev->lpi_map = lpi_map;
1098         dev->lpi_base = lpi_base;
1099         dev->nr_lpis = nr_lpis;
1100         dev->device_id = dev_id;
1101         INIT_LIST_HEAD(&dev->entry);
1102
1103         raw_spin_lock_irqsave(&its->lock, flags);
1104         list_add(&dev->entry, &its->its_device_list);
1105         raw_spin_unlock_irqrestore(&its->lock, flags);
1106
1107         /* Bind the device to the first possible CPU */
1108         cpu = cpumask_first(cpu_online_mask);
1109         dev->collection = &its->collections[cpu];
1110
1111         /* Map device to its ITT */
1112         its_send_mapd(dev, 1);
1113
1114         return dev;
1115 }
1116
1117 static void its_free_device(struct its_device *its_dev)
1118 {
1119         unsigned long flags;
1120
1121         raw_spin_lock_irqsave(&its_dev->its->lock, flags);
1122         list_del(&its_dev->entry);
1123         raw_spin_unlock_irqrestore(&its_dev->its->lock, flags);
1124         kfree(its_dev->itt);
1125         kfree(its_dev);
1126 }
1127
1128 static int its_alloc_device_irq(struct its_device *dev, irq_hw_number_t *hwirq)
1129 {
1130         int idx;
1131
1132         idx = find_first_zero_bit(dev->lpi_map, dev->nr_lpis);
1133         if (idx == dev->nr_lpis)
1134                 return -ENOSPC;
1135
1136         *hwirq = dev->lpi_base + idx;
1137         set_bit(idx, dev->lpi_map);
1138
1139         return 0;
1140 }
1141
1142 struct its_pci_alias {
1143         struct pci_dev  *pdev;
1144         u32             dev_id;
1145         u32             count;
1146 };
1147
1148 static int its_pci_msi_vec_count(struct pci_dev *pdev)
1149 {
1150         int msi, msix;
1151
1152         msi = max(pci_msi_vec_count(pdev), 0);
1153         msix = max(pci_msix_vec_count(pdev), 0);
1154
1155         return max(msi, msix);
1156 }
1157
1158 static int its_get_pci_alias(struct pci_dev *pdev, u16 alias, void *data)
1159 {
1160         struct its_pci_alias *dev_alias = data;
1161
1162         dev_alias->dev_id = alias;
1163         if (pdev != dev_alias->pdev)
1164                 dev_alias->count += its_pci_msi_vec_count(dev_alias->pdev);
1165
1166         return 0;
1167 }
1168
1169 static int its_msi_prepare(struct irq_domain *domain, struct device *dev,
1170                            int nvec, msi_alloc_info_t *info)
1171 {
1172         struct pci_dev *pdev;
1173         struct its_node *its;
1174         struct its_device *its_dev;
1175         struct its_pci_alias dev_alias;
1176
1177         if (!dev_is_pci(dev))
1178                 return -EINVAL;
1179
1180         pdev = to_pci_dev(dev);
1181         dev_alias.pdev = pdev;
1182         dev_alias.count = nvec;
1183
1184         pci_for_each_dma_alias(pdev, its_get_pci_alias, &dev_alias);
1185         its = domain->parent->host_data;
1186
1187         its_dev = its_find_device(its, dev_alias.dev_id);
1188         if (its_dev) {
1189                 /*
1190                  * We already have seen this ID, probably through
1191                  * another alias (PCI bridge of some sort). No need to
1192                  * create the device.
1193                  */
1194                 dev_dbg(dev, "Reusing ITT for devID %x\n", dev_alias.dev_id);
1195                 goto out;
1196         }
1197
1198         its_dev = its_create_device(its, dev_alias.dev_id, dev_alias.count);
1199         if (!its_dev)
1200                 return -ENOMEM;
1201
1202         dev_dbg(&pdev->dev, "ITT %d entries, %d bits\n",
1203                 dev_alias.count, ilog2(dev_alias.count));
1204 out:
1205         info->scratchpad[0].ptr = its_dev;
1206         info->scratchpad[1].ptr = dev;
1207         return 0;
1208 }
1209
1210 static struct msi_domain_ops its_pci_msi_ops = {
1211         .msi_prepare    = its_msi_prepare,
1212 };
1213
1214 static struct msi_domain_info its_pci_msi_domain_info = {
1215         .flags  = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
1216                    MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX),
1217         .ops    = &its_pci_msi_ops,
1218         .chip   = &its_msi_irq_chip,
1219 };
1220
1221 static int its_irq_gic_domain_alloc(struct irq_domain *domain,
1222                                     unsigned int virq,
1223                                     irq_hw_number_t hwirq)
1224 {
1225         struct of_phandle_args args;
1226
1227         args.np = domain->parent->of_node;
1228         args.args_count = 3;
1229         args.args[0] = GIC_IRQ_TYPE_LPI;
1230         args.args[1] = hwirq;
1231         args.args[2] = IRQ_TYPE_EDGE_RISING;
1232
1233         return irq_domain_alloc_irqs_parent(domain, virq, 1, &args);
1234 }
1235
1236 static int its_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
1237                                 unsigned int nr_irqs, void *args)
1238 {
1239         msi_alloc_info_t *info = args;
1240         struct its_device *its_dev = info->scratchpad[0].ptr;
1241         irq_hw_number_t hwirq;
1242         int err;
1243         int i;
1244
1245         for (i = 0; i < nr_irqs; i++) {
1246                 err = its_alloc_device_irq(its_dev, &hwirq);
1247                 if (err)
1248                         return err;
1249
1250                 err = its_irq_gic_domain_alloc(domain, virq + i, hwirq);
1251                 if (err)
1252                         return err;
1253
1254                 irq_domain_set_hwirq_and_chip(domain, virq + i,
1255                                               hwirq, &its_irq_chip, its_dev);
1256                 dev_dbg(info->scratchpad[1].ptr, "ID:%d pID:%d vID:%d\n",
1257                         (int)(hwirq - its_dev->lpi_base), (int)hwirq, virq + i);
1258         }
1259
1260         return 0;
1261 }
1262
1263 static void its_irq_domain_activate(struct irq_domain *domain,
1264                                     struct irq_data *d)
1265 {
1266         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1267         u32 event = its_get_event_id(d);
1268
1269         /* Map the GIC IRQ and event to the device */
1270         its_send_mapvi(its_dev, d->hwirq, event);
1271 }
1272
1273 static void its_irq_domain_deactivate(struct irq_domain *domain,
1274                                       struct irq_data *d)
1275 {
1276         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1277         u32 event = its_get_event_id(d);
1278
1279         /* Stop the delivery of interrupts */
1280         its_send_discard(its_dev, event);
1281 }
1282
1283 static void its_irq_domain_free(struct irq_domain *domain, unsigned int virq,
1284                                 unsigned int nr_irqs)
1285 {
1286         struct irq_data *d = irq_domain_get_irq_data(domain, virq);
1287         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1288         int i;
1289
1290         for (i = 0; i < nr_irqs; i++) {
1291                 struct irq_data *data = irq_domain_get_irq_data(domain,
1292                                                                 virq + i);
1293                 u32 event = its_get_event_id(data);
1294
1295                 /* Mark interrupt index as unused */
1296                 clear_bit(event, its_dev->lpi_map);
1297
1298                 /* Nuke the entry in the domain */
1299                 irq_domain_reset_irq_data(data);
1300         }
1301
1302         /* If all interrupts have been freed, start mopping the floor */
1303         if (bitmap_empty(its_dev->lpi_map, its_dev->nr_lpis)) {
1304                 its_lpi_free(its_dev->lpi_map,
1305                              its_dev->lpi_base,
1306                              its_dev->nr_lpis);
1307
1308                 /* Unmap device/itt */
1309                 its_send_mapd(its_dev, 0);
1310                 its_free_device(its_dev);
1311         }
1312
1313         irq_domain_free_irqs_parent(domain, virq, nr_irqs);
1314 }
1315
1316 static const struct irq_domain_ops its_domain_ops = {
1317         .alloc                  = its_irq_domain_alloc,
1318         .free                   = its_irq_domain_free,
1319         .activate               = its_irq_domain_activate,
1320         .deactivate             = its_irq_domain_deactivate,
1321 };
1322
1323 static int its_force_quiescent(void __iomem *base)
1324 {
1325         u32 count = 1000000;    /* 1s */
1326         u32 val;
1327
1328         val = readl_relaxed(base + GITS_CTLR);
1329         if (val & GITS_CTLR_QUIESCENT)
1330                 return 0;
1331
1332         /* Disable the generation of all interrupts to this ITS */
1333         val &= ~GITS_CTLR_ENABLE;
1334         writel_relaxed(val, base + GITS_CTLR);
1335
1336         /* Poll GITS_CTLR and wait until ITS becomes quiescent */
1337         while (1) {
1338                 val = readl_relaxed(base + GITS_CTLR);
1339                 if (val & GITS_CTLR_QUIESCENT)
1340                         return 0;
1341
1342                 count--;
1343                 if (!count)
1344                         return -EBUSY;
1345
1346                 cpu_relax();
1347                 udelay(1);
1348         }
1349 }
1350
1351 static int its_probe(struct device_node *node, struct irq_domain *parent)
1352 {
1353         struct resource res;
1354         struct its_node *its;
1355         void __iomem *its_base;
1356         u32 val;
1357         u64 baser, tmp;
1358         int err;
1359
1360         err = of_address_to_resource(node, 0, &res);
1361         if (err) {
1362                 pr_warn("%s: no regs?\n", node->full_name);
1363                 return -ENXIO;
1364         }
1365
1366         its_base = ioremap(res.start, resource_size(&res));
1367         if (!its_base) {
1368                 pr_warn("%s: unable to map registers\n", node->full_name);
1369                 return -ENOMEM;
1370         }
1371
1372         val = readl_relaxed(its_base + GITS_PIDR2) & GIC_PIDR2_ARCH_MASK;
1373         if (val != 0x30 && val != 0x40) {
1374                 pr_warn("%s: no ITS detected, giving up\n", node->full_name);
1375                 err = -ENODEV;
1376                 goto out_unmap;
1377         }
1378
1379         err = its_force_quiescent(its_base);
1380         if (err) {
1381                 pr_warn("%s: failed to quiesce, giving up\n",
1382                         node->full_name);
1383                 goto out_unmap;
1384         }
1385
1386         pr_info("ITS: %s\n", node->full_name);
1387
1388         its = kzalloc(sizeof(*its), GFP_KERNEL);
1389         if (!its) {
1390                 err = -ENOMEM;
1391                 goto out_unmap;
1392         }
1393
1394         raw_spin_lock_init(&its->lock);
1395         INIT_LIST_HEAD(&its->entry);
1396         INIT_LIST_HEAD(&its->its_device_list);
1397         its->base = its_base;
1398         its->phys_base = res.start;
1399         its->msi_chip.of_node = node;
1400         its->ite_size = ((readl_relaxed(its_base + GITS_TYPER) >> 4) & 0xf) + 1;
1401
1402         its->cmd_base = kzalloc(ITS_CMD_QUEUE_SZ, GFP_KERNEL);
1403         if (!its->cmd_base) {
1404                 err = -ENOMEM;
1405                 goto out_free_its;
1406         }
1407         its->cmd_write = its->cmd_base;
1408
1409         err = its_alloc_tables(its);
1410         if (err)
1411                 goto out_free_cmd;
1412
1413         err = its_alloc_collections(its);
1414         if (err)
1415                 goto out_free_tables;
1416
1417         baser = (virt_to_phys(its->cmd_base)    |
1418                  GITS_CBASER_WaWb               |
1419                  GITS_CBASER_InnerShareable     |
1420                  (ITS_CMD_QUEUE_SZ / SZ_4K - 1) |
1421                  GITS_CBASER_VALID);
1422
1423         writeq_relaxed(baser, its->base + GITS_CBASER);
1424         tmp = readq_relaxed(its->base + GITS_CBASER);
1425         writeq_relaxed(0, its->base + GITS_CWRITER);
1426         writel_relaxed(GITS_CTLR_ENABLE, its->base + GITS_CTLR);
1427
1428         if ((tmp ^ baser) & GITS_BASER_SHAREABILITY_MASK) {
1429                 pr_info("ITS: using cache flushing for cmd queue\n");
1430                 its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING;
1431         }
1432
1433         if (of_property_read_bool(its->msi_chip.of_node, "msi-controller")) {
1434                 its->domain = irq_domain_add_tree(NULL, &its_domain_ops, its);
1435                 if (!its->domain) {
1436                         err = -ENOMEM;
1437                         goto out_free_tables;
1438                 }
1439
1440                 its->domain->parent = parent;
1441
1442                 its->msi_chip.domain = pci_msi_create_irq_domain(node,
1443                                                                  &its_pci_msi_domain_info,
1444                                                                  its->domain);
1445                 if (!its->msi_chip.domain) {
1446                         err = -ENOMEM;
1447                         goto out_free_domains;
1448                 }
1449
1450                 err = of_pci_msi_chip_add(&its->msi_chip);
1451                 if (err)
1452                         goto out_free_domains;
1453         }
1454
1455         spin_lock(&its_lock);
1456         list_add(&its->entry, &its_nodes);
1457         spin_unlock(&its_lock);
1458
1459         return 0;
1460
1461 out_free_domains:
1462         if (its->msi_chip.domain)
1463                 irq_domain_remove(its->msi_chip.domain);
1464         if (its->domain)
1465                 irq_domain_remove(its->domain);
1466 out_free_tables:
1467         its_free_tables(its);
1468 out_free_cmd:
1469         kfree(its->cmd_base);
1470 out_free_its:
1471         kfree(its);
1472 out_unmap:
1473         iounmap(its_base);
1474         pr_err("ITS: failed probing %s (%d)\n", node->full_name, err);
1475         return err;
1476 }
1477
1478 static bool gic_rdists_supports_plpis(void)
1479 {
1480         return !!(readl_relaxed(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS);
1481 }
1482
1483 int its_cpu_init(void)
1484 {
1485         if (!list_empty(&its_nodes)) {
1486                 if (!gic_rdists_supports_plpis()) {
1487                         pr_info("CPU%d: LPIs not supported\n", smp_processor_id());
1488                         return -ENXIO;
1489                 }
1490                 its_cpu_init_lpis();
1491                 its_cpu_init_collection();
1492         }
1493
1494         return 0;
1495 }
1496
1497 static struct of_device_id its_device_id[] = {
1498         {       .compatible     = "arm,gic-v3-its",     },
1499         {},
1500 };
1501
1502 int its_init(struct device_node *node, struct rdists *rdists,
1503              struct irq_domain *parent_domain)
1504 {
1505         struct device_node *np;
1506
1507         for (np = of_find_matching_node(node, its_device_id); np;
1508              np = of_find_matching_node(np, its_device_id)) {
1509                 its_probe(np, parent_domain);
1510         }
1511
1512         if (list_empty(&its_nodes)) {
1513                 pr_warn("ITS: No ITS available, not enabling LPIs\n");
1514                 return -ENXIO;
1515         }
1516
1517         gic_rdists = rdists;
1518         gic_root_node = node;
1519
1520         its_alloc_lpi_tables();
1521         its_lpi_init(rdists->id_bits);
1522
1523         return 0;
1524 }