2 * ARM GIC v2m MSI(-X) support
3 * Support for Message Signaled Interrupts for systems that
4 * implement ARM Generic Interrupt Controller: GICv2m.
6 * Copyright (C) 2014 Advanced Micro Devices, Inc.
7 * Authors: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
8 * Harish Kasiviswanathan <harish.kasiviswanathan@amd.com>
9 * Brandon Anderson <brandon.anderson@amd.com>
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
16 #define pr_fmt(fmt) "GICv2m: " fmt
18 #include <linux/irq.h>
19 #include <linux/irqdomain.h>
20 #include <linux/kernel.h>
21 #include <linux/of_address.h>
22 #include <linux/of_pci.h>
23 #include <linux/slab.h>
24 #include <linux/spinlock.h>
29 * [25:16] lowest SPI assigned to MSI
31 * [9:0] Numer of SPIs assigned to MSI
33 #define V2M_MSI_TYPER 0x008
34 #define V2M_MSI_TYPER_BASE_SHIFT 16
35 #define V2M_MSI_TYPER_BASE_MASK 0x3FF
36 #define V2M_MSI_TYPER_NUM_MASK 0x3FF
37 #define V2M_MSI_SETSPI_NS 0x040
38 #define V2M_MIN_SPI 32
39 #define V2M_MAX_SPI 1019
40 #define V2M_MSI_IIDR 0xFCC
42 #define V2M_MSI_TYPER_BASE_SPI(x) \
43 (((x) >> V2M_MSI_TYPER_BASE_SHIFT) & V2M_MSI_TYPER_BASE_MASK)
45 #define V2M_MSI_TYPER_NUM_SPI(x) ((x) & V2M_MSI_TYPER_NUM_MASK)
47 /* APM X-Gene with GICv2m MSI_IIDR register value */
48 #define XGENE_GICV2M_MSI_IIDR 0x06000170
50 /* List of flags for specific v2m implementation */
51 #define GICV2M_NEEDS_SPI_OFFSET 0x00000001
53 static LIST_HEAD(v2m_nodes);
54 static DEFINE_SPINLOCK(v2m_lock);
57 struct list_head entry;
58 struct fwnode_handle *fwnode;
59 struct resource res; /* GICv2m resource */
60 void __iomem *base; /* GICv2m virt address */
61 u32 spi_start; /* The SPI number that MSIs start */
62 u32 nr_spis; /* The number of SPIs for MSIs */
63 unsigned long *bm; /* MSI vector bitmap */
64 u32 flags; /* v2m flags for specific implementation */
67 static void gicv2m_mask_msi_irq(struct irq_data *d)
70 irq_chip_mask_parent(d);
73 static void gicv2m_unmask_msi_irq(struct irq_data *d)
75 pci_msi_unmask_irq(d);
76 irq_chip_unmask_parent(d);
79 static struct irq_chip gicv2m_msi_irq_chip = {
81 .irq_mask = gicv2m_mask_msi_irq,
82 .irq_unmask = gicv2m_unmask_msi_irq,
83 .irq_eoi = irq_chip_eoi_parent,
84 .irq_write_msi_msg = pci_msi_domain_write_msg,
87 static struct msi_domain_info gicv2m_msi_domain_info = {
88 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
90 .chip = &gicv2m_msi_irq_chip,
93 static int gicv2m_set_affinity(struct irq_data *irq_data,
94 const struct cpumask *mask, bool force)
98 ret = irq_chip_set_affinity_parent(irq_data, mask, force);
99 if (ret == IRQ_SET_MASK_OK)
100 ret = IRQ_SET_MASK_OK_DONE;
105 static void gicv2m_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
107 struct v2m_data *v2m = irq_data_get_irq_chip_data(data);
108 phys_addr_t addr = v2m->res.start + V2M_MSI_SETSPI_NS;
110 msg->address_hi = upper_32_bits(addr);
111 msg->address_lo = lower_32_bits(addr);
112 msg->data = data->hwirq;
114 if (v2m->flags & GICV2M_NEEDS_SPI_OFFSET)
115 msg->data -= v2m->spi_start;
118 static struct irq_chip gicv2m_irq_chip = {
120 .irq_mask = irq_chip_mask_parent,
121 .irq_unmask = irq_chip_unmask_parent,
122 .irq_eoi = irq_chip_eoi_parent,
123 .irq_set_affinity = gicv2m_set_affinity,
124 .irq_compose_msi_msg = gicv2m_compose_msi_msg,
127 static int gicv2m_irq_gic_domain_alloc(struct irq_domain *domain,
129 irq_hw_number_t hwirq)
131 struct irq_fwspec fwspec;
135 if (is_of_node(domain->parent->fwnode)) {
136 fwspec.fwnode = domain->parent->fwnode;
137 fwspec.param_count = 3;
139 fwspec.param[1] = hwirq - 32;
140 fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
145 err = irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
149 /* Configure the interrupt line to be edge */
150 d = irq_domain_get_irq_data(domain->parent, virq);
151 d->chip->irq_set_type(d, IRQ_TYPE_EDGE_RISING);
155 static void gicv2m_unalloc_msi(struct v2m_data *v2m, unsigned int hwirq)
159 pos = hwirq - v2m->spi_start;
160 if (pos < 0 || pos >= v2m->nr_spis) {
161 pr_err("Failed to teardown msi. Invalid hwirq %d\n", hwirq);
165 spin_lock(&v2m_lock);
166 __clear_bit(pos, v2m->bm);
167 spin_unlock(&v2m_lock);
170 static int gicv2m_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
171 unsigned int nr_irqs, void *args)
173 struct v2m_data *v2m = NULL, *tmp;
174 int hwirq, offset, err = 0;
176 spin_lock(&v2m_lock);
177 list_for_each_entry(tmp, &v2m_nodes, entry) {
178 offset = find_first_zero_bit(tmp->bm, tmp->nr_spis);
179 if (offset < tmp->nr_spis) {
180 __set_bit(offset, tmp->bm);
185 spin_unlock(&v2m_lock);
190 hwirq = v2m->spi_start + offset;
192 err = gicv2m_irq_gic_domain_alloc(domain, virq, hwirq);
194 gicv2m_unalloc_msi(v2m, hwirq);
198 irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
199 &gicv2m_irq_chip, v2m);
204 static void gicv2m_irq_domain_free(struct irq_domain *domain,
205 unsigned int virq, unsigned int nr_irqs)
207 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
208 struct v2m_data *v2m = irq_data_get_irq_chip_data(d);
210 BUG_ON(nr_irqs != 1);
211 gicv2m_unalloc_msi(v2m, d->hwirq);
212 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
215 static const struct irq_domain_ops gicv2m_domain_ops = {
216 .alloc = gicv2m_irq_domain_alloc,
217 .free = gicv2m_irq_domain_free,
220 static bool is_msi_spi_valid(u32 base, u32 num)
222 if (base < V2M_MIN_SPI) {
223 pr_err("Invalid MSI base SPI (base:%u)\n", base);
227 if ((num == 0) || (base + num > V2M_MAX_SPI)) {
228 pr_err("Number of SPIs (%u) exceed maximum (%u)\n",
229 num, V2M_MAX_SPI - V2M_MIN_SPI + 1);
236 static struct irq_chip gicv2m_pmsi_irq_chip = {
240 static struct msi_domain_ops gicv2m_pmsi_ops = {
243 static struct msi_domain_info gicv2m_pmsi_domain_info = {
244 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS),
245 .ops = &gicv2m_pmsi_ops,
246 .chip = &gicv2m_pmsi_irq_chip,
249 static void gicv2m_teardown(void)
251 struct v2m_data *v2m, *tmp;
253 list_for_each_entry_safe(v2m, tmp, &v2m_nodes, entry) {
254 list_del(&v2m->entry);
257 of_node_put(to_of_node(v2m->fwnode));
262 static int gicv2m_allocate_domains(struct irq_domain *parent)
264 struct irq_domain *inner_domain, *pci_domain, *plat_domain;
265 struct v2m_data *v2m;
267 v2m = list_first_entry_or_null(&v2m_nodes, struct v2m_data, entry);
271 inner_domain = irq_domain_create_tree(v2m->fwnode,
272 &gicv2m_domain_ops, v2m);
274 pr_err("Failed to create GICv2m domain\n");
278 inner_domain->bus_token = DOMAIN_BUS_NEXUS;
279 inner_domain->parent = parent;
280 pci_domain = pci_msi_create_irq_domain(v2m->fwnode,
281 &gicv2m_msi_domain_info,
283 plat_domain = platform_msi_create_irq_domain(v2m->fwnode,
284 &gicv2m_pmsi_domain_info,
286 if (!pci_domain || !plat_domain) {
287 pr_err("Failed to create MSI domains\n");
289 irq_domain_remove(plat_domain);
291 irq_domain_remove(pci_domain);
292 irq_domain_remove(inner_domain);
299 static int __init gicv2m_init_one(struct fwnode_handle *fwnode,
300 u32 spi_start, u32 nr_spis,
301 struct resource *res)
304 struct v2m_data *v2m;
306 v2m = kzalloc(sizeof(struct v2m_data), GFP_KERNEL);
308 pr_err("Failed to allocate struct v2m_data.\n");
312 INIT_LIST_HEAD(&v2m->entry);
313 v2m->fwnode = fwnode;
315 memcpy(&v2m->res, res, sizeof(struct resource));
317 v2m->base = ioremap(v2m->res.start, resource_size(&v2m->res));
319 pr_err("Failed to map GICv2m resource\n");
324 if (spi_start && nr_spis) {
325 v2m->spi_start = spi_start;
326 v2m->nr_spis = nr_spis;
328 u32 typer = readl_relaxed(v2m->base + V2M_MSI_TYPER);
330 v2m->spi_start = V2M_MSI_TYPER_BASE_SPI(typer);
331 v2m->nr_spis = V2M_MSI_TYPER_NUM_SPI(typer);
334 if (!is_msi_spi_valid(v2m->spi_start, v2m->nr_spis)) {
340 * APM X-Gene GICv2m implementation has an erratum where
341 * the MSI data needs to be the offset from the spi_start
342 * in order to trigger the correct MSI interrupt. This is
343 * different from the standard GICv2m implementation where
344 * the MSI data is the absolute value within the range from
345 * spi_start to (spi_start + num_spis).
347 if (readl_relaxed(v2m->base + V2M_MSI_IIDR) == XGENE_GICV2M_MSI_IIDR)
348 v2m->flags |= GICV2M_NEEDS_SPI_OFFSET;
350 v2m->bm = kzalloc(sizeof(long) * BITS_TO_LONGS(v2m->nr_spis),
357 list_add_tail(&v2m->entry, &v2m_nodes);
359 pr_info("range[%#lx:%#lx], SPI[%d:%d]\n",
360 (unsigned long)res->start, (unsigned long)res->end,
361 v2m->spi_start, (v2m->spi_start + v2m->nr_spis));
371 static struct of_device_id gicv2m_device_id[] = {
372 { .compatible = "arm,gic-v2m-frame", },
376 int __init gicv2m_of_init(struct device_node *node, struct irq_domain *parent)
379 struct device_node *child;
381 for (child = of_find_matching_node(node, gicv2m_device_id); child;
382 child = of_find_matching_node(child, gicv2m_device_id)) {
383 u32 spi_start = 0, nr_spis = 0;
386 if (!of_find_property(child, "msi-controller", NULL))
389 ret = of_address_to_resource(child, 0, &res);
391 pr_err("Failed to allocate v2m resource.\n");
395 if (!of_property_read_u32(child, "arm,msi-base-spi",
397 !of_property_read_u32(child, "arm,msi-num-spis", &nr_spis))
398 pr_info("DT overriding V2M MSI_TYPER (base:%u, num:%u)\n",
401 ret = gicv2m_init_one(&child->fwnode, spi_start, nr_spis, &res);
409 ret = gicv2m_allocate_domains(parent);