drivers/gpu/drm/radeon/radeon_uvd.c

   1 /*
   2  * Copyright 2011 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Christian König <deathsimple@vodafone.de>
  29  */
  30
  31 #include <linux/firmware.h>
  32 #include <linux/module.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm.h>
  35
  36 #include "radeon.h"
  37 #include "r600d.h"
  38
  39 /* 1 second timeout */
  40 #define UVD_IDLE_TIMEOUT_MS     1000
  41
  42 /* Firmware Names */
  43 #define FIRMWARE_RV710          "radeon/RV710_uvd.bin"
  44 #define FIRMWARE_CYPRESS        "radeon/CYPRESS_uvd.bin"
  45 #define FIRMWARE_SUMO           "radeon/SUMO_uvd.bin"
  46 #define FIRMWARE_TAHITI         "radeon/TAHITI_uvd.bin"
  47 #define FIRMWARE_BONAIRE        "radeon/BONAIRE_uvd.bin"
  48
  49 MODULE_FIRMWARE(FIRMWARE_RV710);
  50 MODULE_FIRMWARE(FIRMWARE_CYPRESS);
  51 MODULE_FIRMWARE(FIRMWARE_SUMO);
  52 MODULE_FIRMWARE(FIRMWARE_TAHITI);
  53 MODULE_FIRMWARE(FIRMWARE_BONAIRE);
  54
  55 static void radeon_uvd_idle_work_handler(struct work_struct *work);
  56
  57 int radeon_uvd_init(struct radeon_device *rdev)
  58 {
  59         unsigned long bo_size;
  60         const char *fw_name;
  61         int i, r;
  62
  63         INIT_DELAYED_WORK(&rdev->uvd.idle_work, radeon_uvd_idle_work_handler);
  64
  65         switch (rdev->family) {
  66         case CHIP_RV710:
  67         case CHIP_RV730:
  68         case CHIP_RV740:
  69                 fw_name = FIRMWARE_RV710;
  70                 break;
  71
  72         case CHIP_CYPRESS:
  73         case CHIP_HEMLOCK:
  74         case CHIP_JUNIPER:
  75         case CHIP_REDWOOD:
  76         case CHIP_CEDAR:
  77                 fw_name = FIRMWARE_CYPRESS;
  78                 break;
  79
  80         case CHIP_SUMO:
  81         case CHIP_SUMO2:
  82         case CHIP_PALM:
  83         case CHIP_CAYMAN:
  84         case CHIP_BARTS:
  85         case CHIP_TURKS:
  86         case CHIP_CAICOS:
  87                 fw_name = FIRMWARE_SUMO;
  88                 break;
  89
  90         case CHIP_TAHITI:
  91         case CHIP_VERDE:
  92         case CHIP_PITCAIRN:
  93         case CHIP_ARUBA:
  94                 fw_name = FIRMWARE_TAHITI;
  95                 break;
  96
  97         case CHIP_BONAIRE:
  98         case CHIP_KABINI:
  99         case CHIP_KAVERI:
 100         case CHIP_HAWAII:
 101                 fw_name = FIRMWARE_BONAIRE;
 102                 break;
 103
 104         default:
 105                 return -EINVAL;
 106         }
 107
 108         r = request_firmware(&rdev->uvd_fw, fw_name, rdev->dev);
 109         if (r) {
 110                 dev_err(rdev->dev, "radeon_uvd: Can't load firmware \"%s\"\n",
 111                         fw_name);
 112                 return r;
 113         }
 114
 115         bo_size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 8) +
 116                   RADEON_UVD_STACK_SIZE + RADEON_UVD_HEAP_SIZE;
 117         r = radeon_bo_create(rdev, bo_size, PAGE_SIZE, true,
 118                              RADEON_GEM_DOMAIN_VRAM, NULL, &rdev->uvd.vcpu_bo);
 119         if (r) {
 120                 dev_err(rdev->dev, "(%d) failed to allocate UVD bo\n", r);
 121                 return r;
 122         }
 123
 124         r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false);
 125         if (r) {
 126                 radeon_bo_unref(&rdev->uvd.vcpu_bo);
 127                 dev_err(rdev->dev, "(%d) failed to reserve UVD bo\n", r);
 128                 return r;
 129         }
 130
 131         r = radeon_bo_pin(rdev->uvd.vcpu_bo, RADEON_GEM_DOMAIN_VRAM,
 132                           &rdev->uvd.gpu_addr);
 133         if (r) {
 134                 radeon_bo_unreserve(rdev->uvd.vcpu_bo);
 135                 radeon_bo_unref(&rdev->uvd.vcpu_bo);
 136                 dev_err(rdev->dev, "(%d) UVD bo pin failed\n", r);
 137                 return r;
 138         }
 139
 140         r = radeon_bo_kmap(rdev->uvd.vcpu_bo, &rdev->uvd.cpu_addr);
 141         if (r) {
 142                 dev_err(rdev->dev, "(%d) UVD map failed\n", r);
 143                 return r;
 144         }
 145
 146         radeon_bo_unreserve(rdev->uvd.vcpu_bo);
 147
 148         for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
 149                 atomic_set(&rdev->uvd.handles[i], 0);
 150                 rdev->uvd.filp[i] = NULL;
 151                 rdev->uvd.img_size[i] = 0;
 152         }
 153
 154         return 0;
 155 }
 156
 157 void radeon_uvd_fini(struct radeon_device *rdev)
 158 {
 159         int r;
 160
 161         if (rdev->uvd.vcpu_bo == NULL)
 162                 return;
 163
 164         r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false);
 165         if (!r) {
 166                 radeon_bo_kunmap(rdev->uvd.vcpu_bo);
 167                 radeon_bo_unpin(rdev->uvd.vcpu_bo);
 168                 radeon_bo_unreserve(rdev->uvd.vcpu_bo);
 169         }
 170
 171         radeon_bo_unref(&rdev->uvd.vcpu_bo);
 172
 173         release_firmware(rdev->uvd_fw);
 174 }
 175
 176 int radeon_uvd_suspend(struct radeon_device *rdev)
 177 {
 178         unsigned size;
 179         void *ptr;
 180         int i;
 181
 182         if (rdev->uvd.vcpu_bo == NULL)
 183                 return 0;
 184
 185         for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i)
 186                 if (atomic_read(&rdev->uvd.handles[i]))
 187                         break;
 188
 189         if (i == RADEON_MAX_UVD_HANDLES)
 190                 return 0;
 191
 192         size = radeon_bo_size(rdev->uvd.vcpu_bo);
 193         size -= rdev->uvd_fw->size;
 194
 195         ptr = rdev->uvd.cpu_addr;
 196         ptr += rdev->uvd_fw->size;
 197
 198         rdev->uvd.saved_bo = kmalloc(size, GFP_KERNEL);
 199         memcpy(rdev->uvd.saved_bo, ptr, size);
 200
 201         return 0;
 202 }
 203
 204 int radeon_uvd_resume(struct radeon_device *rdev)
 205 {
 206         unsigned size;
 207         void *ptr;
 208
 209         if (rdev->uvd.vcpu_bo == NULL)
 210                 return -EINVAL;
 211
 212         memcpy(rdev->uvd.cpu_addr, rdev->uvd_fw->data, rdev->uvd_fw->size);
 213
 214         size = radeon_bo_size(rdev->uvd.vcpu_bo);
 215         size -= rdev->uvd_fw->size;
 216
 217         ptr = rdev->uvd.cpu_addr;
 218         ptr += rdev->uvd_fw->size;
 219
 220         if (rdev->uvd.saved_bo != NULL) {
 221                 memcpy(ptr, rdev->uvd.saved_bo, size);
 222                 kfree(rdev->uvd.saved_bo);
 223                 rdev->uvd.saved_bo = NULL;
 224         } else
 225                 memset(ptr, 0, size);
 226
 227         return 0;
 228 }
 229
 230 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo)
 231 {
 232         rbo->placement.fpfn = 0 >> PAGE_SHIFT;
 233         rbo->placement.lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT;
 234 }
 235
 236 void radeon_uvd_free_handles(struct radeon_device *rdev, struct drm_file *filp)
 237 {
 238         int i, r;
 239         for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
 240                 uint32_t handle = atomic_read(&rdev->uvd.handles[i]);
 241                 if (handle != 0 && rdev->uvd.filp[i] == filp) {
 242                         struct radeon_fence *fence;
 243
 244                         radeon_uvd_note_usage(rdev);
 245
 246                         r = radeon_uvd_get_destroy_msg(rdev,
 247                                 R600_RING_TYPE_UVD_INDEX, handle, &fence);
 248                         if (r) {
 249                                 DRM_ERROR("Error destroying UVD (%d)!\n", r);
 250                                 continue;
 251                         }
 252
 253                         radeon_fence_wait(fence, false);
 254                         radeon_fence_unref(&fence);
 255
 256                         rdev->uvd.filp[i] = NULL;
 257                         atomic_set(&rdev->uvd.handles[i], 0);
 258                 }
 259         }
 260 }
 261
 262 static int radeon_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[])
 263 {
 264         unsigned stream_type = msg[4];
 265         unsigned width = msg[6];
 266         unsigned height = msg[7];
 267         unsigned dpb_size = msg[9];
 268         unsigned pitch = msg[28];
 269
 270         unsigned width_in_mb = width / 16;
 271         unsigned height_in_mb = ALIGN(height / 16, 2);
 272
 273         unsigned image_size, tmp, min_dpb_size;
 274
 275         image_size = width * height;
 276         image_size += image_size / 2;
 277         image_size = ALIGN(image_size, 1024);
 278
 279         switch (stream_type) {
 280         case 0: /* H264 */
 281
 282                 /* reference picture buffer */
 283                 min_dpb_size = image_size * 17;
 284
 285                 /* macroblock context buffer */
 286                 min_dpb_size += width_in_mb * height_in_mb * 17 * 192;
 287
 288                 /* IT surface buffer */
 289                 min_dpb_size += width_in_mb * height_in_mb * 32;
 290                 break;
 291
 292         case 1: /* VC1 */
 293
 294                 /* reference picture buffer */
 295                 min_dpb_size = image_size * 3;
 296
 297                 /* CONTEXT_BUFFER */
 298                 min_dpb_size += width_in_mb * height_in_mb * 128;
 299
 300                 /* IT surface buffer */
 301                 min_dpb_size += width_in_mb * 64;
 302
 303                 /* DB surface buffer */
 304                 min_dpb_size += width_in_mb * 128;
 305
 306                 /* BP */
 307                 tmp = max(width_in_mb, height_in_mb);
 308                 min_dpb_size += ALIGN(tmp * 7 * 16, 64);
 309                 break;
 310
 311         case 3: /* MPEG2 */
 312
 313                 /* reference picture buffer */
 314                 min_dpb_size = image_size * 3;
 315                 break;
 316
 317         case 4: /* MPEG4 */
 318
 319                 /* reference picture buffer */
 320                 min_dpb_size = image_size * 3;
 321
 322                 /* CM */
 323                 min_dpb_size += width_in_mb * height_in_mb * 64;
 324
 325                 /* IT surface buffer */
 326                 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64);
 327                 break;
 328
 329         default:
 330                 DRM_ERROR("UVD codec not handled %d!\n", stream_type);
 331                 return -EINVAL;
 332         }
 333
 334         if (width > pitch) {
 335                 DRM_ERROR("Invalid UVD decoding target pitch!\n");
 336                 return -EINVAL;
 337         }
 338
 339         if (dpb_size < min_dpb_size) {
 340                 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n",
 341                           dpb_size, min_dpb_size);
 342                 return -EINVAL;
 343         }
 344
 345         buf_sizes[0x1] = dpb_size;
 346         buf_sizes[0x2] = image_size;
 347         return 0;
 348 }
 349
 350 static int radeon_uvd_cs_msg(struct radeon_cs_parser *p, struct radeon_bo *bo,
 351                              unsigned offset, unsigned buf_sizes[])
 352 {
 353         int32_t *msg, msg_type, handle;
 354         unsigned img_size = 0;
 355         void *ptr;
 356
 357         int i, r;
 358
 359         if (offset & 0x3F) {
 360                 DRM_ERROR("UVD messages must be 64 byte aligned!\n");
 361                 return -EINVAL;
 362         }
 363
 364         if (bo->tbo.sync_obj) {
 365                 r = radeon_fence_wait(bo->tbo.sync_obj, false);
 366                 if (r) {
 367                         DRM_ERROR("Failed waiting for UVD message (%d)!\n", r);
 368                         return r;
 369                 }
 370         }
 371
 372         r = radeon_bo_kmap(bo, &ptr);
 373         if (r) {
 374                 DRM_ERROR("Failed mapping the UVD message (%d)!\n", r);
 375                 return r;
 376         }
 377
 378         msg = ptr + offset;
 379
 380         msg_type = msg[1];
 381         handle = msg[2];
 382
 383         if (handle == 0) {
 384                 DRM_ERROR("Invalid UVD handle!\n");
 385                 return -EINVAL;
 386         }
 387
 388         if (msg_type == 1) {
 389                 /* it's a decode msg, calc buffer sizes */
 390                 r = radeon_uvd_cs_msg_decode(msg, buf_sizes);
 391                 /* calc image size (width * height) */
 392                 img_size = msg[6] * msg[7];
 393                 radeon_bo_kunmap(bo);
 394                 if (r)
 395                         return r;
 396
 397         } else if (msg_type == 2) {
 398                 /* it's a destroy msg, free the handle */
 399                 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i)
 400                         atomic_cmpxchg(&p->rdev->uvd.handles[i], handle, 0);
 401                 radeon_bo_kunmap(bo);
 402                 return 0;
 403         } else {
 404                 /* it's a create msg, calc image size (width * height) */
 405                 img_size = msg[7] * msg[8];
 406                 radeon_bo_kunmap(bo);
 407
 408                 if (msg_type != 0) {
 409                         DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type);
 410                         return -EINVAL;
 411                 }
 412
 413                 /* it's a create msg, no special handling needed */
 414         }
 415
 416         /* create or decode, validate the handle */
 417         for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
 418                 if (atomic_read(&p->rdev->uvd.handles[i]) == handle)
 419                         return 0;
 420         }
 421
 422         /* handle not found try to alloc a new one */
 423         for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
 424                 if (!atomic_cmpxchg(&p->rdev->uvd.handles[i], 0, handle)) {
 425                         p->rdev->uvd.filp[i] = p->filp;
 426                         p->rdev->uvd.img_size[i] = img_size;
 427                         return 0;
 428                 }
 429         }
 430
 431         DRM_ERROR("No more free UVD handles!\n");
 432         return -EINVAL;
 433 }
 434
 435 static int radeon_uvd_cs_reloc(struct radeon_cs_parser *p,
 436                                int data0, int data1,
 437                                unsigned buf_sizes[], bool *has_msg_cmd)
 438 {
 439         struct radeon_cs_chunk *relocs_chunk;
 440         struct radeon_cs_reloc *reloc;
 441         unsigned idx, cmd, offset;
 442         uint64_t start, end;
 443         int r;
 444
 445         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
 446         offset = radeon_get_ib_value(p, data0);
 447         idx = radeon_get_ib_value(p, data1);
 448         if (idx >= relocs_chunk->length_dw) {
 449                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
 450                           idx, relocs_chunk->length_dw);
 451                 return -EINVAL;
 452         }
 453
 454         reloc = p->relocs_ptr[(idx / 4)];
 455         start = reloc->lobj.gpu_offset;
 456         end = start + radeon_bo_size(reloc->robj);
 457         start += offset;
 458
 459         p->ib.ptr[data0] = start & 0xFFFFFFFF;
 460         p->ib.ptr[data1] = start >> 32;
 461
 462         cmd = radeon_get_ib_value(p, p->idx) >> 1;
 463
 464         if (cmd < 0x4) {
 465                 if ((end - start) < buf_sizes[cmd]) {
 466                         DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
 467                                   (unsigned)(end - start), buf_sizes[cmd]);
 468                         return -EINVAL;
 469                 }
 470
 471         } else if (cmd != 0x100) {
 472                 DRM_ERROR("invalid UVD command %X!\n", cmd);
 473                 return -EINVAL;
 474         }
 475
 476         if ((start >> 28) != ((end - 1) >> 28)) {
 477                 DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n",
 478                           start, end);
 479                 return -EINVAL;
 480         }
 481
 482         /* TODO: is this still necessary on NI+ ? */
 483         if ((cmd == 0 || cmd == 0x3) &&
 484             (start >> 28) != (p->rdev->uvd.gpu_addr >> 28)) {
 485                 DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
 486                           start, end);
 487                 return -EINVAL;
 488         }
 489
 490         if (cmd == 0) {
 491                 if (*has_msg_cmd) {
 492                         DRM_ERROR("More than one message in a UVD-IB!\n");
 493                         return -EINVAL;
 494                 }
 495                 *has_msg_cmd = true;
 496                 r = radeon_uvd_cs_msg(p, reloc->robj, offset, buf_sizes);
 497                 if (r)
 498                         return r;
 499         } else if (!*has_msg_cmd) {
 500                 DRM_ERROR("Message needed before other commands are send!\n");
 501                 return -EINVAL;
 502         }
 503
 504         return 0;
 505 }
 506
 507 static int radeon_uvd_cs_reg(struct radeon_cs_parser *p,
 508                              struct radeon_cs_packet *pkt,
 509                              int *data0, int *data1,
 510                              unsigned buf_sizes[],
 511                              bool *has_msg_cmd)
 512 {
 513         int i, r;
 514
 515         p->idx++;
 516         for (i = 0; i <= pkt->count; ++i) {
 517                 switch (pkt->reg + i*4) {
 518                 case UVD_GPCOM_VCPU_DATA0:
 519                         *data0 = p->idx;
 520                         break;
 521                 case UVD_GPCOM_VCPU_DATA1:
 522                         *data1 = p->idx;
 523                         break;
 524                 case UVD_GPCOM_VCPU_CMD:
 525                         r = radeon_uvd_cs_reloc(p, *data0, *data1,
 526                                                 buf_sizes, has_msg_cmd);
 527                         if (r)
 528                                 return r;
 529                         break;
 530                 case UVD_ENGINE_CNTL:
 531                         break;
 532                 default:
 533                         DRM_ERROR("Invalid reg 0x%X!\n",
 534                                   pkt->reg + i*4);
 535                         return -EINVAL;
 536                 }
 537                 p->idx++;
 538         }
 539         return 0;
 540 }
 541
 542 int radeon_uvd_cs_parse(struct radeon_cs_parser *p)
 543 {
 544         struct radeon_cs_packet pkt;
 545         int r, data0 = 0, data1 = 0;
 546
 547         /* does the IB has a msg command */
 548         bool has_msg_cmd = false;
 549
 550         /* minimum buffer sizes */
 551         unsigned buf_sizes[] = {
 552                 [0x00000000]    =       2048,
 553                 [0x00000001]    =       32 * 1024 * 1024,
 554                 [0x00000002]    =       2048 * 1152 * 3,
 555                 [0x00000003]    =       2048,
 556         };
 557
 558         if (p->chunks[p->chunk_ib_idx].length_dw % 16) {
 559                 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n",
 560                           p->chunks[p->chunk_ib_idx].length_dw);
 561                 return -EINVAL;
 562         }
 563
 564         if (p->chunk_relocs_idx == -1) {
 565                 DRM_ERROR("No relocation chunk !\n");
 566                 return -EINVAL;
 567         }
 568
 569
 570         do {
 571                 r = radeon_cs_packet_parse(p, &pkt, p->idx);
 572                 if (r)
 573                         return r;
 574                 switch (pkt.type) {
 575                 case RADEON_PACKET_TYPE0:
 576                         r = radeon_uvd_cs_reg(p, &pkt, &data0, &data1,
 577                                               buf_sizes, &has_msg_cmd);
 578                         if (r)
 579                                 return r;
 580                         break;
 581                 case RADEON_PACKET_TYPE2:
 582                         p->idx += pkt.count + 2;
 583                         break;
 584                 default:
 585                         DRM_ERROR("Unknown packet type %d !\n", pkt.type);
 586                         return -EINVAL;
 587                 }
 588         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
 589
 590         if (!has_msg_cmd) {
 591                 DRM_ERROR("UVD-IBs need a msg command!\n");
 592                 return -EINVAL;
 593         }
 594
 595         return 0;
 596 }
 597
 598 static int radeon_uvd_send_msg(struct radeon_device *rdev,
 599                                int ring, struct radeon_bo *bo,
 600                                struct radeon_fence **fence)
 601 {
 602         struct ttm_validate_buffer tv;
 603         struct ww_acquire_ctx ticket;
 604         struct list_head head;
 605         struct radeon_ib ib;
 606         uint64_t addr;
 607         int i, r;
 608
 609         memset(&tv, 0, sizeof(tv));
 610         tv.bo = &bo->tbo;
 611
 612         INIT_LIST_HEAD(&head);
 613         list_add(&tv.head, &head);
 614
 615         r = ttm_eu_reserve_buffers(&ticket, &head);
 616         if (r)
 617                 return r;
 618
 619         radeon_ttm_placement_from_domain(bo, RADEON_GEM_DOMAIN_VRAM);
 620         radeon_uvd_force_into_uvd_segment(bo);
 621
 622         r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
 623         if (r)
 624                 goto err;
 625
 626         r = radeon_ib_get(rdev, ring, &ib, NULL, 64);
 627         if (r)
 628                 goto err;
 629
 630         addr = radeon_bo_gpu_offset(bo);
 631         ib.ptr[0] = PACKET0(UVD_GPCOM_VCPU_DATA0, 0);
 632         ib.ptr[1] = addr;
 633         ib.ptr[2] = PACKET0(UVD_GPCOM_VCPU_DATA1, 0);
 634         ib.ptr[3] = addr >> 32;
 635         ib.ptr[4] = PACKET0(UVD_GPCOM_VCPU_CMD, 0);
 636         ib.ptr[5] = 0;
 637         for (i = 6; i < 16; ++i)
 638                 ib.ptr[i] = PACKET2(0);
 639         ib.length_dw = 16;
 640
 641         r = radeon_ib_schedule(rdev, &ib, NULL);
 642         if (r)
 643                 goto err;
 644         ttm_eu_fence_buffer_objects(&ticket, &head, ib.fence);
 645
 646         if (fence)
 647                 *fence = radeon_fence_ref(ib.fence);
 648
 649         radeon_ib_free(rdev, &ib);
 650         radeon_bo_unref(&bo);
 651         return 0;
 652
 653 err:
 654         ttm_eu_backoff_reservation(&ticket, &head);
 655         return r;
 656 }
 657
 658 /* multiple fence commands without any stream commands in between can
 659    crash the vcpu so just try to emmit a dummy create/destroy msg to
 660    avoid this */
 661 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
 662                               uint32_t handle, struct radeon_fence **fence)
 663 {
 664         struct radeon_bo *bo;
 665         uint32_t *msg;
 666         int r, i;
 667
 668         r = radeon_bo_create(rdev, 1024, PAGE_SIZE, true,
 669                              RADEON_GEM_DOMAIN_VRAM, NULL, &bo);
 670         if (r)
 671                 return r;
 672
 673         r = radeon_bo_reserve(bo, false);
 674         if (r) {
 675                 radeon_bo_unref(&bo);
 676                 return r;
 677         }
 678
 679         r = radeon_bo_kmap(bo, (void **)&msg);
 680         if (r) {
 681                 radeon_bo_unreserve(bo);
 682                 radeon_bo_unref(&bo);
 683                 return r;
 684         }
 685
 686         /* stitch together an UVD create msg */
 687         msg[0] = cpu_to_le32(0x00000de4);
 688         msg[1] = cpu_to_le32(0x00000000);
 689         msg[2] = cpu_to_le32(handle);
 690         msg[3] = cpu_to_le32(0x00000000);
 691         msg[4] = cpu_to_le32(0x00000000);
 692         msg[5] = cpu_to_le32(0x00000000);
 693         msg[6] = cpu_to_le32(0x00000000);
 694         msg[7] = cpu_to_le32(0x00000780);
 695         msg[8] = cpu_to_le32(0x00000440);
 696         msg[9] = cpu_to_le32(0x00000000);
 697         msg[10] = cpu_to_le32(0x01b37000);
 698         for (i = 11; i < 1024; ++i)
 699                 msg[i] = cpu_to_le32(0x0);
 700
 701         radeon_bo_kunmap(bo);
 702         radeon_bo_unreserve(bo);
 703
 704         return radeon_uvd_send_msg(rdev, ring, bo, fence);
 705 }
 706
 707 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
 708                                uint32_t handle, struct radeon_fence **fence)
 709 {
 710         struct radeon_bo *bo;
 711         uint32_t *msg;
 712         int r, i;
 713
 714         r = radeon_bo_create(rdev, 1024, PAGE_SIZE, true,
 715                              RADEON_GEM_DOMAIN_VRAM, NULL, &bo);
 716         if (r)
 717                 return r;
 718
 719         r = radeon_bo_reserve(bo, false);
 720         if (r) {
 721                 radeon_bo_unref(&bo);
 722                 return r;
 723         }
 724
 725         r = radeon_bo_kmap(bo, (void **)&msg);
 726         if (r) {
 727                 radeon_bo_unreserve(bo);
 728                 radeon_bo_unref(&bo);
 729                 return r;
 730         }
 731
 732         /* stitch together an UVD destroy msg */
 733         msg[0] = cpu_to_le32(0x00000de4);
 734         msg[1] = cpu_to_le32(0x00000002);
 735         msg[2] = cpu_to_le32(handle);
 736         msg[3] = cpu_to_le32(0x00000000);
 737         for (i = 4; i < 1024; ++i)
 738                 msg[i] = cpu_to_le32(0x0);
 739
 740         radeon_bo_kunmap(bo);
 741         radeon_bo_unreserve(bo);
 742
 743         return radeon_uvd_send_msg(rdev, ring, bo, fence);
 744 }
 745
 746 /**
 747  * radeon_uvd_count_handles - count number of open streams
 748  *
 749  * @rdev: radeon_device pointer
 750  * @sd: number of SD streams
 751  * @hd: number of HD streams
 752  *
 753  * Count the number of open SD/HD streams as a hint for power mangement
 754  */
 755 static void radeon_uvd_count_handles(struct radeon_device *rdev,
 756                                      unsigned *sd, unsigned *hd)
 757 {
 758         unsigned i;
 759
 760         *sd = 0;
 761         *hd = 0;
 762
 763         for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
 764                 if (!atomic_read(&rdev->uvd.handles[i]))
 765                         continue;
 766
 767                 if (rdev->uvd.img_size[i] >= 720*576)
 768                         ++(*hd);
 769                 else
 770                         ++(*sd);
 771         }
 772 }
 773
 774 static void radeon_uvd_idle_work_handler(struct work_struct *work)
 775 {
 776         struct radeon_device *rdev =
 777                 container_of(work, struct radeon_device, uvd.idle_work.work);
 778
 779         if (radeon_fence_count_emitted(rdev, R600_RING_TYPE_UVD_INDEX) == 0) {
 780                 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
 781                         radeon_dpm_enable_uvd(rdev, false);
 782                 } else {
 783                         radeon_set_uvd_clocks(rdev, 0, 0);
 784                 }
 785         } else {
 786                 schedule_delayed_work(&rdev->uvd.idle_work,
 787                                       msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
 788         }
 789 }
 790
 791 void radeon_uvd_note_usage(struct radeon_device *rdev)
 792 {
 793         bool streams_changed = false;
 794         bool set_clocks = !cancel_delayed_work_sync(&rdev->uvd.idle_work);
 795         set_clocks &= schedule_delayed_work(&rdev->uvd.idle_work,
 796                                             msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
 797
 798         if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
 799                 unsigned hd = 0, sd = 0;
 800                 radeon_uvd_count_handles(rdev, &sd, &hd);
 801                 if ((rdev->pm.dpm.sd != sd) ||
 802                     (rdev->pm.dpm.hd != hd)) {
 803                         rdev->pm.dpm.sd = sd;
 804                         rdev->pm.dpm.hd = hd;
 805                         /* disable this for now */
 806                         /*streams_changed = true;*/
 807                 }
 808         }
 809
 810         if (set_clocks || streams_changed) {
 811                 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
 812                         radeon_dpm_enable_uvd(rdev, true);
 813                 } else {
 814                         radeon_set_uvd_clocks(rdev, 53300, 40000);
 815                 }
 816         }
 817 }
 818
 819 static unsigned radeon_uvd_calc_upll_post_div(unsigned vco_freq,
 820                                               unsigned target_freq,
 821                                               unsigned pd_min,
 822                                               unsigned pd_even)
 823 {
 824         unsigned post_div = vco_freq / target_freq;
 825
 826         /* adjust to post divider minimum value */
 827         if (post_div < pd_min)
 828                 post_div = pd_min;
 829
 830         /* we alway need a frequency less than or equal the target */
 831         if ((vco_freq / post_div) > target_freq)
 832                 post_div += 1;
 833
 834         /* post dividers above a certain value must be even */
 835         if (post_div > pd_even && post_div % 2)
 836                 post_div += 1;
 837
 838         return post_div;
 839 }
 840
 841 /**
 842  * radeon_uvd_calc_upll_dividers - calc UPLL clock dividers
 843  *
 844  * @rdev: radeon_device pointer
 845  * @vclk: wanted VCLK
 846  * @dclk: wanted DCLK
 847  * @vco_min: minimum VCO frequency
 848  * @vco_max: maximum VCO frequency
 849  * @fb_factor: factor to multiply vco freq with
 850  * @fb_mask: limit and bitmask for feedback divider
 851  * @pd_min: post divider minimum
 852  * @pd_max: post divider maximum
 853  * @pd_even: post divider must be even above this value
 854  * @optimal_fb_div: resulting feedback divider
 855  * @optimal_vclk_div: resulting vclk post divider
 856  * @optimal_dclk_div: resulting dclk post divider
 857  *
 858  * Calculate dividers for UVDs UPLL (R6xx-SI, except APUs).
 859  * Returns zero on success -EINVAL on error.
 860  */
 861 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
 862                                   unsigned vclk, unsigned dclk,
 863                                   unsigned vco_min, unsigned vco_max,
 864                                   unsigned fb_factor, unsigned fb_mask,
 865                                   unsigned pd_min, unsigned pd_max,
 866                                   unsigned pd_even,
 867                                   unsigned *optimal_fb_div,
 868                                   unsigned *optimal_vclk_div,
 869                                   unsigned *optimal_dclk_div)
 870 {
 871         unsigned vco_freq, ref_freq = rdev->clock.spll.reference_freq;
 872
 873         /* start off with something large */
 874         unsigned optimal_score = ~0;
 875
 876         /* loop through vco from low to high */
 877         vco_min = max(max(vco_min, vclk), dclk);
 878         for (vco_freq = vco_min; vco_freq <= vco_max; vco_freq += 100) {
 879
 880                 uint64_t fb_div = (uint64_t)vco_freq * fb_factor;
 881                 unsigned vclk_div, dclk_div, score;
 882
 883                 do_div(fb_div, ref_freq);
 884
 885                 /* fb div out of range ? */
 886                 if (fb_div > fb_mask)
 887                         break; /* it can oly get worse */
 888
 889                 fb_div &= fb_mask;
 890
 891                 /* calc vclk divider with current vco freq */
 892                 vclk_div = radeon_uvd_calc_upll_post_div(vco_freq, vclk,
 893                                                          pd_min, pd_even);
 894                 if (vclk_div > pd_max)
 895                         break; /* vco is too big, it has to stop */
 896
 897                 /* calc dclk divider with current vco freq */
 898                 dclk_div = radeon_uvd_calc_upll_post_div(vco_freq, dclk,
 899                                                          pd_min, pd_even);
 900                 if (vclk_div > pd_max)
 901                         break; /* vco is too big, it has to stop */
 902
 903                 /* calc score with current vco freq */
 904                 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div);
 905
 906                 /* determine if this vco setting is better than current optimal settings */
 907                 if (score < optimal_score) {
 908                         *optimal_fb_div = fb_div;
 909                         *optimal_vclk_div = vclk_div;
 910                         *optimal_dclk_div = dclk_div;
 911                         optimal_score = score;
 912                         if (optimal_score == 0)
 913                                 break; /* it can't get better than this */
 914                 }
 915         }
 916
 917         /* did we found a valid setup ? */
 918         if (optimal_score == ~0)
 919                 return -EINVAL;
 920
 921         return 0;
 922 }
 923
 924 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
 925                                 unsigned cg_upll_func_cntl)
 926 {
 927         unsigned i;
 928
 929         /* make sure UPLL_CTLREQ is deasserted */
 930         WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK);
 931
 932         mdelay(10);
 933
 934         /* assert UPLL_CTLREQ */
 935         WREG32_P(cg_upll_func_cntl, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK);
 936
 937         /* wait for CTLACK and CTLACK2 to get asserted */
 938         for (i = 0; i < 100; ++i) {
 939                 uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK;
 940                 if ((RREG32(cg_upll_func_cntl) & mask) == mask)
 941                         break;
 942                 mdelay(10);
 943         }
 944
 945         /* deassert UPLL_CTLREQ */
 946         WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK);
 947
 948         if (i == 100) {
 949                 DRM_ERROR("Timeout setting UVD clocks!\n");
 950                 return -ETIMEDOUT;
 951         }
 952
 953         return 0;
 954 }